| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | xilinx: improve specify functionality | Eddie Hung | 2020-02-27 | 5 | -446/+519 | |
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| * | xilinx: use specify blocks in place of abc9_{arrival,required} | Eddie Hung | 2020-02-27 | 1 | -176/+404 | |
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| * | Auto-generate .box/.lut files from specify blocks | Eddie Hung | 2020-02-27 | 7 | -426/+151 | |
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| * | abc9_ops: -prep_box, to be called once | Eddie Hung | 2020-02-27 | 1 | -1/+1 | |
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| * | abc9_ops: -prep_lut and -write_lut to auto-generate LUT library | Eddie Hung | 2020-02-27 | 2 | -4/+85 | |
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| * | xilinx: mark IOBUFDSE3 IOB pin as external | Piotr Binkowski | 2020-02-27 | 2 | -1/+2 | |
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| * | abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr | Eddie Hung | 2020-02-13 | 1 | -11/+12 | |
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| * | abc9: cleanup | Eddie Hung | 2020-02-10 | 1 | -40/+40 | |
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| * | Remove unnecessary comma | Eddie Hung | 2020-02-07 | 1 | -3/+2 | |
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| * | xilinx: Add support for LUT RAM on LUT4-based devices. | Marcin Kościelnicki | 2020-02-07 | 4 | -27/+22 | |
| | | | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549 | |||||
| * | xilinx: Initial support for LUT4 devices. | Marcin Kościelnicki | 2020-02-07 | 3 | -53/+152 | |
| | | | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547 | |||||
| * | xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. | Marcin Kościelnicki | 2020-02-07 | 11 | -1/+370 | |
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| * | xilinx: Add support for Spartan 3A DSP block RAMs. | Marcin Kościelnicki | 2020-02-07 | 3 | -1/+39 | |
| | | | | | Part of #1550 | |||||
| * | Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk | Eddie Hung | 2020-02-06 | 1 | -4/+5 | |
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| * | Fix/cleanup +/xilinx/arith_map.v | Eddie Hung | 2020-02-06 | 1 | -111/+44 | |
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| * | Merge pull request #1661 from YosysHQ/eddie/abc9_required | Eddie Hung | 2020-02-05 | 5 | -142/+375 | |
| |\ | | | | | abc9: add support for required times | |||||
| | * | Merge branch 'eddie/abc9_refactor' into eddie/abc9_required | Eddie Hung | 2020-01-27 | 3 | -126/+89 | |
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| | * \ | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵ | Eddie Hung | 2020-01-15 | 1 | -1/+1 | |
| | |\ \ | | | | | | | | | | | | | eddie/abc9_required | |||||
| | * | | | abc9_ops: generate flop box ids, add abc9_required to FD* cells | Eddie Hung | 2020-01-14 | 1 | -12/+45 | |
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| | * | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵ | Eddie Hung | 2020-01-14 | 2 | -13/+20 | |
| | |\ \ \ | | | | | | | | | | | | | | | | eddie/abc9_required | |||||
| | * \ \ \ | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵ | Eddie Hung | 2020-01-12 | 1 | -1/+0 | |
| | |\ \ \ \ | | | | | | | | | | | | | | | | | | | eddie/abc9_required | |||||
| | | * | | | | Fix abc9_xc7.box comments | Eddie Hung | 2020-01-07 | 1 | -7/+14 | |
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| | | * | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs | Eddie Hung | 2020-01-07 | 6 | -155/+645 | |
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| | | * | | | | | Re-enable &mfs for synth_{ecp5,xilinx} | Eddie Hung | 2020-01-06 | 1 | -1/+0 | |
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| | * | | | | | | Add abc9_required to DSP48E1.{A,B,C,D,PCIN} | Eddie Hung | 2020-01-10 | 1 | -38/+117 | |
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| | * | | | | | | abc9_ops -prep_times: generate flop boxes from abc9_required attr | Eddie Hung | 2020-01-10 | 1 | -61/+0 | |
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| | * | | | | | | Add abc9_ops -check, -prep_times, -write_box for required times | Eddie Hung | 2020-01-10 | 1 | -0/+5 | |
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| | * | | | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵ | Eddie Hung | 2020-01-08 | 5 | -1676/+518 | |
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | eddie/abc9_required | |||||
| | * \ \ \ \ \ \ | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵ | Eddie Hung | 2020-01-06 | 6 | -498/+1003 | |
| | |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | xaig_arrival_required | |||||
| | * | | | | | | | | Consistency | Eddie Hung | 2019-12-27 | 1 | -1/+1 | |
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| | * | | | | | | | | Update some abc9_arrival times, add abc9_required times | Eddie Hung | 2019-12-27 | 3 | -24/+220 | |
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| * | | | | | | | | | Add opt_lut_ins pass. (#1673) | Marcelina Kościelnicka | 2020-02-03 | 1 | -0/+1 | |
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| * | | | | | | | | | xilinx: use RAM32M/RAM64M for memories with two read ports | Marcin Kościelnicki | 2020-02-02 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes inefficient LUT RAM usage for memories with one write and two read ports (commonly used as register files). | |||||
| * | | | | | | | | | synth_xilinx: cleanup help | Eddie Hung | 2020-01-28 | 1 | -6/+4 | |
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| * | | | | | | | | | synth_xilinx: fix help when no active_design; fixes #1664 | Eddie Hung | 2020-01-28 | 1 | -2/+3 | |
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| * | | | | | | | | | xilinx: Add simulation model for DSP48 (Virtex 4). | Marcin Kościelnicki | 2020-01-29 | 6 | -45/+534 | |
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| * | | | | | | | | | Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts | Eddie Hung | 2020-01-28 | 1 | -62/+37 | |
| |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | Unpermute LUT ordering for ice40/ecp5/xilinx | |||||
| | * | | | | | | | | | xilinx/ice40/ecp5: undo permuting LUT masks in lut_map | Eddie Hung | 2020-01-27 | 1 | -62/+37 | |
| | | |_|_|_|_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | Now done in read_aiger | |||||
| * | | | | | | | | | Fix unresolved conflict from #1573 | Eddie Hung | 2020-01-28 | 1 | -1/+1 | |
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| * | | | | | | | | | Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate | N. Engelhardt | 2020-01-28 | 1 | -0/+3 | |
| |\ \ \ \ \ \ \ \ \ | |/ / / / / / / / |/| | | | | | | | | synth_xilinx: error out if tristate without '-iopad' | |||||
| | * | | | | | | | | Duplicate tribuf call, credit to @mwkmwkmwk | Eddie Hung | 2019-12-13 | 1 | -1/+0 | |
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| | * | | | | | | | | synth_xilinx: error out if tristate without '-iopad' | Eddie Hung | 2019-12-12 | 1 | -0/+4 | |
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| * | | | | | | | | | Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0 | Eddie Hung | 2020-01-22 | 1 | -1/+1 | |
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| * | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor | Eddie Hung | 2020-01-21 | 2 | -125/+88 | |
| |\ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|/ |/| | | | | | | | | ||||||
| | * | | | | | | | | Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623 | Eddie Hung | 2020-01-17 | 2 | -119/+82 | |
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| | * | | | | | | | | +/xilinx/arith_map.v fix $lcu rule | Eddie Hung | 2020-01-17 | 1 | -6/+6 | |
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| * | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor | Eddie Hung | 2020-01-15 | 1 | -1/+1 | |
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| | * | | | | | | | Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_W | Miodrag Milanović | 2020-01-15 | 1 | -1/+1 | |
| | |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | synth_xilinx: fix default W value for non-xc7 | |||||
| | | * | | | | | | | synth_xilinx: fix default W value for non-xc7 | Eddie Hung | 2020-01-14 | 1 | -1/+1 | |
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| * | | | | | | | | | Adding (* techmap_autopurge *) to FD* in abc9_map.v | Eddie Hung | 2020-01-14 | 1 | -8/+8 | |
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