iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Merge branch 'master' of https://github.com/cliffordwolf/yosys into ↵	Andrew Zonenberg	2017-08-30	1	-34/+34
\|\ \| \| \| \| \| \|	counter-extraction
\| *	Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're ↵	Andrew Zonenberg	2017-08-28	1	-34/+34
\| \| \| \| \| \| \| \|	multi-edge-sensitive and getting confused.
* \|	extract_counter: Minor changes requested to comply with upstream policy, ↵	Andrew Zonenberg	2017-08-30	2	-4/+4
\| \| \| \| \| \| \| \|	fixed a few typos
* \|	Finished refactoring counter extraction to be nice and generic. Implemented ↵	Andrew Zonenberg	2017-08-28	2	-1/+69
\| \| \| \| \| \| \| \|	techmapping from $__COUNT_ to GP_COUNTx cells.
* \|	Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to ↵	Andrew Zonenberg	2017-08-28	3	-515/+1
\|/ \| \| \|	techmap/ since it's going to become a generic pass
*	Fixed bug causing GP_SPI model to not synthesize	Andrew Zonenberg	2017-08-27	1	-2/+2
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*	Fixed more issues with GreenPAK counter sim models	Andrew Zonenberg	2017-08-15	1	-19/+23
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*	Updated PGEN model to have level triggered reset (matches actual hardware ↵	Andrew Zonenberg	2017-08-15	1	-4/+4
\| \| \| \|	behavior
*	Fixed bug in GP_COUNTx model	Andrew Zonenberg	2017-08-15	1	-7/+12
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*	Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high	Andrew Zonenberg	2017-08-15	1	-47/+47
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*	Merge pull request #381 from azonenberg/countfix	Clifford Wolf	2017-08-14	4	-504/+900
\|\ \| \| \| \|	Added better behavioral models for GreenPAK counters. Refactored cells_sim into two files so analog/mixed signal stuff is separate
\| *	Fixed typo in GP_COUNT8 sim model	Andrew Zonenberg	2017-08-14	1	-1/+1
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\| *	Fixed typo in error message	Andrew Zonenberg	2017-08-14	1	-1/+1
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\| *	Changed LEVEL resets for GP_COUNTx to be properly synthesizeable	Andrew Zonenberg	2017-08-14	1	-48/+60
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\| *	Changed LEVEL resets to be edge triggered anyway	Andrew Zonenberg	2017-08-14	1	-4/+4
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\| *	Added level-triggered reset support to GP_COUNTx simulation models	Andrew Zonenberg	2017-08-14	1	-2/+68
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\| *	Fixed undeclared "count" in GP_COUNT8_ADV	Andrew Zonenberg	2017-08-14	1	-0/+2
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\| *	Fixed undeclared "count" in GP_COUNT14_ADV	Andrew Zonenberg	2017-08-14	1	-0/+2
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\| *	Fixed typo in last commit	Andrew Zonenberg	2017-08-14	1	-3/+3
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\| *	Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock ↵	Andrew Zonenberg	2017-08-14	2	-37/+293
\| \| \| \| \| \| \| \|	divide, but do everything else.
\| *	Fixed typo in COUNT8 model	Andrew Zonenberg	2017-08-14	1	-2/+2
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\| *	Moved GP_POR out of digital cells b/c it has delays	Andrew Zonenberg	2017-08-14	2	-21/+21
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\| *	Improved cells_sim_digital model for GP_COUNT8	Andrew Zonenberg	2017-08-14	2	-40/+75
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\| *	Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital	Andrew Zonenberg	2017-08-14	4	-428/+451
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* \|	coolrunner2: Add INVERT parameter to some BUFGs	Robert Ou	2017-08-14	1	-2/+6
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* \|	coolrunner2: Add FFs with clock enable to cells_sim.v	Robert Ou	2017-08-14	1	-0/+60
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*	Add techlibs/xilinx/lut2lut.v	Clifford Wolf	2017-07-10	2	-0/+66
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*	Fix some c++ clang compiler errors	Clifford Wolf	2017-07-03	1	-3/+3
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*	Apply minor coding style changes to coolrunner2 target	Clifford Wolf	2017-07-03	2	-1/+1
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*	Merge pull request #352 from rqou/master	Clifford Wolf	2017-07-03	6	-0/+645
\|\ \| \| \| \|	Initial Coolrunner-II support
\| *	coolrunner2: Add a few more primitives	Robert Ou	2017-06-25	1	-0/+110
\| \| \| \| \| \| \| \|	These cannot be inferred yet, but add them to cells_sim.v for now
\| *	coolrunner2: Initial mapping of latches	Robert Ou	2017-06-25	4	-0/+63
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\| *	coolrunner2: Initial mapping of DFFs	Robert Ou	2017-06-25	4	-0/+76
\| \| \| \| \| \| \| \| \| \|	All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N (negative-edge triggered)
\| *	coolrunner2: Remove redundant INVERT_PTC	Robert Ou	2017-06-25	2	-4/+1
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\| *	coolrunner2: Remove debug prints	Robert Ou	2017-06-25	1	-2/+0
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\| *	coolrunner2: Correctly handle $_NOT_ after $sop	Robert Ou	2017-06-25	1	-5/+41
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\| *	coolrunner2: Also construct the XOR cell in the macrocell	Robert Ou	2017-06-25	2	-7/+34
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\| *	coolrunner2: Initial techmapping for $sop	Robert Ou	2017-06-25	4	-153/+268
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\| *	coolrunner2: Initial commit	Robert Ou	2017-06-24	3	-0/+223
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* \|	greenpak4_counters: Changed generation of primitive names so that the ↵	Andrew Zonenberg	2017-06-24	1	-3/+21
\|/ \| \| \|	absorbed register's name is included
*	Add dff2ff.v techmap file	Clifford Wolf	2017-05-31	2	-0/+15
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*	greenpak4_counters: Added support for parallel output from GP_COUNTx cells	Andrew Zonenberg	2017-05-22	1	-17/+70
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*	Add $_ANDNOT_ and $_ORNOT_ gates	Clifford Wolf	2017-05-17	1	-0/+38
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*	Squelch trailing whitespace	Larry Doolittle	2017-04-12	8	-126/+126
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*	Add initial support for both MAX10 and Cyclone IV (E\|GX) FPGAs	dh73	2017-04-05	8	-0/+968
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2017-02-25	1	-3/+4
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\| *	Merge https://github.com/cliffordwolf/yosys	Andrew Zonenberg	2017-02-14	1	-2/+0
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\| * \	Merge https://github.com/cliffordwolf/yosys	Andrew Zonenberg	2017-02-08	1	-0/+8
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\| * \| \|	greenpak4: Added POUT to GP_COUNTx cells	Andrew Zonenberg	2017-01-01	1	-3/+4
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* \| \| \|	Add $live and $fair cell types, add support for s_eventually keyword	Clifford Wolf	2017-02-25	1	-0/+16
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