| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | | [wip] sim model testing | David Shah | 2019-08-08 | 4 | -15/+77 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | [wip] sim model testing | David Shah | 2019-08-08 | 3 | -40/+360 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-07 | 1 | -6/+82 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-06 | 1 | -23/+120 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | [wip] DSP48E1 sim model improvements | David Shah | 2019-08-06 | 1 | -8/+75 | |
| |/ / / | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | Trim Y_WIDTH | Eddie Hung | 2019-08-01 | 1 | -5/+3 | |
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| * | | | Add DSP_SIGNEDONLY back | Eddie Hung | 2019-08-01 | 1 | -0/+16 | |
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| * | | | DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH | Eddie Hung | 2019-08-01 | 2 | -5/+12 | |
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| * | | | Change $__softmul back to $mul | Eddie Hung | 2019-08-01 | 1 | -0/+1 | |
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| * | | | Revert "Do not do sign extension in techmap; let packer do it" | Eddie Hung | 2019-08-01 | 1 | -5/+14 | |
| | | | | | | | | | | | | | This reverts commit 595a8f032f1e9db385959f92a4a414a40de291fd. | |||||
| * | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-01 | 6 | -18/+24 | |
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| | * | | RST -> RSTBRST for RAMB8BWER | Eddie Hung | 2019-07-29 | 1 | -3/+3 | |
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| | * | Merge branch 'ZirconiumX-synth_intel_m9k' | Clifford Wolf | 2019-07-25 | 4 | -5/+11 | |
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| | | * | intel: Map M9K BRAM only on families that have it | Dan Ravensloft | 2019-07-23 | 4 | -5/+12 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM. | |||||
| | * | | Merge pull request #1218 from ZirconiumX/synth_intel_iopads | Clifford Wolf | 2019-07-25 | 1 | -8/+8 | |
| | |\ \ | | | | | | | | | intel: Make -noiopads the default | |||||
| | | * | | intel: Make -noiopads the default | Dan Ravensloft | 2019-07-24 | 1 | -8/+8 | |
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| | * | | | Merge pull request #1224 from YosysHQ/xilinx_fix_ff | Eddie Hung | 2019-07-25 | 1 | -2/+2 | |
| | |\ \ \ | | |/ / | |/| | | xilinx: Fix missing cell name underscore in cells_map.v | |||||
| | | * | | xilinx: Fix missing cell name underscore in cells_map.v | David Shah | 2019-07-25 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | Fix B_WIDTH > DSP_B_MAXWIDTH case | Eddie Hung | 2019-08-01 | 1 | -32/+14 | |
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| * | | | | Do not compute sign bit if result is zero | Eddie Hung | 2019-07-31 | 1 | -1/+2 | |
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| * | | | | For signed multipliers, compute sign bit separately... | Eddie Hung | 2019-07-31 | 1 | -23/+42 | |
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| * | | | | Fix spacing | Eddie Hung | 2019-07-26 | 1 | -3/+3 | |
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| * | | | | Add copyright header, comment on cascade | Eddie Hung | 2019-07-24 | 1 | -4/+34 | |
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| * | | | | Typo for Y_WIDTH | Eddie Hung | 2019-07-23 | 1 | -1/+1 | |
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| * | | | | Remove debug | Eddie Hung | 2019-07-22 | 1 | -1/+0 | |
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| * | | | | Rename according to vendor doc TN1295 | Eddie Hung | 2019-07-22 | 1 | -0/+1 | |
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| * | | | | opt and wreduce necessary for -dsp | Eddie Hung | 2019-07-22 | 1 | -2/+4 | |
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| * | | | | Use minimum sized width wires | Eddie Hung | 2019-07-22 | 1 | -7/+13 | |
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| * | | | | Indirection via $__soft_mul | Eddie Hung | 2019-07-19 | 2 | -9/+10 | |
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| * | | | | Do not do sign extension in techmap; let packer do it | Eddie Hung | 2019-07-19 | 1 | -14/+5 | |
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| * | | | | Do not $mul -> $__mul if A and B are less than maxwidth | Eddie Hung | 2019-07-19 | 1 | -1/+3 | |
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| * | | | | Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold | Eddie Hung | 2019-07-19 | 1 | -1/+1 | |
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| * | | | | Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too | Eddie Hung | 2019-07-19 | 1 | -28/+68 | |
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| * | | | | Merge branch 'xc7dsp' into ice40dsp | Eddie Hung | 2019-07-19 | 1 | -1/+1 | |
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| | * | | | | Fix typo in B | Eddie Hung | 2019-07-19 | 1 | -1/+1 | |
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| | * | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-07-18 | 15 | -84/+164 | |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dsp | Eddie Hung | 2019-07-19 | 3 | -7/+239 | |
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| | * | | | | ice40: Fix test_dsp_model.sh | David Shah | 2019-07-19 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | | | ice40/cells_sim.v: Fix sign of J and K partial products | David Shah | 2019-07-19 | 1 | -5/+7 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | | | ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode | David Shah | 2019-07-19 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | | | Add tests for all combinations of A and B signedness for comb mul | Eddie Hung | 2019-07-19 | 2 | -1/+229 | |
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| | * | | | | Don't copy ref if exists already | Eddie Hung | 2019-07-19 | 1 | -1/+3 | |
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| * | | | | Use sign_headroom instead | Eddie Hung | 2019-07-19 | 1 | -4/+4 | |
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| * | | | | Fix SB_MAC sim model -- do not sign extend internal products? | Eddie Hung | 2019-07-18 | 1 | -2/+2 | |
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| * | | | | Add params | Eddie Hung | 2019-07-18 | 1 | -0/+6 | |
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| * | | | | Merge remote-tracking branch 'origin/master' into ice40dsp | Eddie Hung | 2019-07-18 | 1 | -33/+18 | |
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| | * | | | Merge pull request #1208 from ZirconiumX/intel_cleanups | David Shah | 2019-07-18 | 1 | -29/+14 | |
| | |\ \ \ | | | | | | | | | | | Assorted synth_intel cleanups from @bwidawsk | |||||
| | | * | | | synth_intel: Use stringf | Dan Ravensloft | 2019-07-18 | 1 | -7/+2 | |
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| | | * | | | synth_intel: s/not family/no family/ | Dan Ravensloft | 2019-07-18 | 1 | -2/+2 | |
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| | | * | | | intel_synth: Fix help message | Ben Widawsky | 2019-07-18 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cyclonev has been a "supported" family since the initial commit. The old commit message suggested to use a10gx which is incorrect. Aside from the obvious lack of functional change due to this just being a help message, users who were previously using "a10gx" for "cyclonev" will also have no functional change by using "cyclonev" instead. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | |||||
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index : iCE40/yosys | |
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