iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Really permute Xilinx LUT mappings as default LUT6.I5:A6	Eddie Hung	2019-06-18	1	-16/+16
*	Revert "Fix (do not) permute LUT inputs, but permute mux selects"	Eddie Hung	2019-06-18	1	-33/+31
*	Clean up	Eddie Hung	2019-06-18	1	-6/+4
*	Fix (do not) permute LUT inputs, but permute mux selects	Eddie Hung	2019-06-18	1	-31/+33
*	Fix copy-pasta issue	Eddie Hung	2019-06-17	1	-9/+8
*	Permute INIT for +/xilinx/lut_map.v	Eddie Hung	2019-06-17	1	-32/+58
*	Simplify comment	Eddie Hung	2019-06-17	1	-1/+1
*	Update LUT7/8 delays to take account for [ABC]OUTMUX delay	Eddie Hung	2019-06-17	1	-5/+5
*	Try -W 300	Eddie Hung	2019-06-17	1	-1/+2
*	Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O	Eddie Hung	2019-06-15	1	-2/+2
*	As per @daveshah1 remove async DFF timing from xilinx	Eddie Hung	2019-06-14	1	-2/+2
*	Resolve comments from @daveshah1	Eddie Hung	2019-06-14	1	-1/+1
*	Add XC7_WIRE_DELAY macro to synth_xilinx.cc	Eddie Hung	2019-06-14	1	-1/+3
*	Update delays based on SymbiFlow/prjxray-db	Eddie Hung	2019-06-14	1	-12/+13
*	Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}	Eddie Hung	2019-06-14	4	-3/+3
*	Comment out dist RAM boxing on ECP5 for now	Eddie Hung	2019-06-14	1	-1/+1
*	Remove WIP ABC9 flop support	Eddie Hung	2019-06-14	4	-46/+46
*	Make doc consistent	Eddie Hung	2019-06-14	3	-3/+6
*	ecp5: Add abc9 option	David Shah	2019-06-14	6	-70/+184
*	Fix name clash	Eddie Hung	2019-06-13	1	-4/+8
*	Fix LP SB_LUT4 timing	Eddie Hung	2019-06-13	1	-1/+1
*	Move neg-pol to pos-pol mapping from ff_map to cells_map.v	Eddie Hung	2019-06-12	1	-0/+8
*	Reduce diff with master	Eddie Hung	2019-06-12	1	-1/+1
*	Remove abc_flop{,_d} attributes from ice40/cells_sim.v	Eddie Hung	2019-06-12	1	-40/+20
*	Fix spacing	Eddie Hung	2019-06-12	1	-6/+6
*	Remove wide mux inference	Eddie Hung	2019-06-12	4	-194/+3
*	Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"	Eddie Hung	2019-06-12	1	-1/+1
*	Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"	Eddie Hung	2019-06-12	1	-1/+1
*	Add "-W' wire delay arg to abc9, use from synth_xilinx	Eddie Hung	2019-06-11	1	-1/+1
*	Disable dist RAM boxes due to comb loop	Eddie Hung	2019-06-11	1	-2/+2
*	Remove #ifndef ABC	Eddie Hung	2019-06-11	1	-4/+0
*	Revert "Revert "Move ff_map back after ABC for shregmap""	Eddie Hung	2019-06-10	1	-5/+5
*	Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"	Eddie Hung	2019-06-10	1	-2/+2
*	Merge remote-tracking branch 'origin/master' into xc7mux	Eddie Hung	2019-06-10	1	-0/+24
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\| *	ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k	Simon Schubert	2019-06-10	1	-0/+24
* \|	Comment out muxpack (currently broken)	Eddie Hung	2019-06-07	1	-2/+2
* \|	$__XILINX_MUX_ -> $__XILINX_SHIFTX	Eddie Hung	2019-06-06	2	-11/+11
* \|	Fix muxcover and its techmapping	Eddie Hung	2019-06-06	2	-3/+3
* \|	Run muxpack and muxcover in synth_xilinx	Eddie Hung	2019-06-06	2	-1/+18
* \|	Remove abc_flop attributes for now	Eddie Hung	2019-06-06	1	-56/+10
* \|	Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux	Eddie Hung	2019-06-06	1	-0/+15
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\| *	Merge pull request #1073 from whitequark/ecp5-diamond-iob	David Shah	2019-06-06	1	-0/+15
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\| \| *	ECP5: implement all Diamond I/O buffer primitives.	whitequark	2019-06-06	1	-0/+15
* \| \|	Update abc attributes on FD*E_1	Eddie Hung	2019-06-05	1	-6/+26
* \| \|	Cleanup	Eddie Hung	2019-06-05	2	-17/+0
* \| \|	Call shregmap -tech xilinx_static	Eddie Hung	2019-06-05	1	-1/+1
* \| \|	Revert "Move ff_map back after ABC for shregmap"	Eddie Hung	2019-06-05	1	-4/+4
* \| \|	Rename shregmap -tech xilinx -> xilinx_dynamic	Eddie Hung	2019-06-04	1	-2/+2
* \| \|	Add space between -D and _ABC	Eddie Hung	2019-06-04	1	-2/+2
* \| \|	Add (* abc_flop_q *) to brams_bb.v	Eddie Hung	2019-06-04	1	-8/+8