| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | | | | | | | | | | | | | | | | | | xilinx: Test our DSP48A/DSP48A1 simulation models. | Marcin Kościelnicki | 2019-12-23 | 5 | -7/+362 | |
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| * | | | | | | | | | | | | | | | | / / | Add abc9_arrival times for RAM{32,64}M | Eddie Hung | 2019-12-20 | 1 | -24/+10 | |
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| * | | | | | | | | | | | | | | | | | | Add RAM{32,64}M to abc9_map.v | Eddie Hung | 2019-12-20 | 1 | -0/+78 | |
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| * | | | | | | | | | | | | | | | | | | Revert "Optimise write_xaiger" | Eddie Hung | 2019-12-20 | 3 | -15/+0 | |
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| * | | | | | | | | | | | | | | | | | | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup | Eddie Hung | 2019-12-19 | 3 | -0/+15 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimise write_xaiger | |||||
| | * | | | | | | | | | | | | | | | | | | techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger | Eddie Hung | 2019-12-06 | 3 | -0/+15 | |
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| * | | | | | | | | | | | | | | | | | | xilinx: Add simulation models for remaining CLB primitives. | Marcin Kościelnicki | 2019-12-19 | 3 | -156/+210 | |
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| * | | | | | | | | | | | | | | | | | | xilinx_dffopt: Keep order of LUT inputs. | Marcin Kościelnicki | 2019-12-19 | 1 | -16/+30 | |
| | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549 | |||||
| * | | | | | | | | | | | | | | | | | Merge pull request #1563 from YosysHQ/dave/async-prld | David Shah | 2019-12-18 | 2 | -4/+28 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ecp5: Add support for mapping PRLD FFs | |||||
| | * | | | | | | | | | | | | | | | | | ecp5: Add support for mapping PRLD FFs | David Shah | 2019-12-07 | 2 | -4/+28 | |
| | |/ / / / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | | | | | | | | | | | | | | xilinx: Add xilinx_dffopt pass (#1557) | Marcin Kościelnicki | 2019-12-18 | 6 | -22/+389 | |
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| * | | | | | | | | | | | | | | | | | xilinx: Improve flip-flop handling. | Marcin Kościelnicki | 2019-12-18 | 4 | -38/+228 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data. | |||||
| * | | | | | | | | | | | | | | | | | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram | Eddie Hung | 2019-12-16 | 3 | -12/+301 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xilinx: add LUTRAM rules for RAM32M, RAM64M | |||||
| | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into ↵ | Eddie Hung | 2019-12-16 | 1 | -2/+8 | |
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | eddie/xilinx_lutram | |||||
| | | * | | | | | | | | | | | | | | | | | Populate DID/DOD even if unused | Eddie Hung | 2019-12-16 | 1 | -2/+8 | |
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| | * | | | | | | | | | | | | | | | | | | Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q | Eddie Hung | 2019-12-16 | 2 | -6/+6 | |
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| | * | | | | | | | | | | | | | | | | | Disable RAM16X1D match rule; carry-over from LUT4 arches | Eddie Hung | 2019-12-13 | 1 | -6/+9 | |
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| | * | | | | | | | | | | | | | | | | | RAM64M8 to also have [5:0] for address | Eddie Hung | 2019-12-13 | 1 | -8/+8 | |
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| | * | | | | | | | | | | | | | | | | | Add RAM32X6SDP and RAM64X3SDP modes | Eddie Hung | 2019-12-12 | 2 | -8/+120 | |
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| | * | | | | | | | | | | | | | | | | | Fix RAM64M model to have 6 bit address bus | Eddie Hung | 2019-12-12 | 1 | -4/+4 | |
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| | * | | | | | | | | | | | | | | | | | Add memory rules for RAM16X1D, RAM32M, RAM64M | Eddie Hung | 2019-12-12 | 2 | -0/+168 | |
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| * | | | | | | | | | | | | | | | | | Add unconditional match blocks for force RAM | Eddie Hung | 2019-12-16 | 1 | -4/+36 | |
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| * | | | | | | | | | | | | | | | | | Update xc7/xcu bram rules | Eddie Hung | 2019-12-16 | 1 | -8/+4 | |
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| * | | | | | | | | | | | | | | | | | Removing fixed attribute value to !ramstyle rules | Diego H | 2019-12-15 | 1 | -4/+4 | |
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| * | | | | | | | | | | | | | | | | | Merging attribute rules into a single match block; Adding tests | Diego H | 2019-12-15 | 1 | -18/+12 | |
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| * | | | | | | | | | | | | | | | | | Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific | Diego H | 2019-12-13 | 1 | -0/+19 | |
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| * | | | | | | | | | | | | | | | | | Merge pull request #1533 from dh73/bram_xilinx | Eddie Hung | 2019-12-13 | 1 | -6/+9 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |/ / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1 | |||||
| | * | | | | | | | | | | | | | | | | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. | Diego H | 2019-12-12 | 1 | -5/+5 | |
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| | * | | | | | | | | | | | | | | | | Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 | Diego H | 2019-12-12 | 1 | -2/+2 | |
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| | * | | | | | | | | | | | | | | | | Merge https://github.com/YosysHQ/yosys into bram_xilinx | Diego H | 2019-12-12 | 20 | -775/+1170 | |
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| | * | | | | | | | | | | | | | | | | Adjusting Vivado's BRAM min bits threshold for RAMB18E1 | Diego H | 2019-11-27 | 1 | -2/+5 | |
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| * | | | | | | | | | | | | | | | | abc9_map.v: fix Xilinx LUTRAM | Eddie Hung | 2019-12-12 | 1 | -6/+6 | |
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| * | | | | | | | | | | | | | | | Fix bitwidth mismatch; suppresses iverilog warning | Eddie Hung | 2019-12-11 | 1 | -4/+4 | |
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| * | | | | | | | | | | | | | | | Merge pull request #1564 from ZirconiumX/intel_housekeeping | David Shah | 2019-12-11 | 8 | -6/+6 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel housekeeping | |||||
| | * | | | | | | | | | | | | | | | synth_intel: a10gx -> arria10gx | Dan Ravensloft | 2019-12-10 | 5 | -4/+4 | |
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| | * | | | | | | | | | | | | | | | synth_intel: cyclone10 -> cyclone10lp | Dan Ravensloft | 2019-12-10 | 5 | -4/+4 | |
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| * | | | | | | | | | | | | | | | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr | Eddie Hung | 2019-12-09 | 4 | -20/+22 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |/ / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER | |||||
| | * | | | | | | | | | | | | | | ice40_opt to restore attributes/name when unwrapping | Eddie Hung | 2019-12-09 | 1 | -0/+15 | |
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| | * | | | | | | | | | | | | | | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4 | Eddie Hung | 2019-12-09 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | | | ice40_wrapcarry to really preserve attributes via -unwrap option | Eddie Hung | 2019-12-09 | 2 | -19/+1 | |
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| | * | | | | | | | | | | | | | | $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve | Eddie Hung | 2019-12-03 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | name and attr | |||||
| | * | | | | | | | | | | | | | | ice40_opt to ignore (* keep *) -ed cells | Eddie Hung | 2019-12-03 | 1 | -0/+5 | |
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| * | | | | | | | | | | | | | | | xilinx: Add tristate buffer mapping. (#1528) | Marcin Kościelnicki | 2019-12-04 | 2 | -9/+16 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #1225. | |||||
| * | | | | | | | | | | | | | | | xilinx: Add models for LUTRAM cells. (#1537) | Marcin Kościelnicki | 2019-12-04 | 3 | -624/+831 | |
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| * | | | | | | | | | | | | | | Merge pull request #1524 from pepijndevos/gowindffinit | Clifford Wolf | 2019-12-03 | 2 | -112/+270 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Gowin: add and test DFF init values | |||||
| | * | | | | | | | | | | | | | | Use -match-init to not synth contradicting init values | Pepijn de Vos | 2019-12-03 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | | | attempt to fix formatting | Pepijn de Vos | 2019-11-25 | 1 | -154/+154 | |
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| | * | | | | | | | | | | | | | | gowin: add and test dff init values | Pepijn de Vos | 2019-11-25 | 2 | -41/+199 | |
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| * | | | | | | | | | | | | | | | xilinx: Add missing blackbox cell for BUFPLL. | Marcin Kościelnicki | 2019-11-29 | 2 | -0/+21 | |
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| * | | | | | | | | | | | | | | xilinx: Add simulation models for IOBUF and OBUFT. | Marcin Kościelnicki | 2019-11-26 | 3 | -25/+30 | |
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