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* Remove signed from ports in +/xilinx/dsp_map.vEddie Hung2019-08-081-1/+1
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* Rework ice40_dsp to map to SB_MAC16 earlier, and check before packingEddie Hung2019-08-083-1/+36
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* Combine techmap callsEddie Hung2019-08-081-2/+1
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* Move xilinx_dsp to before alumaccEddie Hung2019-08-081-6/+4
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* INMODE is 5 bitsEddie Hung2019-08-081-1/+1
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* Fix copy-pasta typoEddie Hung2019-08-081-2/+2
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* ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinxDavid Shah2019-08-081-11/+11
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Bring up to date with mul2dsp changesDavid Shah2019-08-082-2/+10
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspDavid Shah2019-08-087-125/+278
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| * Run "opt_expr -fine" instead of "wreduce" due to #1213Eddie Hung2019-08-071-2/+1
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| * Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-076-123/+277
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| | * Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixesDavid Shah2019-08-071-101/+244
| | |\ | | | | | | | | ecp5: Make cells_sim.v consistent with nextpnr
| | | * ecp5: Make cells_sim.v consistent with nextpnrDavid Shah2019-08-071-101/+244
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | Merge pull request #1249 from mmicko/anlogic_fixClifford Wolf2019-08-071-16/+8
| | |\ \ | | | |/ | | |/| anlogic : Fix alu mapping
| | | * anlogic : Fix alu mappingMiodrag Milanovic2019-08-031-16/+8
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| | * | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+19
| | |/ | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Merge pull request #1239 from mmicko/mingw_fixClifford Wolf2019-08-023-6/+6
| | |\ | | | | | | | | Fix formatting for msys2 mingw build
| | | * Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-013-6/+6
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* | | | DSP48E1 sim model: add SIMD testsDavid Shah2019-08-083-3/+113
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | DSP48E1 model: test CE inputsDavid Shah2019-08-082-7/+17
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | DSP48E1 sim model: fix seq tests and add preadder testsDavid Shah2019-08-082-6/+91
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | DSP48E1 sim model: seq test workingDavid Shah2019-08-083-16/+60
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | DSP48E1 sim model: Comb, no pre-adder, mode workingDavid Shah2019-08-082-8/+13
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | [wip] sim model testingDavid Shah2019-08-084-15/+77
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | [wip] sim model testingDavid Shah2019-08-083-40/+360
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-071-6/+82
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-23/+120
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-8/+75
|/ / / | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Trim Y_WIDTHEddie Hung2019-08-011-5/+3
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* | | Add DSP_SIGNEDONLY backEddie Hung2019-08-011-0/+16
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* | | DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTHEddie Hung2019-08-012-5/+12
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* | | Change $__softmul back to $mulEddie Hung2019-08-011-0/+1
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* | | Revert "Do not do sign extension in techmap; let packer do it"Eddie Hung2019-08-011-5/+14
| | | | | | | | | | | | This reverts commit 595a8f032f1e9db385959f92a4a414a40de291fd.
* | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-016-18/+24
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| * | RST -> RSTBRST for RAMB8BWEREddie Hung2019-07-291-3/+3
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| * Merge branch 'ZirconiumX-synth_intel_m9k'Clifford Wolf2019-07-254-5/+11
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| | * intel: Map M9K BRAM only on families that have itDan Ravensloft2019-07-234-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM.
| * | Merge pull request #1218 from ZirconiumX/synth_intel_iopadsClifford Wolf2019-07-251-8/+8
| |\ \ | | | | | | | | intel: Make -noiopads the default
| | * | intel: Make -noiopads the defaultDan Ravensloft2019-07-241-8/+8
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| * | | Merge pull request #1224 from YosysHQ/xilinx_fix_ffEddie Hung2019-07-251-2/+2
| |\ \ \ | | |/ / | |/| | xilinx: Fix missing cell name underscore in cells_map.v
| | * | xilinx: Fix missing cell name underscore in cells_map.vDavid Shah2019-07-251-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Fix B_WIDTH > DSP_B_MAXWIDTH caseEddie Hung2019-08-011-32/+14
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* | | | Do not compute sign bit if result is zeroEddie Hung2019-07-311-1/+2
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* | | | For signed multipliers, compute sign bit separately...Eddie Hung2019-07-311-23/+42
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* | | | Fix spacingEddie Hung2019-07-261-3/+3
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* | | | Add copyright header, comment on cascadeEddie Hung2019-07-241-4/+34
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* | | | Typo for Y_WIDTHEddie Hung2019-07-231-1/+1
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* | | | Remove debugEddie Hung2019-07-221-1/+0
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* | | | Rename according to vendor doc TN1295Eddie Hung2019-07-221-0/+1
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* | | | opt and wreduce necessary for -dspEddie Hung2019-07-221-2/+4
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