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* Add iCE40 SB_SPRAM256KA simulation modelClifford Wolf2018-09-101-9/+30
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-2016-54/+54
* ecp5: Fixing miscellaneous sim model issuesDavid Shah2018-07-161-2/+2
* ecp5: Fixing 'X' issues with LUT simulation modelsDavid Shah2018-07-161-6/+19
* ecp5: ECP5 synthesis fixesDavid Shah2018-07-163-15/+32
* ecp5: Adding synchronous set/reset supportDavid Shah2018-07-142-21/+42
* ecp5: Add DRAM match ruleDavid Shah2018-07-131-0/+4
* ecp5: Cells and mappings fixesDavid Shah2018-07-132-5/+5
* ecp5: Fixing arith_mapDavid Shah2018-07-131-4/+5
* ecp5: Initial arith_map implementationDavid Shah2018-07-133-6/+80
* ecp5: Adding basic synth_ecp5 based on synth_ice40David Shah2018-07-133-7/+345
* ecp5: Adding DFF mapsDavid Shah2018-07-132-1/+30
* ecp5: Adding DRAM mapDavid Shah2018-07-133-1/+76
* ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7David Shah2018-07-132-0/+473
* ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LCDavid Shah2018-07-131-2/+6
* Add "synth_ice40 -json"Clifford Wolf2018-06-131-9/+22
* Fix ice40_opt for cases where a port is connected to a signal with width != 1Clifford Wolf2018-06-111-9/+25
* Make -nordff the default in "prep"Clifford Wolf2018-05-301-9/+13
* Avoid mixing module port declaration styles in ice40 cells_sim.vOlof Kindgren2018-05-171-43/+23
* Merge pull request #537 from mithro/yosys-vprClifford Wolf2018-05-044-11/+48
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| * Improving vpr output support.Tim 'mithro' Ansell2018-04-184-7/+40
| * synth_ice40: Rework the vpr blif output slightly.Tim 'mithro' Ansell2018-04-181-4/+8
* | Add "synth_intel --noiopads"Clifford Wolf2018-04-301-2/+11
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* Add "synth_ice40 -nodffe"Clifford Wolf2018-04-161-2/+11
* Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal val...c60k282018-03-3111-178/+233
* coolrunner2: Add an ANDTERM/XOR between chained FFsRobert Ou2018-03-311-0/+58
* coolrunner2: Split multi-bit netsRobert Ou2018-03-311-0/+1
* coolrunner2: Add extraction for TFFsRobert Ou2018-03-313-0/+54
* Squelch trailing whitespace, including meta-whitespaceLarry Doolittle2018-03-114-16/+16
* Add Xilinx RAM64X1D and RAM128X1D simulation modelsClifford Wolf2018-03-074-23/+30
* Add "synth -noshare"Clifford Wolf2018-03-041-2/+11
* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-0/+24
* coolrunner2: Move LOC attributes onto the IO cellsRobert Ou2018-01-171-0/+2
* Add "dffinit -highlow" and fix synth_intelClifford Wolf2018-01-091-1/+1
* Fix minor typo in "prep" help messageClifford Wolf2017-12-191-1/+1
* Fix port names in SB_IO_ODGraham Edgecombe2017-12-101-18/+18
* Remove trailing comma from SB_IO_OD port listGraham Edgecombe2017-12-101-1/+1
* Fix spelling in -vpr help for synth_ice40Tim Ansell2017-12-081-1/+1
* Merge pull request #462 from daveshah1/up5kClifford Wolf2017-11-281-0/+263
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| * Add remaining UltraPlus cells to ice40 techlibDavid Shah2017-11-281-0/+263
* | Merge pull request #455 from daveshah1/up5kClifford Wolf2017-11-181-0/+103
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| * Remove unnecessary keep attributesDavid Shah2017-11-181-5/+5
| * Merge branch 'master' into up5kDavid Shah2017-11-172-5/+29
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| * | Add some UltraPlus cells to ice40 techlibDavid Shah2017-11-161-0/+103
* | | Merge pull request #453 from dh73/masterClifford Wolf2017-11-1810-5/+312
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| * | Initial Cyclone 10 supportdh732017-11-085-1/+308
| * | Organizing Speedster file namesdh732017-11-085-4/+4
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* / Add "synth_ice40 -vpr"Clifford Wolf2017-11-162-5/+29
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* Clean whitespace and permissions in techlibs/intelLarry Doolittle2017-10-0521-190/+190
* Rename "write_verilog -nobasenradix" to "write_verilog -decimal"Clifford Wolf2017-10-031-4/+1
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