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Author
Age
Files
Lines
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-12
13
-30
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+32
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abc9_map.v: fix Xilinx LUTRAM
Eddie Hung
2019-12-12
1
-6
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+6
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Fix bitwidth mismatch; suppresses iverilog warning
Eddie Hung
2019-12-11
1
-4
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+4
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Merge pull request #1564 from ZirconiumX/intel_housekeeping
David Shah
2019-12-11
8
-6
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+6
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synth_intel: a10gx -> arria10gx
Dan Ravensloft
2019-12-10
5
-4
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+4
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synth_intel: cyclone10 -> cyclone10lp
Dan Ravensloft
2019-12-10
5
-4
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+4
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Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
Eddie Hung
2019-12-09
4
-20
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+22
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ice40_opt to restore attributes/name when unwrapping
Eddie Hung
2019-12-09
1
-0
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+15
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Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4
Eddie Hung
2019-12-09
1
-1
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+1
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ice40_wrapcarry to really preserve attributes via -unwrap option
Eddie Hung
2019-12-09
2
-19
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+1
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$__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve
Eddie Hung
2019-12-03
1
-1
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+1
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ice40_opt to ignore (* keep *) -ed cells
Eddie Hung
2019-12-03
1
-0
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+5
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abc9_map.v: fix Xilinx LUTRAM
Eddie Hung
2019-12-12
1
-6
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+6
*
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Fix comment
Eddie Hung
2019-12-09
1
-1
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+1
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-06
7
-745
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+1138
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xilinx: Add tristate buffer mapping. (#1528)
Marcin Kościelnicki
2019-12-04
2
-9
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+16
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xilinx: Add models for LUTRAM cells. (#1537)
Marcin Kościelnicki
2019-12-04
3
-624
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+831
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Merge pull request #1524 from pepijndevos/gowindffinit
Clifford Wolf
2019-12-03
2
-112
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+270
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Use -match-init to not synth contradicting init values
Pepijn de Vos
2019-12-03
1
-1
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+1
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attempt to fix formatting
Pepijn de Vos
2019-11-25
1
-154
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+154
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gowin: add and test dff init values
Pepijn de Vos
2019-11-25
2
-41
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+199
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xilinx: Add missing blackbox cell for BUFPLL.
Marcin Kościelnicki
2019-11-29
2
-0
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+21
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Remove creation of $abc9_control_wire
Eddie Hung
2019-12-06
1
-16
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+6
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abc9 to use mergeability class to differentiate sync/async
Eddie Hung
2019-12-06
1
-12
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+15
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Remove clkpart
Eddie Hung
2019-12-05
1
-4
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+0
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Revert "Special abc9_clock wire to contain only clock signal"
Eddie Hung
2019-12-05
1
-10
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+12
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Missing wire declaration
Eddie Hung
2019-12-04
1
-0
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+1
*
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abc9_map.v to transform INIT=1 to INIT=0
Eddie Hung
2019-12-04
1
-118
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+201
*
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Oh deary me
Eddie Hung
2019-12-04
1
-4
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+4
*
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output reg Q -> output Q to suppress warning
Eddie Hung
2019-12-04
1
-8
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+8
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abc9_map.v to do `zinit' and make INIT = 1'b0
Eddie Hung
2019-12-04
1
-70
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+112
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Add abc9_init wire, attach to abc9_flop cell
Eddie Hung
2019-12-03
1
-2
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+12
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Revert "Add INIT value to abc9_control"
Eddie Hung
2019-12-03
1
-8
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+8
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techmap abc_unmap.v before xilinx_srl -fixed
Eddie Hung
2019-12-03
1
-6
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+5
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Add INIT value to abc9_control
Eddie Hung
2019-12-02
1
-8
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+8
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clkpart -unpart into 'finalize'
Eddie Hung
2019-11-28
1
-3
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+4
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ean call after abc{,9}
Eddie Hung
2019-11-27
1
-1
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+2
*
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Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff
Eddie Hung
2019-11-27
3
-25
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+30
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xilinx: Add simulation models for IOBUF and OBUFT.
Marcin Kościelnicki
2019-11-26
3
-25
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+30
*
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Move 'clean' from map_luts to finalize
Eddie Hung
2019-11-26
1
-1
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+1
*
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-11-25
3
-5
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+11
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clkbufmap: Add support for inverters in clock path.
Marcin Kościelnicki
2019-11-25
1
-1
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+5
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xilinx: Use INV instead of LUT1 when applicable
Marcin Kościelnicki
2019-11-25
1
-2
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+6
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coolrunner2: remove spurious log_pop() call, fixes #1463
Martin Pietryka
2019-11-23
1
-2
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+0
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Special abc9_clock wire to contain only clock signal
Eddie Hung
2019-11-25
1
-12
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+10
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For abc9, run clkpart before ff_map and after abc9
Eddie Hung
2019-11-23
1
-0
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+2
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Merge branch 'eddie/clkpart' into xaig_dff
Eddie Hung
2019-11-22
1
-0
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+2
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gowin: Add missing .gitignore entries
Marcin Kościelnicki
2019-11-22
1
-0
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+2
*
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Merge branch 'eddie/xaig_dff_adff' into xaig_dff
Eddie Hung
2019-11-21
1
-12
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+16
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Do not drop async control signals in abc_map.v
Eddie Hung
2019-11-19
1
-12
/
+16
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