aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs
Commit message (Collapse)AuthorAgeFilesLines
...
| * | | | set undriven pads to zeroPepijn de Vos2019-09-041-0/+1
| | | | |
| * | | | Merge remote-tracking branch 'diego/gowin'Pepijn de Vos2019-09-042-2/+2
| |\ \ \ \
| | * | | | Updating gowinDiego H2019-09-022-2/+2
| | | | | |
| * | | | | gowin: add splitnets to appease the PnRPepijn de Vos2019-09-041-0/+1
| | | | | |
* | | | | | xilinx: Add simulation models for MULT18X18* and DSP48A*.Marcin Kościelnicki2019-11-193-132/+516
| |_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds simulation models for the following primitives: - MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3) - MULT18X18SIO (Spartan 3E, Spartan 3A) - DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1 - DSP48A1 (Spartan 6)
* | | | | ecp5: Use new autoname pass for better cell/net namesDavid Shah2019-11-151-0/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | Merge pull request #1490 from YosysHQ/clifford/autonameClifford Wolf2019-11-141-0/+1
|\ \ \ \ \ | | | | | | | | | | | | Add "autoname" pass and use it in "synth_ice40"
| * | | | | Add "autoname" pass and use it in "synth_ice40"Clifford Wolf2019-11-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Merge pull request #1465 from YosysHQ/dave/ice40_timing_simClifford Wolf2019-11-141-14/+436
|\ \ \ \ \ \ | |/ / / / / |/| | | | | ice40: Support for post-place-and-route timing simulations
| * | | | | ice40: Add post-pnr ICESTORM_RAM model and fix FFsDavid Shah2019-10-231-2/+340
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | ice40: Support for post-pnr timing simulationDavid Shah2019-10-231-12/+96
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | Do not map $eq and $ne in cmp2lut, only proper arithmetic cmpClifford Wolf2019-11-111-1/+1
| |_|_|_|/ |/| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | synth_xilinx: Merge blackbox primitive libraries.Marcin Kościelnicki2019-11-0611-23234/+29820
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First, there are no longer separate cell libraries for xc6s/xc7/xcu. Manually instantiating a primitive for a "wrong" family will result in yosys passing it straight through to the output, and it will be either upgraded or rejected by the P&R tool. Second, the blackbox library is expanded to cover many more families: everything from Spartan 3 up is included. Primitives for Virtex and Virtex 2 are listed in the Python file as well if we ever want to include them, but that would require having two different ISE versions (10.1 and 14.7) available when running cells_xtra.py, and so is probably more trouble than it's worth. Third, the blockram blackboxes are no longer in separate files — there is no practical reason to do so (from synthesis PoV, they are no different from any other cells_xtra blackbox), and they needlessly complicated the flow (among other things, merging them allows the user to use eg. Series 7 primitives and have them auto-upgraded to Ultrascale). Last, since xc5v logic synthesis appears to work reasonably well (the only major problem is lack of blockram inference support), xc5v is now an accepted setting for the -family option.
* | | | | xilinx: Add URAM288 mapping for xcupDavid Shah2019-10-235-2/+92
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | xilinx: Add support for UltraScale[+] BRAM mappingDavid Shah2019-10-237-416/+1062
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | xilinx: Support multiplier mapping for all families.Marcin Kościelnicki2019-10-229-9/+269
| | | | | | | | | | | | | | | | | | | | | | | | | This supports several older families that are not yet supported for actual logic synthesis — the intention is to add them soon.
* | | | | Merge pull request #1452 from nakengelhardt/fix_dsp_mem_regClifford Wolf2019-10-222-0/+2
|\ \ \ \ \ | |_|_|_|/ |/| | | | Call memory_dff before DSP mapping to reserve registers (fixes #1447)
| * | | | Call memory_dff before DSP mapping to reserve registers (fixes #1447)N. Engelhardt2019-10-172-0/+2
| | | | |
* | | | | ecp5: Pass -nomfs to abc9David Shah2019-10-201-2/+2
| |/ / / |/| | | | | | | | | | | | | | | | | | | Fixes #1459 Signed-off-by: David Shah <dave@ds0.me>
* | | | Makefile: don't assume python is called `python3`Sean Cross2019-10-194-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross <sean@xobs.io>
* | | | Merge branch 'master' into mmicko/efinixMiodrag Milanović2019-10-1837-474/+305
|\| | |
| * | | ecp5: Add ECLKBRIDGECS blackboxDavid Shah2019-10-111-0/+7
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | ecp5: Add attrmvcp to copy syn_useioff to driving FFDavid Shah2019-10-101-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | ecp5: Set syn_useioff on IO FFs to enable packingDavid Shah2019-10-101-8/+8
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | xilinx: Add simulation model for IBUFG.Marcin Kościelnicki2019-10-105-33/+14
| | | |
| * | | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9Eddie Hung2019-10-0831-228/+236
| |\ \ \ | | | | | | | | | | Rename abc_* names/attributes to more precisely be abc9_*
| | * \ \ Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-044-181/+9
| | |\ \ \
| | * | | | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-0431-227/+235
| | | | | |
| * | | | | Add comment on why partial multipliers are 18x18Eddie Hung2019-10-041-4/+8
| | | | | |
| * | | | | Fix typo in check_label()Eddie Hung2019-10-041-1/+1
| | |/ / / | |/| | |
| * | | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-041-2/+6
| | | | |
| * | | | Remove DSP48E1 from *_cells_xtra.vEddie Hung2019-10-043-178/+2
| |/ / /
| * | | Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-045-31/+4
| | | |
| * | | OopsEddie Hung2019-10-041-1/+1
| | | |
| * | | Ohmilord this wasn't added all this time!?!Eddie Hung2019-10-041-0/+29
| | | |
* | | | FF should be initialized to 0Miodrag Milanovic2019-10-041-1/+3
| | | |
* | | | Add missing latch mappingMiodrag Milanovic2019-10-041-0/+12
|/ / /
* | | ecp5: Fix shuffle_enable portDavid Shah2019-10-011-2/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ecp5: Add support for mapping 36-bit wide PDP BRAMsDavid Shah2019-10-016-1/+183
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}Eddie Hung2019-09-306-122/+46
| | |
* | | synth_xilinx: Support latches, remove used-up FF init values.Marcin Kościelnicki2019-09-302-2/+76
| | | | | | | | | | | | Fixes #1387.
* | | Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-2919-31/+3395
|\ \ \ | | | | | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5)
| * | | Re-orderEddie Hung2019-09-272-2/+2
| | | |
| * | | Missing (* mul2dsp *) for sliceBEddie Hung2019-09-271-2/+2
| | | |
| * | | Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run onceEddie Hung2019-09-261-9/+4
| | | |
| * | | TypoEddie Hung2019-09-261-1/+1
| | | |
| * | | select onceEddie Hung2019-09-262-8/+12
| | | |
| * | | Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-263-38/+14
| | | |
| * | | mul2dsp.v slice namesEddie Hung2019-09-251-5/+5
| | | |
| * | | Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicitEddie Hung2019-09-251-3/+1
| | | |
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 09:51:33 +0000