Commit message (Collapse) | Author | Age | Files | Lines | |
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* | fix argument order for macOS compatibility | N. Engelhardt | 2020-03-18 | 1 | -3/+3 |
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* | Merge pull request #1759 from zeldin/constant_with_comment_redux | Miodrag Milanović | 2020-03-14 | 2 | -0/+24 |
|\ | | | | | refixed parsing of constant with comment between size and value | ||||
| * | Add regression tests for new handling of comments in constants | Marcus Comstedt | 2020-03-14 | 2 | -0/+24 |
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* | | Merge pull request #1754 from boqwxp/precise_locations | Miodrag Milanović | 2020-03-14 | 1 | -0/+8 |
|\ \ | | | | | | | Set AST node source location in more parser rules. | ||||
| * | | verilog: add test | Eddie Hung | 2020-03-11 | 1 | -0/+8 |
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* | | | Added back tests for logger | Miodrag Milanovic | 2020-03-13 | 4 | -0/+24 |
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* | | Merge pull request #1721 from YosysHQ/dave/tribuf-unused | David Shah | 2020-03-10 | 1 | -0/+14 |
|\ \ | |/ |/| | deminout: Don't demote inouts with unused bits | ||||
| * | deminout: Don't demote inouts with unused bits | David Shah | 2020-03-04 | 1 | -0/+14 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | Fix partsel expr bit width handling and add test case | Claire Wolf | 2020-03-08 | 1 | -0/+4 |
| | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
* | | rpc test: make frontend listen before launching yosys & introduce safeguard ↵ | N. Engelhardt | 2020-03-06 | 1 | -1/+2 |
| | | | | | | | | if yosys errors | ||||
* | | tests: extend tests/arch/run-tests.sh for defines | Eddie Hung | 2020-03-05 | 1 | -3/+14 |
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* | | Merge pull request #1718 from boqwxp/precise_locations | Claire Wolf | 2020-03-03 | 2 | -4/+4 |
|\ \ | | | | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes. | ||||
| * | | Change attribute search value to specify precise location instead of simple ↵ | Alberto Gonzalez | 2020-02-24 | 1 | -2/+2 |
| | | | | | | | | | | | | line number. | ||||
| * | | Change attribute search value to specify precise location instead of simple ↵ | Alberto Gonzalez | 2020-02-24 | 1 | -2/+2 |
| |/ | | | | | | | line number. | ||||
* | | Merge pull request #1519 from YosysHQ/eddie/submod_po | Claire Wolf | 2020-03-03 | 1 | -0/+124 |
|\ \ | | | | | | | submod: several bugfixes | ||||
| * \ | Merge branch 'master' into eddie/submod_po | Eddie Hung | 2020-02-01 | 83 | -175/+2399 |
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| * | | | Add a quick testcase for unknown modules as inout | Eddie Hung | 2019-12-09 | 1 | -2/+24 |
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* | | | | iopadmap: Look harder for already-present buffers. (#1731) | Marcelina Kościelnicka | 2020-03-02 | 1 | -2/+21 |
| | | | | | | | | | | | | | | | | | | | | iopadmap: Look harder for already-present buffers. Fixes #1720. | ||||
* | | | | Merge pull request #1724 from YosysHQ/eddie/abc9_specify | Eddie Hung | 2020-03-02 | 6 | -7/+10 |
|\ \ \ \ | | | | | | | | | | | abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries | ||||
| * | | | | Revert "Fix tests/arch/xilinx/fsm.ys to count flops only" | Eddie Hung | 2020-02-27 | 1 | -3/+9 |
| | | | | | | | | | | | | | | | | | | | | This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5. | ||||
| * | | | | Cleanup tests | Eddie Hung | 2020-02-27 | 2 | -1/+1 |
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| * | | | | Update bug1630.ys to use -lut 4 instead of lut file | Eddie Hung | 2020-02-27 | 1 | -1/+1 |
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| * | | | | Fix tests/arch/xilinx/fsm.ys to count flops only | Eddie Hung | 2020-02-27 | 1 | -9/+3 |
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| * | | | | Update simple_abc9 tests | Eddie Hung | 2020-02-27 | 3 | -5/+8 |
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* / | | | ast: fixes #1710; do not generate RTLIL for unreachable ternary | Eddie Hung | 2020-02-27 | 1 | -0/+30 |
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* | | | Merge pull request #1703 from YosysHQ/eddie/specify_improve | Eddie Hung | 2020-02-21 | 2 | -3/+47 |
|\ \ \ | | | | | | | | | Improve specify parser | ||||
| * | | | clean: ignore specify-s inside cells when determining whether to keep | Eddie Hung | 2020-02-19 | 1 | -1/+20 |
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| * | | | verilog: ignore ranges too without -specify | Eddie Hung | 2020-02-13 | 1 | -0/+7 |
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| * | | | verilog: improve specify support when not in -specify mode | Eddie Hung | 2020-02-13 | 2 | -3/+1 |
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| * | | | verilog: ignore '&&&' when not in -specify mode | Eddie Hung | 2020-02-13 | 1 | -0/+6 |
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| * | | | specify: system timing checks to accept min:typ:max triple | Eddie Hung | 2020-02-13 | 1 | -0/+7 |
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| * | | | verilog: fix $specify3 check | Eddie Hung | 2020-02-13 | 1 | -0/+7 |
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* | | | | Merge pull request #1642 from jjj11x/jjj11x/sv-enum | Claire Wolf | 2020-02-20 | 4 | -1/+68 |
|\ \ \ \ | | | | | | | | | | | Enum support | ||||
| * | | | | add attributes for enumerated values in ilang | Jeff Wang | 2020-02-17 | 2 | -3/+3 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files | ||||
| * | | | | scoped enum tests | Jeff Wang | 2020-01-16 | 1 | -1/+13 |
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| * | | | | enum in package test | Jeff Wang | 2020-01-16 | 1 | -0/+3 |
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| * | | | | simple enum test | Jeff Wang | 2020-01-16 | 2 | -0/+52 |
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* | | | | | tests/aiger: Add missing .gitignore | Marcin Kościelnicki | 2020-02-15 | 1 | -0/+2 |
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* | | | | | Merge pull request #1701 from nakengelhardt/rpc-test | Miodrag Milanović | 2020-02-14 | 3 | -7/+7 |
|\ \ \ \ \ | | | | | | | | | | | | | make rpc frontend unix socket test less fragile | ||||
| * | | | | | make rpc frontend unix socket test less fragile | N. Engelhardt | 2020-02-13 | 3 | -7/+7 |
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* | | | | | Fine tune #1699 tests | Eddie Hung | 2020-02-13 | 1 | -14/+14 |
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* | | | | | iopadmap: move \init attributes from outpad output to its input | Eddie Hung | 2020-02-13 | 1 | -0/+37 |
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* | | | | Merge pull request #1679 from thasti/delay-parsing | N. Engelhardt | 2020-02-13 | 1 | -0/+5 |
|\ \ \ \ | | | | | | | | | | | Fix crash on wire declaration with delay | ||||
| * | | | | add testcase for #1614 | Stefan Biereigel | 2020-02-03 | 1 | -0/+5 |
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* | | | | Merge pull request #1670 from rodrigomelo9/master | Eddie Hung | 2020-02-10 | 4 | -0/+137 |
|\ \ \ \ | | | | | | | | | | | $readmem[hb] file inclusion is now relative to the Verilog file | ||||
| * | | | | Added 'set -e' into tests/memfile/run-test.sh | Rodrigo Alejandro Melo | 2020-02-06 | 1 | -0/+20 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also added two checks for situations where the execution must fail. Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | ||||
| * | | | | Merge branch 'master' into master | Rodrigo A. Melo | 2020-02-03 | 4 | -4/+84 |
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| * \ \ \ \ | Merge branch 'master' of https://github.com/YosysHQ/yosys | Rodrigo Alejandro Melo | 2020-02-03 | 2 | -0/+136 |
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Solved a conflict into the CHANGELOG Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | ||||
| * | | | | | | Removed 'synth' into tests/memfile/run-test.sh | Rodrigo Alejandro Melo | 2020-02-02 | 1 | -8/+8 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | ||||
| * | | | | | | Added content1.dat into tests/memfile | Rodrigo Alejandro Melo | 2020-02-02 | 2 | -21/+81 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modified run-test.sh to use it. Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> |