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author | fishsoupisgood <github@madingley.org> | 2018-05-17 09:17:21 +0100 |
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committer | fishsoupisgood <github@madingley.org> | 2018-05-17 09:17:21 +0100 |
commit | 0780df86a9ec88bf8810f7fef1d241030dc1b655 (patch) | |
tree | 616b7af709d554a64de9c6077e34c8d64919c875 /dflipflop.vhd | |
download | rob_spdif-0780df86a9ec88bf8810f7fef1d241030dc1b655.tar.gz rob_spdif-0780df86a9ec88bf8810f7fef1d241030dc1b655.tar.bz2 rob_spdif-0780df86a9ec88bf8810f7fef1d241030dc1b655.zip |
first version for rob - supports only 44.1kHz
Diffstat (limited to 'dflipflop.vhd')
-rw-r--r-- | dflipflop.vhd | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/dflipflop.vhd b/dflipflop.vhd new file mode 100644 index 0000000..c83d1d3 --- /dev/null +++ b/dflipflop.vhd @@ -0,0 +1,35 @@ + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.numeric_std.all; + +entity dflipflop is + port + ( + n_reset : in std_logic; + clk : in std_logic; + d : in std_logic; + q : out std_logic + ); +end dflipflop; + + +architecture rtl of dflipflop is + signal qish : + std_logic; +begin + + process(clk, d, n_reset) + begin + if n_reset = '0' then + qish <= '0'; + elsif RISING_EDGE(clk) then + qish <= d; + end if; + end process; + + q <= qish; +end rtl; + |