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author | Thomas Langer <thomas.langer@lantiq.com> | 2008-11-19 17:40:05 +0000 |
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committer | Thomas Langer <thomas.langer@lantiq.com> | 2008-11-19 17:40:05 +0000 |
commit | 8294879df7f852871fd030d674943453b3096bc2 (patch) | |
tree | 6318ca0953b9ec71c18ecb46f81c874dfe799b1a /package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e111.h | |
parent | e1e65079b407832393ffb37934d74df83223d05a (diff) | |
download | upstream-8294879df7f852871fd030d674943453b3096bc2.tar.gz upstream-8294879df7f852871fd030d674943453b3096bc2.tar.bz2 upstream-8294879df7f852871fd030d674943453b3096bc2.zip |
cleanup uboot package
SVN-Revision: 13291
Diffstat (limited to 'package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e111.h')
-rw-r--r-- | package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e111.h | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e111.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e111.h new file mode 100644 index 0000000000..b655ca2898 --- /dev/null +++ b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e111.h @@ -0,0 +1,50 @@ +/* Settings for Denali DDR SDRAM controller */ +/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ +#define MC_DC0_VALUE 0x1B1B +#define MC_DC1_VALUE 0x0 +#define MC_DC2_VALUE 0x0 +#define MC_DC3_VALUE 0x0 +#define MC_DC4_VALUE 0x0 +#define MC_DC5_VALUE 0x200 +#define MC_DC6_VALUE 0x605 +#define MC_DC7_VALUE 0x303 +#define MC_DC8_VALUE 0x102 +#define MC_DC9_VALUE 0x70a +#define MC_DC10_VALUE 0x203 +#define MC_DC11_VALUE 0xc02 +#define MC_DC12_VALUE 0x1C8 +#define MC_DC13_VALUE 0x1 +#define MC_DC14_VALUE 0x0 +#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ +#define MC_DC16_VALUE 0xC800 +#define MC_DC17_VALUE 0xd +#define MC_DC18_VALUE 0x300 +#define MC_DC19_VALUE 0x200 +#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */ +#define MC_DC21_VALUE 0x1800 +#define MC_DC22_VALUE 0x1818 +#define MC_DC23_VALUE 0x0 +#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ +#define MC_DC25_VALUE 0x0 +#define MC_DC26_VALUE 0x0 +#define MC_DC27_VALUE 0x0 +#define MC_DC28_VALUE 0x510 +#define MC_DC29_VALUE 0x2d89 +#define MC_DC30_VALUE 0x8300 +#define MC_DC31_VALUE 0x0 +#define MC_DC32_VALUE 0x0 +#define MC_DC33_VALUE 0x0 +#define MC_DC34_VALUE 0x0 +#define MC_DC35_VALUE 0x0 +#define MC_DC36_VALUE 0x0 +#define MC_DC37_VALUE 0x0 +#define MC_DC38_VALUE 0x0 +#define MC_DC39_VALUE 0x0 +#define MC_DC40_VALUE 0x0 +#define MC_DC41_VALUE 0x0 +#define MC_DC42_VALUE 0x0 +#define MC_DC43_VALUE 0x0 +#define MC_DC44_VALUE 0x0 +#define MC_DC45_VALUE 0x500 +//#define MC_DC45_VALUE 0x400 +#define MC_DC46_VALUE 0x0 |