ath79: add kernel 5.10 support

This adds Kernel 5.10 support for the generic, nand and tiny subtargets.

The following patch is not contained, as it needs to be reworked:
platform/920-mikrotik-rb4xx.patch

Tested-on:
 - Siemens WS-AP3610
 - Enterasys WS-AP3710
 - Aerohive HiveAP 121
 - TP-Link TL-WA901 v2
 - TP-Link TL-WR741 v1

Signed-off-by: David Bauer <mail@david-bauer.net>

1 files changed, 85 insertions, 0 deletions

diff --git a/target/linux/ath79/patches-5.10/0053-mtd-spi-nor-use-4-bit-BP-for-large-Macronix-flash.patch b/target/linux/ath79/patches-5.10/0053-mtd-spi-nor-use-4-bit-BP-for-large-Macronix-flash.patch
new file mode 100644
index 0000000000..bb393e52eb
--- /dev/null
+++ b/target/linux/ath79/patches-5.10/0053-mtd-spi-nor-use-4-bit-BP-for-large-Macronix-flash.patch
@@ -0,0 +1,85 @@
+From 59f88b8d4447be809d0b5e7a283290d06848d3bc Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Sun, 25 Oct 2020 01:14:22 +0200
+Subject: [PATCH 2/2] mtd: spi-nor: use 4 bit BP for large Macronix flash
+
+Macronix SPI-NOR chips with 128 or more 64k blocks have 4 block
+protection bits in their status register. Add the corresponding
+flag in order to clear these bits when unloking the flash.
+
+Otherwise, the flash might not be writable depending on the state the
+bootloader left the flash in.
+
+Fixes commit 62593cf40b23 ("mtd: spi-nor: refactor block protection functions")
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ drivers/mtd/spi-nor/macronix.c | 31 ++++++++++++++++++-------------
+ 1 file changed, 18 insertions(+), 13 deletions(-)
+
+--- a/drivers/mtd/spi-nor/macronix.c
++++ b/drivers/mtd/spi-nor/macronix.c
+@@ -50,8 +50,8 @@ static const struct flash_info macronix_
+ 	{ "mx25u4035",   INFO(0xc22533, 0, 64 * 1024,   8, SECT_4K) },
+ 	{ "mx25u8035",   INFO(0xc22534, 0, 64 * 1024,  16, SECT_4K) },
+ 	{ "mx25u6435f",  INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
+-	{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, SECT_4K) },
+-	{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
++	{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_4BIT_BP) },
++	{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, SPI_NOR_4BIT_BP) },
+ 	{ "mx25r1635f",  INFO(0xc22815, 0, 64 * 1024,  32,
+ 			      SECT_4K | SPI_NOR_DUAL_READ |
+ 			      SPI_NOR_QUAD_READ) },
+@@ -60,36 +60,41 @@ static const struct flash_info macronix_
+ 			      SPI_NOR_QUAD_READ) },
+ 	{ "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256,
+ 			      SECT_4K | SPI_NOR_DUAL_READ |
+-			      SPI_NOR_QUAD_READ) },
++			      SPI_NOR_QUAD_READ | SPI_NOR_4BIT_BP) },
+ 	{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512,
+-			      SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
++			      SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
++			      SPI_NOR_4BIT_BP)
+ 		.fixups = &mx25l25635_fixups },
+ 	{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512,
+-			      SECT_4K | SPI_NOR_4B_OPCODES) },
++			      SECT_4K | SPI_NOR_4B_OPCODES |
++			      SPI_NOR_4BIT_BP) },
+ 	{ "mx25u51245g", INFO(0xc2253a, 0, 64 * 1024, 1024,
+ 			      SECT_4K | SPI_NOR_DUAL_READ |
+-			      SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
++			      SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
++			      SPI_NOR_4BIT_BP) },
+ 	{ "mx25v8035f",  INFO(0xc22314, 0, 64 * 1024,  16,
+ 			      SECT_4K | SPI_NOR_DUAL_READ |
+ 			      SPI_NOR_QUAD_READ) },
+-	{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
++	{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, SPI_NOR_4BIT_BP) },
+ 	{ "mx25l51245g", INFO(0xc2201a, 0, 64 * 1024, 1024,
+ 			      SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+-			      SPI_NOR_4B_OPCODES) },
++			      SPI_NOR_4B_OPCODES | SPI_NOR_4BIT_BP) },
+ 	{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024,
+ 			      SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+-			      SPI_NOR_4B_OPCODES) },
++			      SPI_NOR_4B_OPCODES | SPI_NOR_4BIT_BP) },
+ 	{ "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024,
+ 			      SECT_4K | SPI_NOR_DUAL_READ |
+-			      SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
++			      SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
++			      SPI_NOR_4BIT_BP) },
+ 	{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048,
+ 			      SECT_4K | SPI_NOR_DUAL_READ |
+-			      SPI_NOR_QUAD_READ) },
++			      SPI_NOR_QUAD_READ | SPI_NOR_4BIT_BP) },
+ 	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048,
+-			      SPI_NOR_QUAD_READ) },
++			      SPI_NOR_QUAD_READ | SPI_NOR_4BIT_BP) },
+ 	{ "mx66u2g45g",	 INFO(0xc2253c, 0, 64 * 1024, 4096,
+ 			      SECT_4K | SPI_NOR_DUAL_READ |
+-			      SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
++			      SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
++			      SPI_NOR_4BIT_BP) },
+ };
+ 
+ static void macronix_default_init(struct spi_nor *nor)