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authorNico Huber <nico.h@gmx.de>2018-03-13 18:14:52 +0100
committerNico Huber <nico.h@gmx.de>2018-10-03 13:14:57 +0000
commit86bddb5d52659f23531282db137350cbf7fb5992 (patch)
tree2f2b2da3f475065c9e86218b79ded18547c6b2c3 /flashchips.c
parent57dbd64b33143964bb8eb91d33d72a2147f0091c (diff)
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Enable 4BA mode for Spansion 25FL256S
4BA mode is entered by setting bit 7 for the extended address register. Change-Id: I807bf55d65763a9f48a6a3377f14f4e5288a7a4c Signed-off-by: Nico Huber <nico.h@gmx.de> Tested-by: Michael Fuckner <michael@fuckner.net> Reviewed-on: https://review.coreboot.org/25133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'flashchips.c')
-rw-r--r--flashchips.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/flashchips.c b/flashchips.c
index 78538492..c75e0b8a 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -12524,7 +12524,7 @@ const struct flashchip flashchips[] = {
.total_size = 32768,
.page_size = 256,
/* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_EXT_ADDR,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_EAR7,
.tested = TEST_OK_PREW,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,