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* tests: Make libusb conditional dependency for unit testsAnastasia Klimchuk2022-07-103-6/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unit tests had an unconditional dependency on libusb and this was a) strictly speaking not needed, b) blocking one build system effort. This patch is a temporary solution to unblock one build system effort, specifically CB:63724. It creates a condition so that libusb is only included when it is required, not always. This workaround is based on the fact that at the moment only 2 lifecycle unit tests are using libusb symbols: dediprog and raiden_debug. BUG=b:237606255 TEST=the following scenarios run tests successfully 1) dediprog and raiden_debug programmers enabled, libusb.h present result: all test run and pass 2) dediprog disabled, libusb.h present result: dediprog test skipped, all other tests run and pass 3) dediprog and raiden_debug both disabled, libusb.h changed to libusbabcd.h result: dediprog and raiden_debug tests are skipped, all other tests run and pass Change-Id: Iec8a1826951fd6ae586e90fde1a55170e7de41a8 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Thomas Heijligen <src@posteo.de>
* tests: Split lifecycle test file into per-programmer filesAnastasia Klimchuk2022-07-109-383/+502
| | | | | | | | | | | | | | | | | | | This patch creates individual files for each programmer's lifecycle tests. Common functions that are reusable for all tests are gathered in lifecycle.c. Each individual file needs to include lifecycle.h BUG=b:237606255 TEST=ninja test Change-Id: If2307699dcbb3a085b91a2dcd41156e6fd07f812 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65543 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tests: Add lifecycle function prototypes into lifecycle.h headerAnastasia Klimchuk2022-07-102-7/+6
| | | | | | | | | | | | | | | Lifecycle functions will be used in all lifecycle tests and need to be available by including lifecycle.h BUG=b:237606255 TEST=ninja test Change-Id: Ic4e9defe16c535c9384c1304c1cad2f5b84294c9 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Thomas Heijligen <src@posteo.de>
* tests: Create lifecycle.h and gather includes and macro thereAnastasia Klimchuk2022-07-102-12/+33
| | | | | | | | | | | | | | | | | | New header file lifecycle.h need to gather all things shared among lifecycle tests. This is one step to the goal of splitting lifecycle tests into separate per-programmer file. BUG=b:237606255 TEST=ninja test Change-Id: I93d0db943d9c96e2c36e9f7dce5c885c959745a0 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Thomas Heijligen <src@posteo.de>
* gfxnvidia: Refactor singleton states into reentrant patternAlexander Goncharov2022-07-081-6/+27
| | | | | | | | | | | | | | | | | | | | Move global singleton states into a struct and store within the par_master data field for the life-time of the driver. This is one of the steps on the way to move par_master data memory management behind the initialisation API, for more context see other patches under the same topic "register_master_api". BUG=b:185191942 TEST=builds Change-Id: I00877e3cc359996e3aa59649f62c76e521ab119b Signed-off-by: Alexander Goncharov <chat@joursoir.net> Ticket: https://ticket.coreboot.org/issues/391 Reviewed-on: https://review.coreboot.org/c/flashrom/+/65342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* drkaiser: Drop drkaiser_ prefix for par data struct membersAlexander Goncharov2022-07-061-4/+4
| | | | | | | | | | | | | | | The name of the struct type already contains drkaiser_ prefix, so prefix doesn't need to be repeated in members name TEST=builds Change-Id: Ice3883b5171bdd2b4814ba4c5a7668c800ee7492 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Thomas Heijligen <src@posteo.de>
* realtek_mst_i2c_spi.c: Clarify gpio pin 88 comment to be more exactingEdward O'Callaghan2022-07-051-2/+1
| | | | | | | | | | | | | | Avoid confusion from the comment. While technically a GPIO can do anything, like drive a LED. The GPIO pin 88 *is* meant to drive the WP line of the SPI flash, that is its purpose. Change-Id: If718d41a27931380e5f7ebdb75b9863da0c61559 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65546 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dummyflasher: Remove spurious init for VARIABLE_SIZENico Huber2022-07-051-8/+0
| | | | | | | | | | | Now that the VARIABLE_SIZE emulation doesn't use SPI paths anymore, we can drop these initializations. Change-Id: I43b3667303498b6cc40310c6123bd5c39024645a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65458 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Mark MT25QU256 as testedAngel Pons2022-07-051-1/+1
| | | | | | | | | | | | As reported by Charles Parent on the mailing list. Change-Id: I9d8b0038673185103ba08c9797ff94f2f7639d6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62664 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: change GD25Q256D to "GD25Q256D/GD25Q256E"Nikolai Artemiev2022-07-051-1/+1
| | | | | | | | | | | | | | | | Extend "D" chip entry to include newer "E" parts. BUG=b:234054642 BRANCH=none TEST=builds Change-Id: I6b398d417da9289cc1d6a191fb20e3f937addb21 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65191 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* it85spi: EOL supportEdward O'Callaghan2022-07-045-381/+1
| | | | | | | | | | | | | | | | | | | | | This code was originally introduced by ITE for now exceedingly old Chromebooks. The code has had very little attention to maintain it, unlikely tested for a long time and now seems to be just a technical burden to the flashrom project. If someone is later interested it could be resurrected for reference from git history. However, it needs quite a bit of work to bring it back into maintainable order. BUG=b:156143896,b:170689483 TEST=tree builds under meson+make and unit tests pass. Change-Id: I5e8cafd73db837941c518f0e2d72d8192274fd79 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65378 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add `str` extension to extract_programmer_param function nameChinmay Lonkar2022-07-0231-81/+81
| | | | | | | | | | | | | This patch changes the function name of extract_programmer_param() to extract_programmer_param_str() as this function name will clearly specify that it returns the value of the given parameter as a string. Signed-off-by: Chinmay Lonkar <chinmay20220@gmail.com> Change-Id: Id7b9fff4d3e1de22abd31b8123a1d237cd0f5c97 Reviewed-on: https://review.coreboot.org/c/flashrom/+/65521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Thomas Heijligen <src@posteo.de>
* drkaiser: Refactor singleton states into reentrant patternAlexander Goncharov2022-06-301-7/+29
| | | | | | | | | | | | | | | | | | | | | Move global singleton states into a struct and store within the par_master data field for the life-time of the driver. This is one of the steps on the way to move par_master data memory management behind the initialisation API, for more context see other patches under the same topic "register_master_api". Implements: https://ticket.coreboot.org/issues/391 BUG=b:185191942 TEST=builds Change-Id: I3dd35eceadb9dbca8e526705b7be977564ed7318 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* tests: Remove unnecessary static keyword from lifecycle testsAnastasia Klimchuk2022-06-281-9/+9
| | | | | | | | | | | | | | | | | | Lifecycle tests had local struct declared with static keyword, but static was not necessary for them. So, removing. BUG=b:233816068 TEST=ninja test Change-Id: If844d07ec42b878bd0da8460655be45e865f089f Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Evan Benn <evanbenn@google.com> Reviewed-by: Joursoir <chat@joursoir.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Thomas Heijligen <src@posteo.de>
* tests: Add dummyflasher unit tests for opaque programmerAnastasia Klimchuk2022-06-283-1/+17
| | | | | | | | | | | | | | | | | | In commit a721181a08 dummyflasher became an opaque master too, and now registers prog bus by default. This patch upgrades a dummy unit test which uses all buses as programmer param, and adds a unit test which covers specific use case for opaque programmer. BUG=b:233816068 TEST=ninja test Change-Id: I61a5333b61ea84fb91c7f8310d52b64213c62f83 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Joursoir <chat@joursoir.net> Reviewed-by: Thomas Heijligen <src@posteo.de>
* tree: indent struct *_master consistently with tabsThomas Heijligen2022-06-2733-293/+293
| | | | | | | | | | | | | | Use `<tab>.key<tab>*= <value>,` TEST: `make VERSION=0 MAN_DATE=0` returns the same flashrom binary before and after the patch Change-Id: I1c45ea9804ca09e040d7ac98255042f58b01f8ef Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* spi25.c: Add function to return opcode of passed erase fucntion pointerAarya Chaumal2022-06-272-0/+13
| | | | | | | | | | | | | There is a function, spi_get_erasefn_from_opcode, which returns the erase function for given opcode. Add a function which does the opposite i.e. returns the opcode for given erase function. Change-Id: Ia3aefc9b9465efdd16b1678bb2ada9a23f00d316 Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Thomas Heijligen <src@posteo.de>
* spi25.c: Add a list to lookup erasefn and opcode instead of switch caseAarya Chaumal2022-06-271-39/+28
| | | | | | | | | | | | | Add a list (erasefn, opcode) which maps opcodes to erase functions. Modify the spi_get_opcode_from_erasefn to use this list. Change-Id: I126f88c313ad309b509b367f9087235b87df6136 Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Simon Buhrow Reviewed-by: Thomas Heijligen <src@posteo.de>
* ichspi.c: Simplify ich9_handle_{frap,pr}() to work with logical repEdward O'Callaghan2022-06-241-26/+21
| | | | | | | | | | | | | | Simplify ich9_handle_frap() to do the translation to the logical representation of the ich_access_protection enum in one place and work from there. This removes some unnecessary branch complexity and the possibility of out of bounds array accesses. Change-Id: I1eda067c44a84d662713475d13902c85534a59fe Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65189 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* dummyflasher: Handle invalid value of freq parameterAnastasia Klimchuk2022-06-241-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 0 is an invalid value for freq parameter and caused floating point exception. This patch checks that freq is not 0 during initialisation. Fixes: https://ticket.coreboot.org/issues/366 TEST=the following scenarios 1) error $ ./flashrom -p dummy:emulate=W25Q128FV,freq=0 -V <...> init_data: invalid value 0 for freq parameter Unhandled programmer parameters (possibly due to another failure): emulate=W25Q128FV, Error: Programmer initialization failed. 2) successful $ ./flashrom -p dummy:emulate=W25Q128FV,freq=10 -V Found Winbond flash chip "W25Q128.V" (16384 kB, SPI). 3) default is also successful $ ./flashrom -p dummy:emulate=W25Q128FV -V Found Winbond flash chip "W25Q128.V" (16384 kB, SPI). Change-Id: I0a95495de0a677f0d4d7f4c2fc61dcbc00d6ad4c Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* flashchips: Add missing block eraser for S25FL512SNico Huber2022-06-231-0/+3
| | | | | | | | | | | | | Now that we can make use of the extended-address register, we can also advertise the `d8` eraser that can take 3- or 4-byte addresses. Signed-off-by: Nico Huber <nico.h@gmx.de> Ticket: https://ticket.coreboot.org/issues/357 Change-Id: I8708294d42f5da80c0ca07ccdae627f13fd5c645 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64637 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Enable FEATURE_4BA_EAR_1716 for S25FL512SNico Huber2022-06-231-2/+3
| | | | | | | | | | | | | | | | According to its datasheet, Spansion S25FL512S supports writing/ reading its extended address register via 0x17/0x16 opcodes. With that enabled, we can also enable the EAR7 feature, i.e. toggling 4BA mode via bit 7 of that register. S25FL512S did not advertise EAR support at all, so we set it to TEST_UNTESTED again. Change-Id: Ib214e509a5c294ab60460a2b5d00a713a119ab3f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Enable FEATURE_4BA_EAR_1716 for ISSI chipsNico Huber2022-06-231-2/+4
| | | | | | | | | | | | | | | | | According to their datasheets, ISSI IS25LP256 and IS25WP256 support both 0xc5/0xc8 and 0x17/0x16 opcodes to write / read their extended address register. Flashrom will use 0xc5 by default if available, so adding the FEATURE_4BA_EAR_1716 flag makes no difference for now (FEATURE_4BA_EAR_C5C8 is included in the already selected FEATURE_4BA set). It's better to have a comprehensive description of the chips, though, in case somebody wants to use them in the future with a master that restricts available opcodes. Change-Id: I03e4ff825c7742e7ff79b51b75293d53a091d4d4 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips,spi25: Replace `.wrea_override` with FEATURE_4BA_EAR_1716Nico Huber2022-06-235-17/+27
| | | | | | | | | | | | | | | | | | | | | | | | | There are two competing sets of instructions to access the extended address register of 4BA SPI chips. Some chips even support both sets. So far, we assumed the 0xc5/0xc8 instructions by default and allowed to override the write instructions with the `.wrea_override` field. This has some disadvantages: * The additional field is easily overlooked. So when adding a new flash chip, one might assume only 0xc5/0xc8 are supported. * We cannot describe flash chips completely that allow both instructions (and some programmers may be picky about which instructions can be used). Therefore, replace the `.wrea_override` field with a feature flag. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I6d82f24898acd0789203516a7456fd785907bc10 Ticket: https://ticket.coreboot.org/issues/357 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Rename FEATURE_4BA_EXT_ADDR -> _EAR_C5C8Nico Huber2022-06-224-10/+11
| | | | | | | | | | | | | | There are two competing sets of instructions to access the extended address register of 4BA SPI chips. Some chips even support both sets. To prepare for other instructions than the default 0xc5/0xc8, rename the original feature flag. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: Iacb7b68a9e3444fe28873ff0fe5e3fab16643c8c Ticket: https://ticket.coreboot.org/issues/357 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Drop FOUR_BYTE_ADDR commentsNico Huber2022-06-221-7/+0
| | | | | | | | | | | 4BA support is implemented by now. So drop these obsolete comments. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I28c5d1de052c28735d5f07874874068ee744b77f Reviewed-on: https://review.coreboot.org/c/flashrom/+/64600 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Split W25Q256.VNico Huber2022-06-221-1/+56
| | | | | | | | | | | | The W25Q256JV supports the full set of 4BA instructions, including two native-4BA block erasers. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I1a68121ff40d2b1769632d8e5151c2cd972c23ef Ticket: https://ticket.coreboot.org/issues/362 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* pcidev: Always fetch ident infoNico Huber2022-06-221-4/+10
| | | | | | | | | | | | | | | | | As discovered earlier[1], the `vendor_id` and `device_id` fields are not always automatically set. However, we use these fields throughout flash- rom. To not lose track when we actually fetched them, let's always call pci_fill_info(PCI_FILL_IDENT) before returning a `pci_dev` handle. [1] Commit ca2e3bce0 (pcidev.c: populate IDs with pci_fill_info()) Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: Iae2511178bec44343cbe902722fdca9eda036059 Ticket: https://ticket.coreboot.org/issues/367 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* ichspi.c: Implement read_write_status for wpEdward O'Callaghan2022-06-211-0/+74
| | | | | | | | | | | | | | | | | The ichspi hwseq path has a opaque master specialisation that allows for reading and writing STATUS1 registers. Hook the callbacks with a implementation to allow for this so that writeprotect maybe supported though this path. BUG=none BRANCH=none TEST=flashrom --wp-status on AMD and Intel DUTs Change-Id: I7ecbe8491ecea3697922c91af26ca62276e86317 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* writeprotect.c: Allow opaque masters to hook {read,write}_register()Edward O'Callaghan2022-06-214-13/+53
| | | | | | | | | | | | | | | | | | | | Allow specialisation in opaque masters, such as ichspi hwseq, to write to status registers. Also update the dispatch logic in libflashrom to call wp code when status register access functions are provided by an opaque master. BUG=none BRANCH=none TEST=flashrom --wp-status on AMD and Intel DUTs Change-Id: I3ab0d7f5f48338c8ecb118a69651c203fbc516ac Signed-off-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Co-Authored-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64375 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tests: Use regular cmocka wraps for hwaccess functionsAnastasia Klimchuk2022-06-215-83/+18
| | | | | | | | | | | | | | | | | | | | | hwaccess functions used to be static inline functions and needed a special treatment so that they could be mocked for unit tests. This has changed, see include/hwaccess_x86_io.h now the functions are not static inline anymore, and it is possible to use regular cmocka wraps. Fixes https://ticket.coreboot.org/issues/385 BUG=b:181803212 TEST=ninja test Change-Id: Iafce071ea7ad5bcfdebbba968699d5743705f8e0 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joursoir <chat@joursoir.net> Reviewed-by: Thomas Heijligen <src@posteo.de>
* dummyflasher: Add emulation for S25FL128LNico Huber2022-06-202-2/+59
| | | | | | | | | | Used to test WRSR_EXT2/3 support. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: Ic3cbea87218c973331b9b83e809e7d438407bc13 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64748 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add Spansion (today Infineon) S25FL128L and S25FL256LNico Huber2022-06-204-0/+135
| | | | | | | | | | | | | | | | | | | | | | | These chips seem to be rather regular, supporting 2.7V..3.6V, the common erase block sizes 4KiB, 32KiB, 64KiB and the usual block- protection bits. Status/configuration register naming differs from other vendors, though. These chips have 2 status registers plus 3 configuration registers. Configuration registers 1 & 2 match status registers 2 & 3 of what we are used from other vendors. Read opcodes match too, however writes are always done through the WRSR instruction which can write up to 4 bytes (SR1, CR1, CR2, CR3). S25FL256L supports native 4BA commands and entering a 4BA mode. However, it uses an unusual opcode (0x53) for the 32KiB 4BA block erase. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I356df6649f29e50879a4da4183f1164a81cb0a09 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64747 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25_statusreg: Allow WRSR_EXT for Status Register 3Nico Huber2022-06-206-38/+83
| | | | | | | | | | | | | | | | | Spansion flash chips S25FL128L and S25FL256L use the WRSR instruction to write more than 2 registers. So align SR2 and SR3 support: The current FEATURE_WRSR_EXT is renamed to FEATURE_WRSR_EXT2 and FEATURE_WRSR_EXT3 is added. Also, WRSR3 needs a separate flag now. Verified that FEATURE_WRSR_EXT2 still works using the `dummy_flasher`. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: Ibdfc6eb3d2cfecbf8da0493d067031ddb079a094 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashrom.c, flashcips.c: Test the order of erase functionsAarya Chaumal2022-06-202-12/+23
| | | | | | | | | | | | | | | | | | Add a check so that the erase functions for all flashchips are in increasing order of their respective eraseblock sizes. This is required for the implentation of the improved erasing algorithm. The patch uses the count of eraseblocks in each erase function to determine the order (More eraseblocks means that the function has smaller eraseblock size). Also fix the structs in flashchips.c which were found to be not conforming to this test. TEST = make && ./flashrom Change-Id: I137cb40483fa690ecc6c7eaece2d9d3f7a851bb4 Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64961 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* board_enable: Add ASUS P5W DH DeluxeTasos Sahanidis2022-06-202-0/+3
| | | | | | | | | | | Flashrom can now write to the onboard SST49LF008 flash Signed-off-by: Tasos Sahanidis <tasos@tasossah.com> Change-Id: Iea4f858cb45c60a6180de07c8361a8a831635dfd Reviewed-on: https://review.coreboot.org/c/flashrom/+/63736 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* writeprotect: Add line-break after each `spew` messageNico Huber2022-06-201-1/+1
| | | | | | | | | Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I3131ff0e3fa4f9e949ce2e8d2d0a9c862a15e1cd Reviewed-on: https://review.coreboot.org/c/flashrom/+/64745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* atahpt: Refactor singleton states into reentrant patternAlexander Goncharov2022-06-191-6/+27
| | | | | | | | | | | | | | | | | | | | | | Move global singleton states into a struct and store within the par_master data field for the life-time of the driver. This is one of the steps on the way to move par_master data memory management behind the initialisation API, for more context see other patches under the same topic "register_master_api". Implements: https://ticket.coreboot.org/issues/391 BUG=b:185191942 TEST=builds Change-Id: I82e4c82916dc835e9462b80750b06f9d78701edf Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* atavia: fix BYTE_OFFSET's macro argument valueAlexander Goncharov2022-06-181-1/+1
| | | | | | | | | | | A macro value has to use a correct argument name. Change-Id: I666204ec92c6df625b34ca721b3e1af78772bccf Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* dummyflasher: Wire variable size feature via opaque infraAnastasia Klimchuk2022-06-163-70/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wire "variable size" feature in dummy programmer via opaque infra. This patch fixes the broken build with CONFIG_DUMMY=no. Dummyflasher registers opaque master for the case when it is initialised with EMULATE_VARIABLE_SIZE. Dummy opaque master emulates read/write/erase as simple memory operations over `data->flashchip_contents`. The feature works via "Opaque flash chip" in flashchips.c which has one block eraser at the moment. If this changes in future, each block eraser needs to be updated in `probe_variable_size`. Fixes: https://ticket.coreboot.org/issues/365 TEST=the following scenarious run successfully Testing build $ make clean && make CONFIG_DUMMY=no $ flashrom -h : dummy is not in the list $ make clean && make CONFIG_EVERYTHING=yes $ flashrom -h : dummy is in the list Testing "variable size" feature $ flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE -V $ flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE -r /tmp/dump.bin -V $ head -c 8388608 </dev/urandom >/tmp/image.bin $ flashrom -p dummy:image=/tmp/image.bin,size=8388608,emulate=VARIABLE_SIZE -w /tmp/dump.bin -V also same as above with erase_to_zero=yes Testing standard flow $ flashrom -p dummy:emulate=W25Q128FV -V $ flashrom -p dummy:emulate=W25Q128FV -r /tmp/dump.bin -V $ head -c 16777216 </dev/urandom >/tmp/image.bin $ flashrom -p dummy:image=/tmp/image.bin,emulate=W25Q128FV -w /tmp/dump.bin -V Testing invalid combination of programmer params (`init_data` fails and prints error message which is WAI) $ flashrom -p dummy:size=8388608 -V -> init_data: size parameter is only valid for VARIABLE_SIZE chip. $ flashrom -p dummy:emulate=VARIABLE_SIZE -V -> init_data: the size parameter is not given. $ flashrom -p dummy:emulate=W25Q128FV,erase_to_zero=yes -V -> init_data: erase_to_zero parameter is not valid for real chip. Change-Id: I76402bfdf8b1a75489e4509fec92c9a777d0cf58 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* libflashrom.map: Add missing functions from libflashrom.hEvan Benn2022-06-151-1/+18
| | | | | | | | | | | | Some functions were not being defined, namely flashrom_wp_*. Thus, add all missing functions from libflashrom.h header file. Change-Id: Ic90b3c20780d3a07b00bfca82d23d44c4fa6f22f Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* tree: Consolidate BIT() macroEdward O'Callaghan2022-06-103-3/+2
| | | | | | | | | Change-Id: I7e61f7671b70ca5ed751d99405714436bcd18d5a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* Add W25Q512NW-IM ID to flashromAtul Dhudase2022-06-072-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add Winbond W25Q512NW-IM chip ID and specs to flashrom. BUG=b:200173901 BRANCH=none TEST=flash W25Q512NW-IM using CCD. Original-Change-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65 Original-Signed-off-by: Atul Dhudase <adhudase@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/3171890 Original-Reviewed-by: Shelley Chen <shchen@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Shelley Chen <shchen@chromium.org> Original-Commit-Queue: Shelley Chen <shchen@chromium.org> (cherry picked from commit facb282e8939b8e4ad15d2478ed9ef86d98aed61) Note: this commit was cherry-picked from the cros tree but includes corrections to errors in the original commit's 4BA feature flags that were spotted by Angel Pons Change-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* test_build.sh: Allow WARNERROR to be overriddenMartin Roth2022-05-311-1/+1
| | | | | | | | | | | | | | | | Currently, WARNERROR is hardcoded to 'yes' which is what we want most of the time, but there are cases (such as when building with -fanalyzer) that we don't want it enabled, so we see the entire output of the build, and it doesn't halt at the first error. Removing the WARNERROR line from the script allows the variable to be overridden from an environment variable. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Iea931e57f2a6992762566dc3dbaae8bb8df5b226 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62745 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* meson: use files() for srcs listThomas Heijligen2022-05-311-61/+64
| | | | | | | | | | | | | | | Meson looks up if the file xyz.c exists when calling file('xyz.c'). Furthermore it keeps track of the directory of the file. This is handy when using multiple directories. Change-Id: I346b5468b4203f1521ec73a90f93ff3b13ebf43c Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Fix W25Q256.WPatrick Rudolph2022-05-261-3/+8
| | | | | | | | | | | | | | | | | The JW is the only known variant. A W25Q256FW may have existed with less 4BA instructions supported, but it never showed up and no data- sheet is available. Used the datasheet from here: https://www.winbond.com/resource-files/w25q256jw%20spi%20revb%2012082017.pdf Change-Id: I9a3995c66ad7b74823e17984bf1ffac50b5663e0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Nico Huber <nico.h@gmx.de> Ticket: https://ticket.coreboot.org/issues/362 Reviewed-on: https://review.coreboot.org/c/flashrom/+/44810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* flashchips.c: add CMP bit entry to W25Q256.VNikolai Artemiev2022-05-261-0/+1
| | | | | | | | | | | | | | | Add bit that was missed in `commit a850fd0a` BUG=b:182223106 BRANCH=none TEST=builds Change-Id: I1cb400f6b8542a9054875b8f2557db1cc06292e2 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64607 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libflashrom: Return progress state to the library userRichard Hughes2022-05-2522-3/+184
| | | | | | | | | | | | | | | | | | | | | | Projects using libflashrom like fwupd expect the user to wait for the operation to complete. To avoid the user thinking the process has "hung" or "got stuck" report back the progress complete of the erase, write and read operations. Add a new --progress flag to the CLI to report progress of operations. Include a test for the dummy spi25 device. TEST=./test_build.sh; ./flashrom -p lspcon_i2c_spi:bus=7 -r /dev/null --progress Change-Id: I7197572bb7f19e3bdb2bde855d70a0f50fd3854c Signed-off-by: Richard Hughes <richard@hughsie.com> Signed-off-by: Daniel Campello <campello@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashrom: initialize restore func count in correct placeNikolai Artemiev2022-05-231-1/+3
| | | | | | | | | | | | | | | | | | | | | Set `flash->chip_restore_fn_count` to zero before calling the chip's unlock funciton in `prepare_flash_access()`. Previously `flash->chip_restore_fn_count` was uninitialized before calling `chip->unlock()` and subsequently reset after the dispatch by initializing it. This caused the restore handler that is registered within `spi_disable_blockprotect_generic()` to be lost. BUG=b:228945411 BRANCH=none TEST=enable wp; flashrom -w; check wp still enabled. Change-Id: I4c7df424bd2ae2b5fb2a2ab6b47a3c9ff3233acf Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ichspi: Add Intel Alder Lake-S supportMichał Kopeć2022-05-192-2/+15
| | | | | | | | | | | | Add ADL PCH-S device IDs to enable flashrom on Alder Lake-S platforms. TEST=Dump BIOS on MSI Z690 PRO DDR4 WIFI Change-Id: Ib2a8c057994874a41ed400b176f156048dae43c0 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 19:37:59 +0000