aboutsummaryrefslogtreecommitdiffstats
path: root/testsuite/issues/pr61/vector.vhdl
diff options
context:
space:
mode:
authorTristan Gingold <tgingold@free.fr>2019-11-05 04:44:55 +0100
committerTristan Gingold <tgingold@free.fr>2019-11-05 04:44:55 +0100
commit70acfa684c7752dd836d4bf95c4b7d4d83053592 (patch)
treef171daa26fddc8bf0c6dd438b121c1f3ba76a43e /testsuite/issues/pr61/vector.vhdl
parent7a7e6050f8db18b7030e05a85cbb378e909d5f7b (diff)
downloadghdl-yosys-plugin-70acfa684c7752dd836d4bf95c4b7d4d83053592.tar.gz
ghdl-yosys-plugin-70acfa684c7752dd836d4bf95c4b7d4d83053592.tar.bz2
ghdl-yosys-plugin-70acfa684c7752dd836d4bf95c4b7d4d83053592.zip
testsuite: move pr tests in issues/
Diffstat (limited to 'testsuite/issues/pr61/vector.vhdl')
-rw-r--r--testsuite/issues/pr61/vector.vhdl15
1 files changed, 15 insertions, 0 deletions
diff --git a/testsuite/issues/pr61/vector.vhdl b/testsuite/issues/pr61/vector.vhdl
new file mode 100644
index 0000000..61a0d67
--- /dev/null
+++ b/testsuite/issues/pr61/vector.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector is
+ port (v: out signed(63 downto 0);
+ u: out unsigned(63 downto 0));
+end vector;
+
+architecture synth of vector is
+
+begin
+ v <= signed'(x"0ffffffffffffff0")+(-1);
+ u <= unsigned'(x"00ffffffffffff00")+4294967290;
+end synth;