testsuite: move pr tests in issues/

8 files changed, 115 insertions, 0 deletions

diff --git a/testsuite/issues/pr61/testsuite.sh b/testsuite/issues/pr61/testsuite.sh
new file mode 100755
index 0000000..cbbaeda
--- /dev/null
+++ b/testsuite/issues/pr61/testsuite.sh
@@ -0,0 +1,17 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+run_yosys -q -p "ghdl vector.vhdl -e vector; dump -o vector.il"
+
+grep -q 0000000000000000000000000000000011111111111111111111111111111010 vector.il || exit 1
+grep -q 0000000011111111111111111111111111111111111111111111111100000000 vector.il || exit 1
+grep -q 1111111111111111111111111111111111111111111111111111111111111111 vector.il || exit 1
+grep -q 0000111111111111111111111111111111111111111111111111111111110000 vector.il || exit 1
+
+rm -f vector.il
+
+clean
+
+echo "OK"
diff --git a/testsuite/issues/pr61/vector.vhdl b/testsuite/issues/pr61/vector.vhdl
new file mode 100644
index 0000000..61a0d67
--- /dev/null
+++ b/testsuite/issues/pr61/vector.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector is
+  port (v: out signed(63 downto 0);
+        u: out unsigned(63 downto 0));
+end vector;
+
+architecture synth of vector is
+
+begin
+  v <= signed'(x"0ffffffffffffff0")+(-1);
+  u <= unsigned'(x"00ffffffffffff00")+4294967290;
+end synth;
diff --git a/testsuite/issues/pr63/testsuite.sh b/testsuite/issues/pr63/testsuite.sh
new file mode 100755
index 0000000..cc40f65
--- /dev/null
+++ b/testsuite/issues/pr63/testsuite.sh
@@ -0,0 +1,13 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+run_yosys -q -p "ghdl vector.vhdl -e vector; opt; dump -o vector.il"
+
+grep -q 1111000000000000000000000000000000000000000000000000000000010000 vector.il || exit 1
+
+clean
+
+rm vector.il
+echo OK
diff --git a/testsuite/issues/pr63/vector.vhdl b/testsuite/issues/pr63/vector.vhdl
new file mode 100644
index 0000000..568d3f3
--- /dev/null
+++ b/testsuite/issues/pr63/vector.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector is
+    port (
+        u : out signed(63 downto 0)
+        );
+end entity vector;
+
+architecture synth of vector is
+begin
+    u <= -signed'(x"0ffffffffffffff0");
+end synth;
diff --git a/testsuite/issues/pr64/testsuite.sh b/testsuite/issues/pr64/testsuite.sh
new file mode 100755
index 0000000..0073184
--- /dev/null
+++ b/testsuite/issues/pr64/testsuite.sh
@@ -0,0 +1,14 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+run_yosys -q -p "ghdl vector.vhdl -e vector; opt; dump -o vector.il"
+
+grep -q 11111111111011110000000000100000000000001101111111110000000000000001000011111111111011110000000000000001000000000000000000000000 vector.il || exit 1
+grep -q 00000000000000000000000000001111111111111110111111110000000100000001000011111111111011110000000000000001000000000000000000000000 vector.il || exit 1
+
+clean
+
+rm vector.il
+echo OK
diff --git a/testsuite/issues/pr64/vector.vhdl b/testsuite/issues/pr64/vector.vhdl
new file mode 100644
index 0000000..c88c117
--- /dev/null
+++ b/testsuite/issues/pr64/vector.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector is
+    port (
+        s : out signed(127 downto 0);
+        u : out unsigned(127 downto 0)
+        );
+end entity vector;
+
+architecture synth of vector is
+begin
+    s <= signed'(x"ffff000000fffff0") * signed'(x"fff0000ffff00000");
+    u <= unsigned'(x"ffff000000fffff0") * unsigned'(x"fff0000ffff00000");
+end synth;
diff --git a/testsuite/issues/pr66/testsuite.sh b/testsuite/issues/pr66/testsuite.sh
new file mode 100755
index 0000000..6d8bc7e
--- /dev/null
+++ b/testsuite/issues/pr66/testsuite.sh
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+run_yosys -q -p "ghdl vector.vhdl -e vector; opt; dump -o vector.il"
+
+grep -q 'connect \\v 63' vector.il || exit 1
+
+clean
+rm  vector.il
+echo OK
diff --git a/testsuite/issues/pr66/vector.vhdl b/testsuite/issues/pr66/vector.vhdl
new file mode 100644
index 0000000..3eb9951
--- /dev/null
+++ b/testsuite/issues/pr66/vector.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector is
+    port (v: out integer
+          );
+end vector;
+
+architecture synth of vector is
+
+begin
+    v <= to_integer(unsigned'(x"7fffffff")) mod 64;
+end synth;