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| author | Tristan Gingold <tgingold@free.fr> | 2020-09-27 09:56:42 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-09-27 09:57:18 +0200 |
| commit | a5b45005f091ab16c108279a0c15334efc0347d3 (patch) | |
| tree | ebb48b34ce5f0ddab3472569ebabeb6e984e8ba5 /testsuite/issues/pr61/vector.vhdl | |
| parent | 7d100bbe4c8c8cfbcba13231c47683b52b220b86 (diff) | |
| download | ghdl-yosys-plugin-a5b45005f091ab16c108279a0c15334efc0347d3.tar.gz ghdl-yosys-plugin-a5b45005f091ab16c108279a0c15334efc0347d3.tar.bz2 ghdl-yosys-plugin-a5b45005f091ab16c108279a0c15334efc0347d3.zip | |
testsuite/issues: renames pr61 to issue61
Diffstat (limited to 'testsuite/issues/pr61/vector.vhdl')
| -rw-r--r-- | testsuite/issues/pr61/vector.vhdl | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/testsuite/issues/pr61/vector.vhdl b/testsuite/issues/pr61/vector.vhdl deleted file mode 100644 index 34274be..0000000 --- a/testsuite/issues/pr61/vector.vhdl +++ /dev/null @@ -1,20 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity vector is - port (v: out signed(63 downto 0); - u: out unsigned(63 downto 0)); -end vector; - -architecture synth of vector is - signal v1 : signed (63 downto 0); - signal u1 : unsigned (63 downto 0); - -begin - v1 <= x"0ffffffffffffff0"; - v <= v1+(-1); - u1 <= x"00ffffffffffff00"; --- u <= u1 + (-6); -- +4294967290; - u <= u1 + 6; -end synth; |