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authorTristan Gingold <tgingold@free.fr>2019-11-07 06:58:01 +0100
committerTristan Gingold <tgingold@free.fr>2019-11-07 06:58:01 +0100
commit4c08c5cbb898d8e14ee915cb667416c8c0b45050 (patch)
tree08d7220e4ed49978d184393e2f1cf3f88eb82a33 /testsuite/issues
parent016591a902e5746986244064c12183847f2f1101 (diff)
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Add testcase for #65
Diffstat (limited to 'testsuite/issues')
-rw-r--r--testsuite/issues/issue65/latch3.vhdl20
-rwxr-xr-xtestsuite/issues/issue65/testsuite.sh9
-rwxr-xr-xtestsuite/issues/issue68/testsuite.sh1
3 files changed, 30 insertions, 0 deletions
diff --git a/testsuite/issues/issue65/latch3.vhdl b/testsuite/issues/issue65/latch3.vhdl
new file mode 100644
index 0000000..e4518fe
--- /dev/null
+++ b/testsuite/issues/issue65/latch3.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity latch is
+ port (
+ signal clk : in std_logic;
+ signal data : in std_logic
+ );
+end entity;
+
+
+
+architecture rtl of latch is
+ signal other : std_logic := '0';
+begin
+
+ default clock is rising_edge(clk);
+ assert always {true}
+ |=> next (data = other);
+end architecture;
diff --git a/testsuite/issues/issue65/testsuite.sh b/testsuite/issues/issue65/testsuite.sh
new file mode 100755
index 0000000..65eb2b6
--- /dev/null
+++ b/testsuite/issues/issue65/testsuite.sh
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+synth_import --std=08 latch3.vhdl -e
+
+clean
+echo OK
diff --git a/testsuite/issues/issue68/testsuite.sh b/testsuite/issues/issue68/testsuite.sh
index 7c3a75a..916c10a 100755
--- a/testsuite/issues/issue68/testsuite.sh
+++ b/testsuite/issues/issue68/testsuite.sh
@@ -6,3 +6,4 @@ topdir=../..
synth_ice40 "demux.vhdl -e"
clean
+echo OK