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| author | Anton Blanchard <anton@linux.ibm.com> | 2019-11-04 04:48:29 +1100 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-11-03 18:48:29 +0100 |
| commit | 3cefdbec000eb69d27070c6ecfa87e109219df95 (patch) | |
| tree | ccefd8553b719777e5b79f41c94dd156712a86d3 /testsuite/pr66/vector.vhdl | |
| parent | 0ac58d2a569dae3db5d53c70750c5cb0b535ce8b (diff) | |
| download | ghdl-yosys-plugin-3cefdbec000eb69d27070c6ecfa87e109219df95.tar.gz ghdl-yosys-plugin-3cefdbec000eb69d27070c6ecfa87e109219df95.tar.bz2 ghdl-yosys-plugin-3cefdbec000eb69d27070c6ecfa87e109219df95.zip | |
Add Id_Smod support (#66)
Diffstat (limited to 'testsuite/pr66/vector.vhdl')
| -rw-r--r-- | testsuite/pr66/vector.vhdl | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/testsuite/pr66/vector.vhdl b/testsuite/pr66/vector.vhdl new file mode 100644 index 0000000..3eb9951 --- /dev/null +++ b/testsuite/pr66/vector.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vector is + port (v: out integer + ); +end vector; + +architecture synth of vector is + +begin + v <= to_integer(unsigned'(x"7fffffff")) mod 64; +end synth; |