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* Use mem v2 cellsTristan Gingold2021-11-271-93/+125
* ghdl.cc: adjust after renaming of instances attributesTristan Gingold2021-11-171-7/+7
* ghdl.cc: propagate ports attributesTristan Gingold2021-11-171-8/+16
* ghdl.cc: strip signals on memory init data. Fix #160Tristan Gingold2021-10-111-2/+9
* ghdl.cc: set attributes on signals when they are created. Fix #154Tristan Gingold2021-10-031-40/+22
* ghdl.cc: display compile date and git hashTristan Gingold2021-10-031-0/+5
* ghdl.cc: always create a wire for signal/isignal. Fix #158Tristan Gingold2021-10-021-7/+3
* ghdl.cc: remove unused/extra memory module. Fix #1699Tristan Gingold2021-03-271-10/+0
* ghdl.cc: handle read after write for memories. Fix #145Tristan Gingold2021-03-241-1/+9
* ghdl.cc: handle attributes on output portsTristan Gingold2021-03-171-8/+12
* ghdl.cc: adjust include pathTristan Gingold2021-03-071-1/+1
* ghdl.cc: handle gclk attributes on dff. For ghdl/ghdl#1610Tristan Gingold2021-01-251-13/+70
* Minor rework on attributes.Tristan Gingold2021-01-251-5/+19
* Use ':' instead of '$' for number namesTristan Gingold2020-11-181-2/+3
* ghdl.cc: allow extended identifier of length 1Tristan Gingold2020-11-181-1/+1
* Try to convert extended name to a nameTristan Gingold2020-11-181-1/+31
* '%' is not supported by Xilinx ISE edif2ngc. Fix #134eine2020-10-021-1/+2
* Fix signed modulo behaviourXiretza2020-05-301-4/+5
* Add reduce_xor support to the Yosys pluginrlee2872020-05-281-0/+4
* ghdl.cc: import attributes on memory. For ghdl/ghdl#1318Tristan Gingold2020-05-231-1/+19
* ghdl.cc: handle Id_IinoutTristan Gingold2020-05-161-0/+2
* Fix ordering of $pmux portsXiretza2020-05-141-2/+2
* ghdl.cc: implement id_pmuxTristan Gingold2020-05-091-12/+22
* handle Id_Tri and Id_ResolverTristan Gingold2020-04-231-0/+9
* ghdl.cc: adjust for recent yosys. Fix #107Tristan Gingold2020-04-231-1/+1
* ghdl.cc: adjust for edge handle (ghdl#1227)Tristan Gingold2020-04-151-16/+53
* ghdl.cc: avoid duplicate blackboxes.Tristan Gingold2020-04-091-1/+4
* Add support for non-constant asynchronous reset dff.Tristan Gingold2020-04-071-5/+29
* Add support for smod. Fix #102Tristan Gingold2020-04-071-0/+2
* Handle Id_User_Parameters: add parameters to gates.Tristan Gingold2020-03-311-21/+60
* Add support for inout gate. Fix #96Tristan Gingold2020-03-291-3/+39
* Add min/max gatesXiretza2020-03-221-0/+21
* Add abs gate (#91)Xiretza2020-03-101-0/+9
* Fix ghdl.cc indentation (#90)Xiretza2020-03-101-168/+169
* ghdl.cc: avoid infinite recursion due to concatenation.Tristan Gingold2020-03-091-2/+50
* ghdl.cc: refactoring before optimization.Tristan Gingold2020-03-091-25/+26
* ghdl.cc: rewrite help.Tristan Gingold2020-03-011-2/+23
* ghdl.cc: adjust after changes in ghdl (for memories).Tristan Gingold2020-02-231-4/+16
* add cons_0, div, and umod (#72)Pepijn de Vos2019-12-311-2/+22
* handle mem_rd_sync gates.Tristan Gingold2019-12-051-0/+10
* Handle removal of id_output gates.Tristan Gingold2019-12-051-28/+10
* Fix init input for iadff. For #76Tristan Gingold2019-12-031-1/+1
* Do not rename ports. Fix #75Tristan Gingold2019-12-031-8/+9
* Support multiple synthesis. Fix #73Tristan Gingold2019-12-021-4/+7
* Add Id_Smod support (#66)Anton Blanchard2019-11-031-0/+4
* add iadff (#67)Pepijn de Vos2019-11-031-1/+8
* rewrite import_memory, directly generate $memTristan Gingold2019-11-031-97/+130
* handle formal input ports.Tristan Gingold2019-10-311-5/+31
* Handle Id_Cover_AssertTristan Gingold2019-10-221-0/+2
* Initial support of memories.Tristan Gingold2019-10-191-18/+152
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