| Commit message (Collapse) | Author | Age | Files | Lines |
|---|
| ... | |
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
* sign extend 32b literals
* Fix undefined behavior
Right shift of a signed values is undefined but does
arithemetic shift in practice.
However, shifting by more than one int width
is also undefined but *wraps around*.
This caused bit/log to work because it'd shift mod 32.
But it actually cause the UL32 to be wrong
because it'd just repeat the value rather than extending.
* zero pad unsigned and add signed
* add testsuite
|
| |
|
|
|
|
|
|
| |
* Add Id_Neg support
* Add testcase for Id_Neg
Thanks to Pepijn for the example I based this on.
|
| |
|
|
|
|
| |
* Add Id_Smul and Id_Umul support
* Add testcase for Id_Smul and Id_Umul
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
I see a few compiler warnings on gcc 9.2:
src/ghdl.cc: In function ‘Yosys::RTLIL::SigSpec get_src(std::vector<Yosys::RTLIL::Wire*>&, GhdlSynth::Net)’:
src/ghdl.cc:123:43: warning: ‘valzx’ may be used uninitialized in this function [-Wmaybe-uninitialized]
123 | switch(((val01 >> i)&1)+((valzx >> i)&1)*2)
| ~~~~~~~^~~~~
src/ghdl.cc:123:26: warning: ‘val01’ may be used uninitialized in this function [-Wmaybe-uninitialized]
123 | switch(((val01 >> i)&1)+((valzx >> i)&1)*2)
| ~~~~~~~^~~~~
src/ghdl.cc:99:26: warning: ‘val’ may be used uninitialized in this function [-Wmaybe-uninitialized]
99 | bits[i] = (val >> i) & 1 ? RTLIL::State::S1 : RTLIL::State::S0;
| ~~~~~^~~~~
These both appear to be spurious, but initialize them to 0 to avoid the
warning.
|
| | |
|
| | |
|
| | |
|
| | |
|
| | |
|
| | |
|
| | |
|
| | |
|
| | |
|
|
|
* makefile: use '--build' shortcut to build ghdl.so
* move: rename subdir 'ghdl' to 'src'
* travis: add travis config file, build script and utils script
* testsuite: do not call ghdl explicitly
* readme: update
|
