| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Use mem v2 cells | Tristan Gingold | 2021-11-27 | 1 | -93/+125 |
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| * | ghdl.cc: adjust after renaming of instances attributes | Tristan Gingold | 2021-11-17 | 1 | -7/+7 |
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| * | ghdl.cc: propagate ports attributes | Tristan Gingold | 2021-11-17 | 1 | -8/+16 |
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| * | ghdl.cc: strip signals on memory init data. Fix #160 | Tristan Gingold | 2021-10-11 | 1 | -2/+9 |
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| * | ghdl.cc: set attributes on signals when they are created. Fix #154 | Tristan Gingold | 2021-10-03 | 1 | -40/+22 |
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| * | ghdl.cc: display compile date and git hash | Tristan Gingold | 2021-10-03 | 1 | -0/+5 |
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| * | ghdl.cc: always create a wire for signal/isignal. Fix #158 | Tristan Gingold | 2021-10-02 | 1 | -7/+3 |
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| * | ghdl.cc: remove unused/extra memory module. Fix #1699 | Tristan Gingold | 2021-03-27 | 1 | -10/+0 |
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| * | ghdl.cc: handle read after write for memories. Fix #145 | Tristan Gingold | 2021-03-24 | 1 | -1/+9 |
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| * | ghdl.cc: handle attributes on output ports | Tristan Gingold | 2021-03-17 | 1 | -8/+12 |
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| * | ghdl.cc: adjust include path | Tristan Gingold | 2021-03-07 | 1 | -1/+1 |
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| * | ghdl.cc: handle gclk attributes on dff. For ghdl/ghdl#1610 | Tristan Gingold | 2021-01-25 | 1 | -13/+70 |
| | | | | | Also attribute nets. | ||||
| * | Minor rework on attributes. | Tristan Gingold | 2021-01-25 | 1 | -5/+19 |
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| * | Use ':' instead of '$' for number names | Tristan Gingold | 2020-11-18 | 1 | -2/+3 |
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| * | ghdl.cc: allow extended identifier of length 1 | Tristan Gingold | 2020-11-18 | 1 | -1/+1 |
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| * | Try to convert extended name to a name | Tristan Gingold | 2020-11-18 | 1 | -1/+31 |
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| * | '%' is not supported by Xilinx ISE edif2ngc. Fix #134 | eine | 2020-10-02 | 1 | -1/+2 |
| | | | | | Authored-By: Tristan Gingold <tgingold@free.fr> | ||||
| * | Fix signed modulo behaviour | Xiretza | 2020-05-30 | 1 | -4/+5 |
| | | | | | | | | | | Yosys' $mod cell is the modulo of truncating division, known as "rem" in VHDL. The new $modfloor cell is the modulo of flooring division, known as "mod" in VHDL. "mod" now synthesizes correctly for negative numbers. | ||||
| * | Add reduce_xor support to the Yosys plugin | rlee287 | 2020-05-28 | 1 | -0/+4 |
| | | | | | This is a followup for ghdl/ghdl issue 1342 | ||||
| * | ghdl.cc: import attributes on memory. For ghdl/ghdl#1318 | Tristan Gingold | 2020-05-23 | 1 | -1/+19 |
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| * | ghdl.cc: handle Id_Iinout | Tristan Gingold | 2020-05-16 | 1 | -0/+2 |
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| * | Fix ordering of $pmux ports | Xiretza | 2020-05-14 | 1 | -2/+2 |
| | | | | | | | | | For Id_Pmux, IN(2+n) corresponds to s(n). For $pmux, B[n*WIDTH-1:(n-1)*WIDTH] corresponds to S[n]. Therefore, the inputs need to be appended in ascending order, such that IN(2) is assigned to B[WIDTH-1:0], IN(3) to B[2*WIDTH-1:WIDTH], etc. | ||||
| * | ghdl.cc: implement id_pmux | Tristan Gingold | 2020-05-09 | 1 | -12/+22 |
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| * | handle Id_Tri and Id_Resolver | Tristan Gingold | 2020-04-23 | 1 | -0/+9 |
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| * | ghdl.cc: adjust for recent yosys. Fix #107 | Tristan Gingold | 2020-04-23 | 1 | -1/+1 |
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| * | ghdl.cc: adjust for edge handle (ghdl#1227) | Tristan Gingold | 2020-04-15 | 1 | -16/+53 |
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| * | ghdl.cc: avoid duplicate blackboxes. | Tristan Gingold | 2020-04-09 | 1 | -1/+4 |
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| * | Add support for non-constant asynchronous reset dff. | Tristan Gingold | 2020-04-07 | 1 | -5/+29 |
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| * | Add support for smod. Fix #102 | Tristan Gingold | 2020-04-07 | 1 | -0/+2 |
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| * | Handle Id_User_Parameters: add parameters to gates. | Tristan Gingold | 2020-03-31 | 1 | -21/+60 |
| | | | | | This allows easy interfacing with verilog modules. | ||||
| * | Add support for inout gate. Fix #96 | Tristan Gingold | 2020-03-29 | 1 | -3/+39 |
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| * | Add min/max gates | Xiretza | 2020-03-22 | 1 | -0/+21 |
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| * | Add abs gate (#91) | Xiretza | 2020-03-10 | 1 | -0/+9 |
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| * | Fix ghdl.cc indentation (#90) | Xiretza | 2020-03-10 | 1 | -168/+169 |
| | | | | | Switched everything to tabs, since those seemed to be most common. Also added a vim modeline. | ||||
| * | ghdl.cc: avoid infinite recursion due to concatenation. | Tristan Gingold | 2020-03-09 | 1 | -2/+50 |
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| * | ghdl.cc: refactoring before optimization. | Tristan Gingold | 2020-03-09 | 1 | -25/+26 |
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| * | ghdl.cc: rewrite help. | Tristan Gingold | 2020-03-01 | 1 | -2/+23 |
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| * | ghdl.cc: adjust after changes in ghdl (for memories). | Tristan Gingold | 2020-02-23 | 1 | -4/+16 |
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| * | add cons_0, div, and umod (#72) | Pepijn de Vos | 2019-12-31 | 1 | -2/+22 |
| | | | | | | | * add cons_0, [su]div, and umod * Yosys mod is actually remainder semantics | ||||
| * | handle mem_rd_sync gates. | Tristan Gingold | 2019-12-05 | 1 | -0/+10 |
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| * | Handle removal of id_output gates. | Tristan Gingold | 2019-12-05 | 1 | -28/+10 |
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| * | Fix init input for iadff. For #76 | Tristan Gingold | 2019-12-03 | 1 | -1/+1 |
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| * | Do not rename ports. Fix #75 | Tristan Gingold | 2019-12-03 | 1 | -8/+9 |
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| * | Support multiple synthesis. Fix #73 | Tristan Gingold | 2019-12-02 | 1 | -4/+7 |
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| * | Add Id_Smod support (#66) | Anton Blanchard | 2019-11-03 | 1 | -0/+4 |
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| * | add iadff (#67) | Pepijn de Vos | 2019-11-03 | 1 | -1/+8 |
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| * | rewrite import_memory, directly generate $mem | Tristan Gingold | 2019-11-03 | 1 | -97/+130 |
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| * | handle formal input ports. | Tristan Gingold | 2019-10-31 | 1 | -5/+31 |
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| * | Handle Id_Cover_Assert | Tristan Gingold | 2019-10-22 | 1 | -0/+2 |
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| * | Initial support of memories. | Tristan Gingold | 2019-10-19 | 1 | -18/+152 |
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index : iCE40/ghdl-yosys-plugin | |
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