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author | Tristan Gingold <tgingold@free.fr> | 2017-10-29 09:46:45 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-10-29 09:49:01 +0100 |
commit | 6ecc19f129a9cb25c9edb0fab18f56f5d0914a40 (patch) | |
tree | 305ce0d6495d010b130fbf7a1bdd9eea859e4906 | |
parent | 6a5dd8aa7565e497b9ec19f6a95dd236a50f1628 (diff) | |
download | ghdl-6ecc19f129a9cb25c9edb0fab18f56f5d0914a40.tar.gz ghdl-6ecc19f129a9cb25c9edb0fab18f56f5d0914a40.tar.bz2 ghdl-6ecc19f129a9cb25c9edb0fab18f56f5d0914a40.zip |
Add test cases for individual assocs.
-rw-r--r-- | testsuite/gna/bug077/repro2.vhdl | 2 | ||||
-rw-r--r-- | testsuite/gna/bug077/repro3.vhdl | 26 | ||||
-rw-r--r-- | testsuite/gna/bug077/repro4.vhdl | 26 | ||||
-rw-r--r-- | testsuite/gna/bug077/repro5.vhdl | 32 | ||||
-rw-r--r-- | testsuite/gna/bug077/repro6.vhdl | 32 | ||||
-rw-r--r-- | testsuite/gna/bug077/repro7.vhdl | 32 | ||||
-rwxr-xr-x | testsuite/gna/bug077/testsuite.sh | 17 |
7 files changed, 166 insertions, 1 deletions
diff --git a/testsuite/gna/bug077/repro2.vhdl b/testsuite/gna/bug077/repro2.vhdl index daffca27a..c6d082a69 100644 --- a/testsuite/gna/bug077/repro2.vhdl +++ b/testsuite/gna/bug077/repro2.vhdl @@ -4,7 +4,7 @@ end; architecture behav of child2 is begin - assert i = (i'range => '0'); + assert i = "10"; end behav; entity repro2 is diff --git a/testsuite/gna/bug077/repro3.vhdl b/testsuite/gna/bug077/repro3.vhdl new file mode 100644 index 000000000..a5b7ab089 --- /dev/null +++ b/testsuite/gna/bug077/repro3.vhdl @@ -0,0 +1,26 @@ +entity repro3 is +end repro3; + +architecture behav of repro3 is + type my_rec is record + a : bit; + w : bit_vector; + end record; + + procedure check (v : my_rec) is + begin + assert v.a = '0' and v.w = "01"; + end check; + + procedure pack (a : bit; w : bit_vector) is + begin + check (v.a => a, + v.w => w); + end pack; +begin + process + begin + pack ('0', "01"); + wait; + end process; +end; diff --git a/testsuite/gna/bug077/repro4.vhdl b/testsuite/gna/bug077/repro4.vhdl new file mode 100644 index 000000000..15eba7260 --- /dev/null +++ b/testsuite/gna/bug077/repro4.vhdl @@ -0,0 +1,26 @@ +entity repro3 is +end repro3; + +architecture behav of repro3 is + type my_rec is record + a : bit; + w : bit_vector; + end record; + + procedure check (v : my_rec) is + begin + assert v = ('0', "10"); + end check; + + procedure pack (a : bit; w : bit_vector) is + begin + check (v.a => a, + v.w => w); + end pack; +begin + process + begin + pack ('0', "01"); + wait; + end process; +end; diff --git a/testsuite/gna/bug077/repro5.vhdl b/testsuite/gna/bug077/repro5.vhdl new file mode 100644 index 000000000..080b63c78 --- /dev/null +++ b/testsuite/gna/bug077/repro5.vhdl @@ -0,0 +1,32 @@ +entity repro5 is +end repro5; + +architecture behav of repro5 is + type my_rec is record + a : bit; + w : bit_vector (1 to 2); + end record; + + procedure check (signal v : my_rec) is + begin + assert v.a = '0' and v.w = "01"; + end check; + + procedure pack (signal a : bit; signal w : bit_vector) is + begin + check (v.a => a, + v.w => w); + end pack; + + signal sa : bit; + signal sw : bit_vector (1 to 2); +begin + process + begin + sa <= '0'; + sw <= "01"; + wait for 0 ns; + pack (sa, sw); + wait; + end process; +end; diff --git a/testsuite/gna/bug077/repro6.vhdl b/testsuite/gna/bug077/repro6.vhdl new file mode 100644 index 000000000..f2d96169d --- /dev/null +++ b/testsuite/gna/bug077/repro6.vhdl @@ -0,0 +1,32 @@ +entity repro6 is +end repro6; + +architecture behav of repro6 is + type my_rec is record + a : bit; + w : bit_vector (1 to 3); + end record; + + procedure check (signal v : my_rec) is + begin + assert v.a = '0' and v.w = "001"; + end check; + + procedure pack (signal a : bit; signal w : bit_vector) is + begin + check (v.a => a, + v.w => w); + end pack; + + signal sa : bit; + signal sw : bit_vector (1 to 2); +begin + process + begin + sa <= '0'; + sw <= "01"; + wait for 0 ns; + pack (sa, sw); + wait; + end process; +end; diff --git a/testsuite/gna/bug077/repro7.vhdl b/testsuite/gna/bug077/repro7.vhdl new file mode 100644 index 000000000..8d4d31f2b --- /dev/null +++ b/testsuite/gna/bug077/repro7.vhdl @@ -0,0 +1,32 @@ +entity repro7 is +end repro7; + +architecture behav of repro7 is + type my_rec is record + a : bit; + w : bit_vector; + end record; + + procedure check (signal v : my_rec) is + begin + assert v.a = '0' and v.w = "01"; + end check; + + procedure pack (signal a : bit; signal w : bit_vector) is + begin + check (v.a => a, + v.w => w); + end pack; + + signal sa : bit; + signal sw : bit_vector (1 to 2); +begin + process + begin + sa <= '0'; + sw <= "01"; + wait for 0 ns; + pack (sa, sw); + wait; + end process; +end; diff --git a/testsuite/gna/bug077/testsuite.sh b/testsuite/gna/bug077/testsuite.sh index 8d22a2073..cee255f9a 100755 --- a/testsuite/gna/bug077/testsuite.sh +++ b/testsuite/gna/bug077/testsuite.sh @@ -2,10 +2,27 @@ . ../../testenv.sh +analyze repro2.vhdl +elab_simulate repro2 + +analyze repro5.vhdl +elab_simulate repro5 + +analyze repro6.vhdl +elab_simulate_failure repro6 + +clean + export GHDL_STD_FLAGS=--std=08 analyze repro.vhdl elab_simulate repro +analyze repro3.vhdl +elab_simulate repro3 + +analyze repro7.vhdl +elab_simulate repro7 + clean echo "Test successful" |