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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-11 05:21:24 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-11 05:21:24 +0100 |
| commit | abc76f1224bd8b42b8c5f49afc110c4ee1dda4af (patch) | |
| tree | 9da1cf6efd9b47cd8414b9e57a775ec4322236e8 /src/simul | |
| parent | a6281651d1d34215e793861f50f790dc890c797c (diff) | |
| download | ghdl-abc76f1224bd8b42b8c5f49afc110c4ee1dda4af.tar.gz ghdl-abc76f1224bd8b42b8c5f49afc110c4ee1dda4af.tar.bz2 ghdl-abc76f1224bd8b42b8c5f49afc110c4ee1dda4af.zip | |
simul: handle psl assume directives
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index b2b0a4f2d..4948152cc 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -615,6 +615,7 @@ package body Simul.Vhdl_Elab is return; end if; when Iir_Kind_Psl_Assert_Directive + | Iir_Kind_Psl_Assume_Directive | Iir_Kind_Psl_Cover_Directive => List := Get_PSL_Clock_Sensitivity (Proc); Gather_Sensitivity (Inst, Proc_Idx, List); @@ -904,6 +905,7 @@ package body Simul.Vhdl_Elab is | Iir_Kind_Psl_Declaration => null; when Iir_Kind_Psl_Assert_Directive + | Iir_Kind_Psl_Assume_Directive | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Concurrent_Break_Statement => Processes_Table.Append ((Proc => Stmt, |