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| author | Tristan Gingold <tgingold@free.fr> | 2019-06-30 04:17:12 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-06-30 04:17:12 +0200 |
| commit | 42bda91d39ff6aa94bedc116e495995e66e7559e (patch) | |
| tree | becb645825f85755dbffa28dbe16b4692ef11ad6 /src/vhdl/vhdl-ieee-std_logic_unsigned.adb | |
| parent | 0599fde14e1032fb3bfbbe4fe26aba874070a826 (diff) | |
| download | ghdl-42bda91d39ff6aa94bedc116e495995e66e7559e.tar.gz ghdl-42bda91d39ff6aa94bedc116e495995e66e7559e.tar.bz2 ghdl-42bda91d39ff6aa94bedc116e495995e66e7559e.zip | |
synth: handle std_logic_unsigned."+"
Diffstat (limited to 'src/vhdl/vhdl-ieee-std_logic_unsigned.adb')
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_unsigned.adb | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb index 643c75ddd..9fbdac603 100644 --- a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb +++ b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb @@ -33,6 +33,13 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Int_Slv, others => Iir_Predefined_None); + Add_Patterns : constant Binary_Pattern_Type := + (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv, + Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int, + Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Int_Slv, + Arg_Slv_Sl => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl, + Arg_Sl_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Sl_Slv); + Error : exception; procedure Extract_Declarations (Pkg : Iir_Package_Declaration) @@ -107,6 +114,8 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is case Get_Identifier (Decl) is when Name_Op_Equality => Handle_Binary (Eq_Patterns); + when Name_Op_Plus => + Handle_Binary (Add_Patterns); when others => null; end case; |