Add testcase for issue50.

313 files changed, 26870 insertions, 0 deletions

diff --git a/testsuite/gna/issue50/idct.d/add_163.vhd b/testsuite/gna/issue50/idct.d/add_163.vhd
new file mode 100644
index 000000000..e5d5beaa5
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_163.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_163 is
+	port (
+		result : out std_logic_vector(15 downto 0);
+		in_a : in  std_logic_vector(15 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end add_163;
+
+architecture augh of add_163 is
+
+	signal carry_inA : std_logic_vector(17 downto 0);
+	signal carry_inB : std_logic_vector(17 downto 0);
+	signal carry_res : std_logic_vector(17 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(16 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_165.vhd b/testsuite/gna/issue50/idct.d/add_165.vhd
new file mode 100644
index 000000000..52f02510c
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_165.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_165 is
+	port (
+		result : out std_logic_vector(26 downto 0);
+		in_a : in  std_logic_vector(26 downto 0);
+		in_b : in  std_logic_vector(26 downto 0)
+	);
+end add_165;
+
+architecture augh of add_165 is
+
+	signal carry_inA : std_logic_vector(28 downto 0);
+	signal carry_inB : std_logic_vector(28 downto 0);
+	signal carry_res : std_logic_vector(28 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(27 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_166.vhd b/testsuite/gna/issue50/idct.d/add_166.vhd
new file mode 100644
index 000000000..6a761c6f4
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_166.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_166 is
+	port (
+		result : out std_logic_vector(19 downto 0);
+		in_a : in  std_logic_vector(19 downto 0);
+		in_b : in  std_logic_vector(19 downto 0)
+	);
+end add_166;
+
+architecture augh of add_166 is
+
+	signal carry_inA : std_logic_vector(21 downto 0);
+	signal carry_inB : std_logic_vector(21 downto 0);
+	signal carry_res : std_logic_vector(21 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(20 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_167.vhd b/testsuite/gna/issue50/idct.d/add_167.vhd
new file mode 100644
index 000000000..7a527c2de
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_167.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_167 is
+	port (
+		result : out std_logic_vector(26 downto 0);
+		in_a : in  std_logic_vector(26 downto 0);
+		in_b : in  std_logic_vector(26 downto 0)
+	);
+end add_167;
+
+architecture augh of add_167 is
+
+	signal carry_inA : std_logic_vector(28 downto 0);
+	signal carry_inB : std_logic_vector(28 downto 0);
+	signal carry_res : std_logic_vector(28 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(27 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_168.vhd b/testsuite/gna/issue50/idct.d/add_168.vhd
new file mode 100644
index 000000000..c90a53a72
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_168.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_168 is
+	port (
+		result : out std_logic_vector(19 downto 0);
+		in_a : in  std_logic_vector(19 downto 0);
+		in_b : in  std_logic_vector(19 downto 0)
+	);
+end add_168;
+
+architecture augh of add_168 is
+
+	signal carry_inA : std_logic_vector(21 downto 0);
+	signal carry_inB : std_logic_vector(21 downto 0);
+	signal carry_res : std_logic_vector(21 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(20 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_169.vhd b/testsuite/gna/issue50/idct.d/add_169.vhd
new file mode 100644
index 000000000..8bd74492c
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_169.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_169 is
+	port (
+		result : out std_logic_vector(26 downto 0);
+		in_a : in  std_logic_vector(26 downto 0);
+		in_b : in  std_logic_vector(26 downto 0)
+	);
+end add_169;
+
+architecture augh of add_169 is
+
+	signal carry_inA : std_logic_vector(28 downto 0);
+	signal carry_inB : std_logic_vector(28 downto 0);
+	signal carry_res : std_logic_vector(28 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(27 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_170.vhd b/testsuite/gna/issue50/idct.d/add_170.vhd
new file mode 100644
index 000000000..762945f06
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_170.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_170 is
+	port (
+		result : out std_logic_vector(19 downto 0);
+		in_a : in  std_logic_vector(19 downto 0);
+		in_b : in  std_logic_vector(19 downto 0)
+	);
+end add_170;
+
+architecture augh of add_170 is
+
+	signal carry_inA : std_logic_vector(21 downto 0);
+	signal carry_inB : std_logic_vector(21 downto 0);
+	signal carry_res : std_logic_vector(21 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(20 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_171.vhd b/testsuite/gna/issue50/idct.d/add_171.vhd
new file mode 100644
index 000000000..163da6be4
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_171.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_171 is
+	port (
+		result : out std_logic_vector(26 downto 0);
+		in_a : in  std_logic_vector(26 downto 0);
+		in_b : in  std_logic_vector(26 downto 0)
+	);
+end add_171;
+
+architecture augh of add_171 is
+
+	signal carry_inA : std_logic_vector(28 downto 0);
+	signal carry_inB : std_logic_vector(28 downto 0);
+	signal carry_res : std_logic_vector(28 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(27 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_172.vhd b/testsuite/gna/issue50/idct.d/add_172.vhd
new file mode 100644
index 000000000..0ceb61408
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_172.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_172 is
+	port (
+		result : out std_logic_vector(19 downto 0);
+		in_a : in  std_logic_vector(19 downto 0);
+		in_b : in  std_logic_vector(19 downto 0)
+	);
+end add_172;
+
+architecture augh of add_172 is
+
+	signal carry_inA : std_logic_vector(21 downto 0);
+	signal carry_inB : std_logic_vector(21 downto 0);
+	signal carry_res : std_logic_vector(21 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(20 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_173.vhd b/testsuite/gna/issue50/idct.d/add_173.vhd
new file mode 100644
index 000000000..a3afed3d0
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_173.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_173 is
+	port (
+		result : out std_logic_vector(26 downto 0);
+		in_a : in  std_logic_vector(26 downto 0);
+		in_b : in  std_logic_vector(26 downto 0)
+	);
+end add_173;
+
+architecture augh of add_173 is
+
+	signal carry_inA : std_logic_vector(28 downto 0);
+	signal carry_inB : std_logic_vector(28 downto 0);
+	signal carry_res : std_logic_vector(28 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(27 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_174.vhd b/testsuite/gna/issue50/idct.d/add_174.vhd
new file mode 100644
index 000000000..3d5fbc07b
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_174.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_174 is
+	port (
+		result : out std_logic_vector(19 downto 0);
+		in_a : in  std_logic_vector(19 downto 0);
+		in_b : in  std_logic_vector(19 downto 0)
+	);
+end add_174;
+
+architecture augh of add_174 is
+
+	signal carry_inA : std_logic_vector(21 downto 0);
+	signal carry_inB : std_logic_vector(21 downto 0);
+	signal carry_res : std_logic_vector(21 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(20 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_175.vhd b/testsuite/gna/issue50/idct.d/add_175.vhd
new file mode 100644
index 000000000..9cde83c4d
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_175.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_175 is
+	port (
+		result : out std_logic_vector(26 downto 0);
+		in_a : in  std_logic_vector(26 downto 0);
+		in_b : in  std_logic_vector(26 downto 0)
+	);
+end add_175;
+
+architecture augh of add_175 is
+
+	signal carry_inA : std_logic_vector(28 downto 0);
+	signal carry_inB : std_logic_vector(28 downto 0);
+	signal carry_res : std_logic_vector(28 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(27 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_176.vhd b/testsuite/gna/issue50/idct.d/add_176.vhd
new file mode 100644
index 000000000..20861aebb
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_176.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_176 is
+	port (
+		result : out std_logic_vector(19 downto 0);
+		in_a : in  std_logic_vector(19 downto 0);
+		in_b : in  std_logic_vector(19 downto 0)
+	);
+end add_176;
+
+architecture augh of add_176 is
+
+	signal carry_inA : std_logic_vector(21 downto 0);
+	signal carry_inB : std_logic_vector(21 downto 0);
+	signal carry_res : std_logic_vector(21 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(20 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_177.vhd b/testsuite/gna/issue50/idct.d/add_177.vhd
new file mode 100644
index 000000000..91d40b68e
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_177.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_177 is
+	port (
+		result : out std_logic_vector(26 downto 0);
+		in_a : in  std_logic_vector(26 downto 0);
+		in_b : in  std_logic_vector(26 downto 0)
+	);
+end add_177;
+
+architecture augh of add_177 is
+
+	signal carry_inA : std_logic_vector(28 downto 0);
+	signal carry_inB : std_logic_vector(28 downto 0);
+	signal carry_res : std_logic_vector(28 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(27 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_178.vhd b/testsuite/gna/issue50/idct.d/add_178.vhd
new file mode 100644
index 000000000..3ebed0cbe
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_178.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_178 is
+	port (
+		result : out std_logic_vector(19 downto 0);
+		in_a : in  std_logic_vector(19 downto 0);
+		in_b : in  std_logic_vector(19 downto 0)
+	);
+end add_178;
+
+architecture augh of add_178 is
+
+	signal carry_inA : std_logic_vector(21 downto 0);
+	signal carry_inB : std_logic_vector(21 downto 0);
+	signal carry_res : std_logic_vector(21 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(20 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_179.vhd b/testsuite/gna/issue50/idct.d/add_179.vhd
new file mode 100644
index 000000000..c0e38635b
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_179.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_179 is
+	port (
+		result : out std_logic_vector(26 downto 0);
+		in_a : in  std_logic_vector(26 downto 0);
+		in_b : in  std_logic_vector(26 downto 0)
+	);
+end add_179;
+
+architecture augh of add_179 is
+
+	signal carry_inA : std_logic_vector(28 downto 0);
+	signal carry_inB : std_logic_vector(28 downto 0);
+	signal carry_res : std_logic_vector(28 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(27 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_180.vhd b/testsuite/gna/issue50/idct.d/add_180.vhd
new file mode 100644
index 000000000..ade86c4a5
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_180.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_180 is
+	port (
+		result : out std_logic_vector(19 downto 0);
+		in_a : in  std_logic_vector(19 downto 0);
+		in_b : in  std_logic_vector(19 downto 0)
+	);
+end add_180;
+
+architecture augh of add_180 is
+
+	signal carry_inA : std_logic_vector(21 downto 0);
+	signal carry_inB : std_logic_vector(21 downto 0);
+	signal carry_res : std_logic_vector(21 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(20 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_181.vhd b/testsuite/gna/issue50/idct.d/add_181.vhd
new file mode 100644
index 000000000..e20ca4cac
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_181.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_181 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_181;
+
+architecture augh of add_181 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_182.vhd b/testsuite/gna/issue50/idct.d/add_182.vhd
new file mode 100644
index 000000000..fb9e4a021
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_182.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_182 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_182;
+
+architecture augh of add_182 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_183.vhd b/testsuite/gna/issue50/idct.d/add_183.vhd
new file mode 100644
index 000000000..a2e9e1867
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_183.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_183 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_183;
+
+architecture augh of add_183 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_184.vhd b/testsuite/gna/issue50/idct.d/add_184.vhd
new file mode 100644
index 000000000..8721eaeaf
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_184.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_184 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_184;
+
+architecture augh of add_184 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_191.vhd b/testsuite/gna/issue50/idct.d/add_191.vhd
new file mode 100644
index 000000000..0383c14ec
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_191.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_191 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(30 downto 0)
+	);
+end add_191;
+
+architecture augh of add_191 is
+
+	signal carry_inA : std_logic_vector(32 downto 0);
+	signal carry_inB : std_logic_vector(32 downto 0);
+	signal carry_res : std_logic_vector(32 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(31 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_194.vhd b/testsuite/gna/issue50/idct.d/add_194.vhd
new file mode 100644
index 000000000..864745b93
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_194.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_194 is
+	port (
+		result : out std_logic_vector(29 downto 0);
+		in_a : in  std_logic_vector(29 downto 0);
+		in_b : in  std_logic_vector(29 downto 0)
+	);
+end add_194;
+
+architecture augh of add_194 is
+
+	signal carry_inA : std_logic_vector(31 downto 0);
+	signal carry_inB : std_logic_vector(31 downto 0);
+	signal carry_res : std_logic_vector(31 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(30 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_205.vhd b/testsuite/gna/issue50/idct.d/add_205.vhd
new file mode 100644
index 000000000..154fbe2c7
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_205.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_205 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_205;
+
+architecture augh of add_205 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_206.vhd b/testsuite/gna/issue50/idct.d/add_206.vhd
new file mode 100644
index 000000000..5adf22679
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_206.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_206 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_206;
+
+architecture augh of add_206 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_210.vhd b/testsuite/gna/issue50/idct.d/add_210.vhd
new file mode 100644
index 000000000..8b6a2197d
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_210.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_210 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_210;
+
+architecture augh of add_210 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_211.vhd b/testsuite/gna/issue50/idct.d/add_211.vhd
new file mode 100644
index 000000000..e0b50f01d
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_211.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_211 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_211;
+
+architecture augh of add_211 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_212.vhd b/testsuite/gna/issue50/idct.d/add_212.vhd
new file mode 100644
index 000000000..9e284041a
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_212.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_212 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_212;
+
+architecture augh of add_212 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_226.vhd b/testsuite/gna/issue50/idct.d/add_226.vhd
new file mode 100644
index 000000000..62b7eec4b
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_226.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_226 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_226;
+
+architecture augh of add_226 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_235.vhd b/testsuite/gna/issue50/idct.d/add_235.vhd
new file mode 100644
index 000000000..ac484ebaf
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_235.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_235 is
+	port (
+		result : out std_logic_vector(26 downto 0);
+		in_a : in  std_logic_vector(26 downto 0);
+		in_b : in  std_logic_vector(26 downto 0)
+	);
+end add_235;
+
+architecture augh of add_235 is
+
+	signal carry_inA : std_logic_vector(28 downto 0);
+	signal carry_inB : std_logic_vector(28 downto 0);
+	signal carry_res : std_logic_vector(28 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(27 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_236.vhd b/testsuite/gna/issue50/idct.d/add_236.vhd
new file mode 100644
index 000000000..f0161c138
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_236.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_236 is
+	port (
+		result : out std_logic_vector(19 downto 0);
+		in_a : in  std_logic_vector(19 downto 0);
+		in_b : in  std_logic_vector(19 downto 0)
+	);
+end add_236;
+
+architecture augh of add_236 is
+
+	signal carry_inA : std_logic_vector(21 downto 0);
+	signal carry_inB : std_logic_vector(21 downto 0);
+	signal carry_res : std_logic_vector(21 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(20 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_254.vhd b/testsuite/gna/issue50/idct.d/add_254.vhd
new file mode 100644
index 000000000..a22dce3a5
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_254.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_254 is
+	port (
+		result : out std_logic_vector(26 downto 0);
+		in_a : in  std_logic_vector(26 downto 0);
+		in_b : in  std_logic_vector(26 downto 0)
+	);
+end add_254;
+
+architecture augh of add_254 is
+
+	signal carry_inA : std_logic_vector(28 downto 0);
+	signal carry_inB : std_logic_vector(28 downto 0);
+	signal carry_res : std_logic_vector(28 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(27 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_255.vhd b/testsuite/gna/issue50/idct.d/add_255.vhd
new file mode 100644
index 000000000..f6b20a3b9
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_255.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_255 is
+	port (
+		result : out std_logic_vector(19 downto 0);
+		in_a : in  std_logic_vector(19 downto 0);
+		in_b : in  std_logic_vector(19 downto 0)
+	);
+end add_255;
+
+architecture augh of add_255 is
+
+	signal carry_inA : std_logic_vector(21 downto 0);
+	signal carry_inB : std_logic_vector(21 downto 0);
+	signal carry_res : std_logic_vector(21 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(20 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_276.vhd b/testsuite/gna/issue50/idct.d/add_276.vhd
new file mode 100644
index 000000000..9d9fa4bcd
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_276.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_276 is
+	port (
+		result : out std_logic_vector(26 downto 0);
+		in_a : in  std_logic_vector(26 downto 0);
+		in_b : in  std_logic_vector(26 downto 0)
+	);
+end add_276;
+
+architecture augh of add_276 is
+
+	signal carry_inA : std_logic_vector(28 downto 0);
+	signal carry_inB : std_logic_vector(28 downto 0);
+	signal carry_res : std_logic_vector(28 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(27 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_277.vhd b/testsuite/gna/issue50/idct.d/add_277.vhd
new file mode 100644
index 000000000..4c14a887f
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_277.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_277 is
+	port (
+		result : out std_logic_vector(19 downto 0);
+		in_a : in  std_logic_vector(19 downto 0);
+		in_b : in  std_logic_vector(19 downto 0)
+	);
+end add_277;
+
+architecture augh of add_277 is
+
+	signal carry_inA : std_logic_vector(21 downto 0);
+	signal carry_inB : std_logic_vector(21 downto 0);
+	signal carry_res : std_logic_vector(21 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(20 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_295.vhd b/testsuite/gna/issue50/idct.d/add_295.vhd
new file mode 100644
index 000000000..aea58f9bc
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_295.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_295 is
+	port (
+		result : out std_logic_vector(26 downto 0);
+		in_a : in  std_logic_vector(26 downto 0);
+		in_b : in  std_logic_vector(26 downto 0)
+	);
+end add_295;
+
+architecture augh of add_295 is
+
+	signal carry_inA : std_logic_vector(28 downto 0);
+	signal carry_inB : std_logic_vector(28 downto 0);
+	signal carry_res : std_logic_vector(28 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(27 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_296.vhd b/testsuite/gna/issue50/idct.d/add_296.vhd
new file mode 100644
index 000000000..a7110a8c0
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_296.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_296 is
+	port (
+		result : out std_logic_vector(19 downto 0);
+		in_a : in  std_logic_vector(19 downto 0);
+		in_b : in  std_logic_vector(19 downto 0)
+	);
+end add_296;
+
+architecture augh of add_296 is
+
+	signal carry_inA : std_logic_vector(21 downto 0);
+	signal carry_inB : std_logic_vector(21 downto 0);
+	signal carry_res : std_logic_vector(21 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(20 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_314.vhd b/testsuite/gna/issue50/idct.d/add_314.vhd
new file mode 100644
index 000000000..0966d60d5
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_314.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_314 is
+	port (
+		result : out std_logic_vector(26 downto 0);
+		in_a : in  std_logic_vector(26 downto 0);
+		in_b : in  std_logic_vector(26 downto 0)
+	);
+end add_314;
+
+architecture augh of add_314 is
+
+	signal carry_inA : std_logic_vector(28 downto 0);
+	signal carry_inB : std_logic_vector(28 downto 0);
+	signal carry_res : std_logic_vector(28 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(27 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_315.vhd b/testsuite/gna/issue50/idct.d/add_315.vhd
new file mode 100644
index 000000000..0efd8d789
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_315.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_315 is
+	port (
+		result : out std_logic_vector(19 downto 0);
+		in_a : in  std_logic_vector(19 downto 0);
+		in_b : in  std_logic_vector(19 downto 0)
+	);
+end add_315;
+
+architecture augh of add_315 is
+
+	signal carry_inA : std_logic_vector(21 downto 0);
+	signal carry_inB : std_logic_vector(21 downto 0);
+	signal carry_res : std_logic_vector(21 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(20 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_323.vhd b/testsuite/gna/issue50/idct.d/add_323.vhd
new file mode 100644
index 000000000..6d3769be4
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_323.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_323 is
+	port (
+		result : out std_logic_vector(15 downto 0);
+		in_a : in  std_logic_vector(15 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end add_323;
+
+architecture augh of add_323 is
+
+	signal carry_inA : std_logic_vector(17 downto 0);
+	signal carry_inB : std_logic_vector(17 downto 0);
+	signal carry_res : std_logic_vector(17 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(16 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_338.vhd b/testsuite/gna/issue50/idct.d/add_338.vhd
new file mode 100644
index 000000000..966c49df0
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_338.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_338 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_338;
+
+architecture augh of add_338 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_350.vhd b/testsuite/gna/issue50/idct.d/add_350.vhd
new file mode 100644
index 000000000..46969a50b
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_350.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_350 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_350;
+
+architecture augh of add_350 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_382.vhd b/testsuite/gna/issue50/idct.d/add_382.vhd
new file mode 100644
index 000000000..1c38f11ef
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_382.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_382 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_382;
+
+architecture augh of add_382 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_390.vhd b/testsuite/gna/issue50/idct.d/add_390.vhd
new file mode 100644
index 000000000..ac1d5d6a2
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_390.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_390 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_390;
+
+architecture augh of add_390 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_393.vhd b/testsuite/gna/issue50/idct.d/add_393.vhd
new file mode 100644
index 000000000..8e2b339fb
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_393.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_393 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_393;
+
+architecture augh of add_393 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_419.vhd b/testsuite/gna/issue50/idct.d/add_419.vhd
new file mode 100644
index 000000000..036d0dfc6
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_419.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_419 is
+	port (
+		result : out std_logic_vector(26 downto 0);
+		in_a : in  std_logic_vector(26 downto 0);
+		in_b : in  std_logic_vector(26 downto 0)
+	);
+end add_419;
+
+architecture augh of add_419 is
+
+	signal carry_inA : std_logic_vector(28 downto 0);
+	signal carry_inB : std_logic_vector(28 downto 0);
+	signal carry_res : std_logic_vector(28 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(27 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_420.vhd b/testsuite/gna/issue50/idct.d/add_420.vhd
new file mode 100644
index 000000000..46c9183f4
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_420.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_420 is
+	port (
+		result : out std_logic_vector(19 downto 0);
+		in_a : in  std_logic_vector(19 downto 0);
+		in_b : in  std_logic_vector(19 downto 0)
+	);
+end add_420;
+
+architecture augh of add_420 is
+
+	signal carry_inA : std_logic_vector(21 downto 0);
+	signal carry_inB : std_logic_vector(21 downto 0);
+	signal carry_res : std_logic_vector(21 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(20 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_430.vhd b/testsuite/gna/issue50/idct.d/add_430.vhd
new file mode 100644
index 000000000..8b0d8779a
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_430.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_430 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_430;
+
+architecture augh of add_430 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_466.vhd b/testsuite/gna/issue50/idct.d/add_466.vhd
new file mode 100644
index 000000000..fefc2340e
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_466.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_466 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_466;
+
+architecture augh of add_466 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_474.vhd b/testsuite/gna/issue50/idct.d/add_474.vhd
new file mode 100644
index 000000000..121b554f5
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_474.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_474 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_474;
+
+architecture augh of add_474 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_483.vhd b/testsuite/gna/issue50/idct.d/add_483.vhd
new file mode 100644
index 000000000..92b5fde0e
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_483.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_483 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_483;
+
+architecture augh of add_483 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_487.vhd b/testsuite/gna/issue50/idct.d/add_487.vhd
new file mode 100644
index 000000000..a3464bb9d
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_487.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_487 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_487;
+
+architecture augh of add_487 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_508.vhd b/testsuite/gna/issue50/idct.d/add_508.vhd
new file mode 100644
index 000000000..24e9a80c8
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_508.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_508 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_508;
+
+architecture augh of add_508 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_516.vhd b/testsuite/gna/issue50/idct.d/add_516.vhd
new file mode 100644
index 000000000..88c41b629
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_516.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_516 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_516;
+
+architecture augh of add_516 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_537.vhd b/testsuite/gna/issue50/idct.d/add_537.vhd
new file mode 100644
index 000000000..f3ac3a406
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_537.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_537 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_537;
+
+architecture augh of add_537 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_552.vhd b/testsuite/gna/issue50/idct.d/add_552.vhd
new file mode 100644
index 000000000..ec8fa6f9f
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_552.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_552 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_552;
+
+architecture augh of add_552 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_564.vhd b/testsuite/gna/issue50/idct.d/add_564.vhd
new file mode 100644
index 000000000..4108f7e3c
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_564.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_564 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_564;
+
+architecture augh of add_564 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_570.vhd b/testsuite/gna/issue50/idct.d/add_570.vhd
new file mode 100644
index 000000000..ad0abfb68
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_570.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_570 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_570;
+
+architecture augh of add_570 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_600.vhd b/testsuite/gna/issue50/idct.d/add_600.vhd
new file mode 100644
index 000000000..cb2c86175
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_600.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_600 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_600;
+
+architecture augh of add_600 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_601.vhd b/testsuite/gna/issue50/idct.d/add_601.vhd
new file mode 100644
index 000000000..338e0052b
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_601.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_601 is
+	port (
+		result : out std_logic_vector(26 downto 0);
+		in_a : in  std_logic_vector(26 downto 0);
+		in_b : in  std_logic_vector(26 downto 0)
+	);
+end add_601;
+
+architecture augh of add_601 is
+
+	signal carry_inA : std_logic_vector(28 downto 0);
+	signal carry_inB : std_logic_vector(28 downto 0);
+	signal carry_res : std_logic_vector(28 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(27 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/add_602.vhd b/testsuite/gna/issue50/idct.d/add_602.vhd
new file mode 100644
index 000000000..72d3760c4
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/add_602.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_602 is
+	port (
+		result : out std_logic_vector(19 downto 0);
+		in_a : in  std_logic_vector(19 downto 0);
+		in_b : in  std_logic_vector(19 downto 0)
+	);
+end add_602;
+
+architecture augh of add_602 is
+
+	signal carry_inA : std_logic_vector(21 downto 0);
+	signal carry_inB : std_logic_vector(21 downto 0);
+	signal carry_res : std_logic_vector(21 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(20 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/assert_uut.vhd b/testsuite/gna/issue50/idct.d/assert_uut.vhd
new file mode 100644
index 000000000..1707dcae1
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/assert_uut.vhd
@@ -0,0 +1,419 @@
+--test bench written by Alban Bourge @ TIMA
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+library work;
+use work.pkg_tb.all;
+
+entity assert_uut is
+	port(
+				clock        : in std_logic;
+				reset        : in std_logic;
+				context_uut  : in context_t;
+				en_feed      : in std_logic;
+				stdin_rdy    : in std_logic;
+				stdin_ack    : out std_logic;
+				stdin_data   : out stdin_vector;
+				en_check     : in std_logic;
+				stdout_rdy   : in std_logic;
+				stdout_ack   : out std_logic;
+				stdout_data  : in stdout_vector;
+				vecs_found   : out std_logic;
+				vec_read     : out std_logic;
+				n_error      : out std_logic
+			);
+end assert_uut;
+
+architecture rtl of assert_uut is
+
+	type vin_table  is array(0 to 2**VEC_NO_SIZE - 1) of stdin_vector;
+	type vout_table is array(0 to 2**VEC_NO_SIZE - 1) of stdout_vector;
+	constant input_vectors_1 : vin_table := (
+		--##INPUT_VECTORS_1_GO_DOWN_HERE##--
+		0 => x"00_00_00_a3",
+		1 => x"00_00_00_ea",
+		2 => x"00_00_00_cc",
+		3 => x"00_00_00_28",
+		4 => x"00_00_00_30",
+		5 => x"00_00_00_a0",
+		6 => x"00_00_00_c0",
+		7 => x"00_00_00_80",
+		8 => x"00_00_00_00",
+		9 => x"00_00_00_00",
+		10 => x"00_00_00_00",
+		11 => x"00_00_00_00",
+		12 => x"00_00_00_00",
+		13 => x"00_00_00_00",
+		14 => x"00_00_00_00",
+		15 => x"00_00_00_00",
+		16 => x"00_00_00_00",
+		17 => x"00_00_00_00",
+		18 => x"00_00_00_00",
+		19 => x"00_00_00_00",
+		20 => x"00_00_00_00",
+		21 => x"00_00_00_00",
+		22 => x"00_00_00_00",
+		23 => x"00_00_00_00",
+		24 => x"00_00_00_00",
+		25 => x"00_00_00_00",
+		26 => x"00_00_00_00",
+		27 => x"00_00_00_00",
+		28 => x"00_00_00_00",
+		29 => x"00_00_00_00",
+		30 => x"00_00_00_00",
+		31 => x"00_00_00_00",
+		32 => x"00_00_00_00",
+		33 => x"00_00_00_00",
+		34 => x"00_00_00_00",
+		35 => x"00_00_00_00",
+		36 => x"00_00_00_00",
+		37 => x"00_00_00_00",
+		38 => x"00_00_00_00",
+		39 => x"00_00_00_00",
+		40 => x"00_00_00_00",
+		41 => x"00_00_00_00",
+		42 => x"00_00_00_00",
+		43 => x"00_00_00_00",
+		44 => x"00_00_00_00",
+		45 => x"00_00_00_00",
+		46 => x"00_00_00_00",
+		47 => x"00_00_00_00",
+		48 => x"00_00_00_00",
+		49 => x"00_00_00_00",
+		50 => x"00_00_00_00",
+		51 => x"00_00_00_00",
+		52 => x"00_00_00_00",
+		53 => x"00_00_00_00",
+		54 => x"00_00_00_00",
+		55 => x"00_00_00_00",
+		56 => x"00_00_00_00",
+		57 => x"00_00_00_00",
+		58 => x"00_00_00_00",
+		59 => x"00_00_00_00",
+		60 => x"00_00_00_00",
+		61 => x"00_00_00_00",
+		62 => x"00_00_00_00",
+		63 => x"00_00_00_00",
+		--##INPUT_VECTORS_1_GO_OVER_HERE##--
+		others => (others => '0'));
+	constant output_vectors_1 : vout_table := (
+		--##OUTPUT_VECTORS_1_GO_DOWN_HERE##--
+		0 => x"ff",
+		1 => x"00",
+		2 => x"ff",
+		3 => x"ff",
+		4 => x"00",
+		5 => x"00",
+		6 => x"ff",
+		7 => x"00",
+		8 => x"ff",
+		9 => x"00",
+		10 => x"ff",
+		11 => x"ff",
+		12 => x"00",
+		13 => x"00",
+		14 => x"ff",
+		15 => x"00",
+		16 => x"ff",
+		17 => x"00",
+		18 => x"ff",
+		19 => x"ff",
+		20 => x"00",
+		21 => x"00",
+		22 => x"ff",
+		23 => x"00",
+		24 => x"ff",
+		25 => x"00",
+		26 => x"ff",
+		27 => x"ff",
+		28 => x"00",
+		29 => x"00",
+		30 => x"ff",
+		31 => x"00",
+		32 => x"ff",
+		33 => x"00",
+		34 => x"ff",
+		35 => x"ff",
+		36 => x"00",
+		37 => x"00",
+		38 => x"ff",
+		39 => x"00",
+		40 => x"ff",
+		41 => x"00",
+		42 => x"ff",
+		43 => x"ff",
+		44 => x"00",
+		45 => x"00",
+		46 => x"ff",
+		47 => x"00",
+		48 => x"ff",
+		49 => x"00",
+		50 => x"ff",
+		51 => x"ff",
+		52 => x"00",
+		53 => x"00",
+		54 => x"ff",
+		55 => x"00",
+		56 => x"ff",
+		57 => x"00",
+		58 => x"ff",
+		59 => x"ff",
+		60 => x"00",
+		61 => x"00",
+		62 => x"ff",
+		63 => x"00",
+		--##OUTPUT_VECTORS_1_GO_OVER_HERE##--
+		others => (others => '0'));
+	constant input_vectors_2 : vin_table := (
+		--##INPUT_VECTORS_2_GO_DOWN_HERE##--
+		0 => x"00_00_00_a3",
+		1 => x"00_00_00_ea",
+		2 => x"00_00_00_cc",
+		3 => x"00_00_00_28",
+		4 => x"00_00_00_30",
+		5 => x"00_00_00_a0",
+		6 => x"00_00_00_c0",
+		7 => x"00_00_00_80",
+		8 => x"00_00_00_00",
+		9 => x"00_00_00_00",
+		10 => x"00_00_00_00",
+		11 => x"00_00_00_00",
+		12 => x"00_00_00_00",
+		13 => x"00_00_00_00",
+		14 => x"00_00_00_00",
+		15 => x"00_00_00_00",
+		16 => x"00_00_00_00",
+		17 => x"00_00_00_00",
+		18 => x"00_00_00_00",
+		19 => x"00_00_00_00",
+		20 => x"00_00_00_00",
+		21 => x"00_00_00_00",
+		22 => x"00_00_00_00",
+		23 => x"00_00_00_00",
+		24 => x"00_00_00_00",
+		25 => x"00_00_00_00",
+		26 => x"00_00_00_00",
+		27 => x"00_00_00_00",
+		28 => x"00_00_00_00",
+		29 => x"00_00_00_00",
+		30 => x"00_00_00_00",
+		31 => x"00_00_00_00",
+		32 => x"00_00_00_00",
+		33 => x"00_00_00_00",
+		34 => x"00_00_00_00",
+		35 => x"00_00_00_00",
+		36 => x"00_00_00_00",
+		37 => x"00_00_00_00",
+		38 => x"00_00_00_00",
+		39 => x"00_00_00_00",
+		40 => x"00_00_00_00",
+		41 => x"00_00_00_00",
+		42 => x"00_00_00_00",
+		43 => x"00_00_00_00",
+		44 => x"00_00_00_00",
+		45 => x"00_00_00_00",
+		46 => x"00_00_00_00",
+		47 => x"00_00_00_00",
+		48 => x"00_00_00_00",
+		49 => x"00_00_00_00",
+		50 => x"00_00_00_00",
+		51 => x"00_00_00_00",
+		52 => x"00_00_00_00",
+		53 => x"00_00_00_00",
+		54 => x"00_00_00_00",
+		55 => x"00_00_00_00",
+		56 => x"00_00_00_00",
+		57 => x"00_00_00_00",
+		58 => x"00_00_00_00",
+		59 => x"00_00_00_00",
+		60 => x"00_00_00_00",
+		61 => x"00_00_00_00",
+		62 => x"00_00_00_00",
+		63 => x"00_00_00_00",
+		--##INPUT_VECTORS_2_GO_OVER_HERE##--
+		others => (others => '0'));
+	constant output_vectors_2 : vout_table := (
+		--##OUTPUT_VECTORS_2_GO_DOWN_HERE##--
+		0 => x"ff",
+		1 => x"00",
+		2 => x"ff",
+		3 => x"ff",
+		4 => x"00",
+		5 => x"00",
+		6 => x"ff",
+		7 => x"00",
+		8 => x"ff",
+		9 => x"00",
+		10 => x"ff",
+		11 => x"ff",
+		12 => x"00",
+		13 => x"00",
+		14 => x"ff",
+		15 => x"00",
+		16 => x"ff",
+		17 => x"00",
+		18 => x"ff",
+		19 => x"ff",
+		20 => x"00",
+		21 => x"00",
+		22 => x"ff",
+		23 => x"00",
+		24 => x"ff",
+		25 => x"00",
+		26 => x"ff",
+		27 => x"ff",
+		28 => x"00",
+		29 => x"00",
+		30 => x"ff",
+		31 => x"00",
+		32 => x"ff",
+		33 => x"00",
+		34 => x"ff",
+		35 => x"ff",
+		36 => x"00",
+		37 => x"00",
+		38 => x"ff",
+		39 => x"00",
+		40 => x"ff",
+		41 => x"00",
+		42 => x"ff",
+		43 => x"ff",
+		44 => x"00",
+		45 => x"00",
+		46 => x"ff",
+		47 => x"00",
+		48 => x"ff",
+		49 => x"00",
+		50 => x"ff",
+		51 => x"ff",
+		52 => x"00",
+		53 => x"00",
+		54 => x"ff",
+		55 => x"00",
+		56 => x"ff",
+		57 => x"00",
+		58 => x"ff",
+		59 => x"ff",
+		60 => x"00",
+		61 => x"00",
+		62 => x"ff",
+		63 => x"00",
+		--##OUTPUT_VECTORS_2_GO_OVER_HERE##--
+		others => (others => '0'));
+	signal in_vec_counter_1  : unsigned(VEC_NO_SIZE - 1 downto 0);
+	signal in_vec_counter_2  : unsigned(VEC_NO_SIZE - 1 downto 0);
+	signal out_vec_counter_1 : unsigned(VEC_NO_SIZE - 1 downto 0);
+	signal out_vec_counter_2 : unsigned(VEC_NO_SIZE - 1 downto 0);
+
+	signal stdin_ack_sig  : std_logic;
+	signal vector_read    : std_logic;
+
+begin
+
+	feed : process(reset, clock) is
+	begin
+		if (reset = '1') then
+			in_vec_counter_1 <= (others => '0');
+			in_vec_counter_2 <= (others => '0');
+			stdin_data       <= (others => '0');
+			stdin_ack_sig    <= '0';
+		elsif rising_edge(clock) then
+			case context_uut is
+				when "01" =>
+					if (en_feed = '1') then
+						stdin_data <= input_vectors_1(to_integer(in_vec_counter_1));
+						stdin_ack_sig  <= '1';
+						if (stdin_rdy = '1' and stdin_ack_sig = '1') then
+							in_vec_counter_1 <= in_vec_counter_1 + 1;
+							stdin_ack_sig  <= '0';
+						end if;
+					else
+						--in_vec_counter_1 <= (others => '0');
+						stdin_data     <= (others => '0');
+						stdin_ack_sig  <= '0';
+					end if;
+				when "10" =>
+					if (en_feed = '1') then
+						stdin_data <= input_vectors_2(to_integer(in_vec_counter_2));
+						stdin_ack_sig  <= '1';
+						if (stdin_rdy = '1' and stdin_ack_sig = '1') then
+							in_vec_counter_2 <= in_vec_counter_2 + 1;
+							stdin_ack_sig  <= '0';
+						end if;
+					else
+						--in_vec_counter_2 <= (others => '0');
+						stdin_data     <= (others => '0');
+						stdin_ack_sig  <= '0';
+					end if;
+				when others =>
+			end case;
+		end if;
+	end process feed;
+
+	check : process(reset, clock) is
+	begin
+		if (reset = '1') then
+			n_error     <= '1';
+			vec_read <= '0';
+		elsif rising_edge(clock) then
+			vec_read <= '0';
+			if (en_check = '1') then
+				if (stdout_rdy = '1') then
+					vec_read <= '1';
+					case context_uut is
+						when "01" =>
+							assert (stdout_data = output_vectors_1(to_integer(out_vec_counter_1)))
+							report "ERROR ---> Bad output vector found";
+							--synthesizable check
+							if (stdout_data /= output_vectors_1(to_integer(out_vec_counter_1))) then
+								n_error <= '0';
+							end if;
+						when "10" =>
+							assert (stdout_data = output_vectors_2(to_integer(out_vec_counter_2)))
+							report "ERROR ---> Bad output vector found";
+							--synthesizable check
+							if (stdout_data /= output_vectors_2(to_integer(out_vec_counter_2))) then
+								n_error <= '0';
+							end if;
+						when others =>
+					end case;
+				end if;
+			end if;
+		end if;
+	end process check;
+
+	read_counter : process(reset, clock) is
+	begin
+		if (reset = '1') then
+			out_vec_counter_1 <= (others => '0');
+			out_vec_counter_2 <= (others => '0');
+		elsif rising_edge(clock) then
+			if (en_check = '1') then
+				if (stdout_rdy = '1') then
+					case context_uut is
+						when "01" =>
+							out_vec_counter_1 <= out_vec_counter_1 + 1;
+						when "10" =>
+							out_vec_counter_2 <= out_vec_counter_2 + 1;
+						when others =>
+					end case;
+				end if;
+			--else
+			--	case context_uut is
+			--		when "01" =>
+			--			out_vec_counter_1 <= (others => '0');
+			--		when "10" =>
+			--			out_vec_counter_2 <= (others => '0');
+			--		when others =>
+			--	end case;
+			end if;
+		end if;
+	end process read_counter;
+
+	--asynchronous declarations
+	stdout_ack <= en_check;
+	stdin_ack <= stdin_ack_sig;
+	vecs_found <= '1' when (out_vec_counter_1 /= 0 or out_vec_counter_2 /= 0) else '0';
+
+end rtl;
diff --git a/testsuite/gna/issue50/idct.d/cmp_164.vhd b/testsuite/gna/issue50/idct.d/cmp_164.vhd
new file mode 100644
index 000000000..6dd5acada
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cmp_164.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_164 is
+	port (
+		ne : out std_logic;
+		in0 : in  std_logic_vector(15 downto 0);
+		in1 : in  std_logic_vector(15 downto 0)
+	);
+end cmp_164;
+
+architecture augh of cmp_164 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	ne <= not(tmp);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/cmp_202.vhd b/testsuite/gna/issue50/idct.d/cmp_202.vhd
new file mode 100644
index 000000000..8383a0729
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cmp_202.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_202 is
+	port (
+		ne : out std_logic;
+		in0 : in  std_logic_vector(15 downto 0);
+		in1 : in  std_logic_vector(15 downto 0)
+	);
+end cmp_202;
+
+architecture augh of cmp_202 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	ne <= not(tmp);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/cmp_203.vhd b/testsuite/gna/issue50/idct.d/cmp_203.vhd
new file mode 100644
index 000000000..6f04c559a
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cmp_203.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_203 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic;
+		in1 : in  std_logic
+	);
+end cmp_203;
+
+architecture augh of cmp_203 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/cmp_204.vhd b/testsuite/gna/issue50/idct.d/cmp_204.vhd
new file mode 100644
index 000000000..c601768d7
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cmp_204.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_204 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic;
+		in1 : in  std_logic
+	);
+end cmp_204;
+
+architecture augh of cmp_204 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/cmp_324.vhd b/testsuite/gna/issue50/idct.d/cmp_324.vhd
new file mode 100644
index 000000000..bc0921c90
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cmp_324.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_324 is
+	port (
+		ne : out std_logic;
+		in0 : in  std_logic_vector(15 downto 0);
+		in1 : in  std_logic_vector(15 downto 0)
+	);
+end cmp_324;
+
+architecture augh of cmp_324 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	ne <= not(tmp);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/cmp_325.vhd b/testsuite/gna/issue50/idct.d/cmp_325.vhd
new file mode 100644
index 000000000..e21676dae
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cmp_325.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_325 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic;
+		in1 : in  std_logic
+	);
+end cmp_325;
+
+architecture augh of cmp_325 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/cmp_392.vhd b/testsuite/gna/issue50/idct.d/cmp_392.vhd
new file mode 100644
index 000000000..77107d731
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cmp_392.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_392 is
+	port (
+		ne : out std_logic;
+		in0 : in  std_logic_vector(31 downto 0);
+		in1 : in  std_logic_vector(31 downto 0)
+	);
+end cmp_392;
+
+architecture augh of cmp_392 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	ne <= not(tmp);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/cmp_396.vhd b/testsuite/gna/issue50/idct.d/cmp_396.vhd
new file mode 100644
index 000000000..44eec7bf9
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cmp_396.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_396 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_396;
+
+architecture augh of cmp_396 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/cmp_398.vhd b/testsuite/gna/issue50/idct.d/cmp_398.vhd
new file mode 100644
index 000000000..8d63755bf
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cmp_398.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_398 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_398;
+
+architecture augh of cmp_398 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/cmp_400.vhd b/testsuite/gna/issue50/idct.d/cmp_400.vhd
new file mode 100644
index 000000000..e2941af5a
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cmp_400.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_400 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_400;
+
+architecture augh of cmp_400 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/cmp_402.vhd b/testsuite/gna/issue50/idct.d/cmp_402.vhd
new file mode 100644
index 000000000..a86314c04
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cmp_402.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_402 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_402;
+
+architecture augh of cmp_402 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/cmp_404.vhd b/testsuite/gna/issue50/idct.d/cmp_404.vhd
new file mode 100644
index 000000000..522f3cc95
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cmp_404.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_404 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_404;
+
+architecture augh of cmp_404 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/cmp_406.vhd b/testsuite/gna/issue50/idct.d/cmp_406.vhd
new file mode 100644
index 000000000..38c07a5e7
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cmp_406.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_406 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_406;
+
+architecture augh of cmp_406 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/cmp_408.vhd b/testsuite/gna/issue50/idct.d/cmp_408.vhd
new file mode 100644
index 000000000..b45136077
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cmp_408.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_408 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_408;
+
+architecture augh of cmp_408 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/cmp_410.vhd b/testsuite/gna/issue50/idct.d/cmp_410.vhd
new file mode 100644
index 000000000..5c0abafc4
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cmp_410.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_410 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_410;
+
+architecture augh of cmp_410 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/cmp_411.vhd b/testsuite/gna/issue50/idct.d/cmp_411.vhd
new file mode 100644
index 000000000..2d6c41656
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cmp_411.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_411 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic;
+		in1 : in  std_logic
+	);
+end cmp_411;
+
+architecture augh of cmp_411 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/cmp_412.vhd b/testsuite/gna/issue50/idct.d/cmp_412.vhd
new file mode 100644
index 000000000..7b91164f3
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cmp_412.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_412 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic;
+		in1 : in  std_logic
+	);
+end cmp_412;
+
+architecture augh of cmp_412 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/cmp_413.vhd b/testsuite/gna/issue50/idct.d/cmp_413.vhd
new file mode 100644
index 000000000..997d10d8f
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cmp_413.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_413 is
+	port (
+		ne : out std_logic;
+		in0 : in  std_logic_vector(31 downto 0);
+		in1 : in  std_logic_vector(31 downto 0)
+	);
+end cmp_413;
+
+architecture augh of cmp_413 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	ne <= not(tmp);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/cp3_test.vhd b/testsuite/gna/issue50/idct.d/cp3_test.vhd
new file mode 100644
index 000000000..99fdbb678
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/cp3_test.vhd
@@ -0,0 +1,280 @@
+-- written by Alban Bourge @ TIMA
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.pkg_tb.all;
+
+entity cp3_test is
+	port(
+				clock   : in std_logic;
+				reset   : in std_logic;
+				n_error : out std_logic;
+				stopped : out std_logic
+			);
+end cp3_test;
+
+architecture rtl of cp3_test is
+
+	--TOP signals
+	signal reset_top   : std_logic := '0';
+	signal stdin_data  : stdin_vector;
+	signal stdin_rdy   : std_logic;
+	signal stdin_ack   : std_logic;
+	signal stdout_data : stdout_vector;
+	signal stdout_rdy  : std_logic;
+	signal stdout_ack  : std_logic;
+	--ASSERT_UNIT signals
+	signal context_uut : context_t;
+	signal en_feed     : std_logic;
+	signal en_check    : std_logic;
+	signal n_error_s   : std_logic;
+	signal vecs_found  : std_logic;
+	signal vec_read    : std_logic;
+	--PROG unit signals
+	signal instr_next  : instruction;
+	-- FSM unit signals
+	signal step        : std_logic;
+	signal start       : std_logic;
+	-- FSM signals
+	signal reset_fsm   : std_logic;
+	signal stopped_s   : std_logic;
+
+
+--------------------------------------
+--   PART OF ARCHITECTURE WITH CP3  --
+
+	--TOP signals
+	signal cp_en       : std_logic := '0';
+	signal cp_rest     : std_logic := '0';
+	signal cp_ok       : std_logic;
+	signal cp_din      : cp_vector := (others => '0');
+	signal cp_dout     : cp_vector;
+	--RAM signals
+	signal ram_1       : ram_instruction;
+	signal ram_2       : ram_instruction;
+	signal address1    : std_logic_vector(12 downto 0) := (others => '0');
+	signal address2    : std_logic_vector(12 downto 0) := (others => '0');
+	signal datain      : cp_vector := (others => '0');
+	signal dout1       : cp_vector;
+	signal dout2       : cp_vector;
+
+	--dut component declaration
+	component top is
+		port (
+			clock : in  std_logic;
+			reset : in  std_logic;
+			start : in  std_logic;
+			stdin_data : in  stdin_vector;
+			stdin_rdy : out std_logic;
+			stdin_ack : in  std_logic;
+			stdout_data : out stdout_vector;
+			stdout_rdy : out std_logic;
+			stdout_ack : in  std_logic;
+			cp_en : in  std_logic;
+			cp_rest : in  std_logic;
+			cp_din : in  cp_vector;
+			cp_dout : out cp_vector;
+			cp_ok : out std_logic
+		);
+	end component top;
+
+begin
+
+	uut : entity work.top(augh)
+	port map(
+						clock       => clock,
+						reset       => reset_top,
+						start       => start,
+						stdin_data  => stdin_data,
+						stdin_rdy   => stdin_rdy,
+						stdin_ack   => stdin_ack,
+						cp_en       => cp_en,
+						cp_rest     => cp_rest,
+						cp_ok       => cp_ok,
+						cp_din      => cp_din,
+						cp_dout     => cp_dout,
+						stdout_data => stdout_data,
+						stdout_rdy  => stdout_rdy,
+						stdout_ack  => stdout_ack
+					);
+
+	ram1 : entity work.sync_ram(rtl)
+	port map(
+						clock   => clock,
+						we      => ram_1.we,
+						address => address1,
+						datain  => datain,
+						dataout => dout1
+					);
+
+	ram2 : entity work.sync_ram(rtl)
+	port map(
+						clock   => clock,
+						we      => ram_2.we,
+						address => address2,
+						datain  => datain,
+						dataout => dout2
+					);
+
+	fsm_unit : entity work.fsm(rtl)
+	port map(
+						clock      => clock,
+						reset      => reset,
+						--prog interface
+						instr_next => instr_next,
+						step       => step,
+						--uut interface
+						cp_ok      => cp_ok,
+						stdin_rdy  => stdin_rdy,
+						stdin_ack  => stdin_ack,
+						reset_fsm  => reset_fsm,
+						start      => start,
+						cp_en      => cp_en,
+						cp_rest    => cp_rest,
+						--ram interface
+						ram_1      => ram_1,
+						ram_2      => ram_2,
+						--assert_uut interface
+						context_uut => context_uut,
+						en_feed    => en_feed,
+						en_check   => en_check,
+						vecs_found => vecs_found,
+						vec_read   => vec_read,
+						--tb interface
+						stopped    => stopped_s
+					);
+
+	--RAM ADDRESS controller 1
+	ram_ctrl1 : process(clock, reset)
+	begin
+		if (reset = '1') then
+			address1 <= (others => '0');
+		elsif rising_edge(clock) then
+			if (ram_1.addr_z = '1') then
+				address1 <= (others => '0');
+			elsif (ram_1.addr_up = '1') then
+				address1 <= std_logic_vector(unsigned(address1) + 1);
+			end if;
+		end if;
+	end process ram_ctrl1;
+
+	--RAM ADDRESS controller 2
+	ram_ctrl2 : process(clock, reset)
+	begin
+		if (reset = '1') then
+			address2 <= (others => '0');
+		elsif rising_edge(clock) then
+			if (ram_2.addr_z = '1') then
+				address2 <= (others => '0');
+			elsif (ram_2.addr_up = '1') then
+				address2 <= std_logic_vector(unsigned(address2) + 1);
+			end if;
+		end if;
+	end process ram_ctrl2;
+
+	--other comb signals
+	datain <= cp_dout;
+	cp_din <= dout2 when ram_2.sel = '1' else dout1;
+
+--   END OF ARCHITECTURE WITH CP3  --
+--------------------------------------
+
+--------------------------------------
+-- PART OF ARCHITECTURE WITHOUT CP3 --
+--
+--	--dut component declaration
+--	component top is
+--		port (
+--			clock : in  std_logic;
+--			reset : in  std_logic;
+--			start : in  std_logic;
+--			stdin_data : in  stdin_vector;
+--			stdin_rdy : out std_logic;
+--			stdin_ack : in  std_logic;
+--			stdout_data : out stdout_vector;
+--			stdout_rdy : out std_logic;
+--			stdout_ack : in  std_logic
+--		);
+--	end component top;
+--
+--begin
+--
+--	uut : entity work.top(augh)
+--	port map(
+--						clock       => clock,
+--						reset       => reset_top,
+--						start       => start,
+--						stdin_data  => stdin_data,
+--						stdin_rdy   => stdin_rdy,
+--						stdin_ack   => stdin_ack,
+--						stdout_data => stdout_data,
+--						stdout_rdy  => stdout_rdy,
+--						stdout_ack  => stdout_ack
+--					);
+--
+--	fsm_unit : entity work.fsm(rtl)
+--	port map(
+--						clock      => clock,
+--						reset      => reset,
+--						--prog interface
+--						instr_next => instr_next,
+--						step       => step,
+--						--uut interface
+--						cp_ok      => '0',
+--						stdin_rdy  => stdin_rdy,
+--						stdin_ack  => stdin_ack,
+--						reset_fsm  => reset_fsm,
+--						start      => start,
+--						cp_en      => open,
+--						cp_rest    => open,
+--						--ram interface
+--						ram_1      => open,
+--						ram_2      => open,
+--						--assert_uut interface
+--						context_uut => context_uut,
+--						en_feed    => en_feed,
+--						en_check   => en_check,
+--						vecs_found => vecs_found,
+--						vec_read   => vec_read,
+--						--tb interface
+--						stopped    => stopped_s
+--					);
+--
+-- END OF ARCHITECTURE WITHOUT CP3 --
+--------------------------------------
+
+	assert_unit : entity work.assert_uut(rtl)
+	port map(
+						clock       => clock,
+						reset       => reset,
+						context_uut => context_uut,
+						en_feed     => en_feed,
+						stdin_rdy   => stdin_rdy,
+						stdin_ack   => stdin_ack,
+						stdin_data  => stdin_data,
+						en_check    => en_check,
+						stdout_rdy  => stdout_rdy,
+						stdout_ack  => stdout_ack,
+						stdout_data => stdout_data,
+						vecs_found  => vecs_found,
+						vec_read    => vec_read,
+						n_error     => n_error_s
+					);
+
+	prog_unit : entity work.prog(rtl)
+	port map(
+						clock      => clock,
+						reset      => reset,
+						step       => step,
+						instr_next => instr_next
+					);
+
+	--other comb signals
+	reset_top <= reset or reset_fsm;
+
+	--outputs
+	n_error <= n_error_s;
+	stopped <= stopped_s;
+
+end rtl;
diff --git a/testsuite/gna/issue50/idct.d/fsm.vhd b/testsuite/gna/issue50/idct.d/fsm.vhd
new file mode 100644
index 000000000..2f4ef87ee
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/fsm.vhd
@@ -0,0 +1,396 @@
+--test bench written by Alban Bourge @ TIMA
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+library work;
+use work.pkg_tb.all;
+
+entity fsm is
+	port(
+				clock      : in std_logic;
+				reset      : in std_logic;
+				--prog interface
+				instr_next : in instruction;
+				step       : out std_logic;
+				--uut interface
+				cp_ok      : in std_logic;
+				stdin_rdy  : in std_logic;
+				stdin_ack  : in std_logic;
+				reset_fsm  : out std_logic;
+				start      : out std_logic;
+				cp_en      : out std_logic;
+				cp_rest    : out std_logic;
+				--ram interface
+				ram_1      : out ram_instruction;
+				ram_2      : out ram_instruction;
+				--assert_uut interface
+				context_uut : out context_t;
+				en_feed    : out std_logic;
+				en_check   : out std_logic;
+				vecs_found : in std_logic;
+				vec_read   : in std_logic;
+				--tb interface
+				stopped    : out std_logic
+			);
+end fsm;
+
+architecture rtl of fsm is
+
+	-- read output
+	signal step_sig  : std_logic;
+	-- FSM signals
+	signal instr_c   : instruction := instr_rst;
+	signal instr_n   : instruction := instr_rst;
+	-- TIMER signal
+	signal times_en  : std_logic := '0';
+	signal times_z   : std_logic := '0';
+	signal times     : unsigned(ARG_WIDTH - 1 downto 0);
+	signal times_max : unsigned(ARG_WIDTH - 1 downto 0);
+	signal times_ok  : std_logic := '0';
+	-- COUNTER signal
+	signal count_en  : std_logic := '0';
+	signal count_z   : std_logic := '0';
+	signal count     : unsigned(ARG_WIDTH - 1 downto 0);
+	signal count_max : unsigned(ARG_WIDTH - 1 downto 0);
+	signal count_ok  : std_logic := '0';
+	-- runtime counter
+	signal runtime_en : std_logic := '0';
+	signal runtime    : integer range 0 to 99999999; --100 million cycles
+
+begin
+
+	-- FSM
+	state_reg : process (clock, reset) is
+	begin
+		if (reset = '1') then
+			instr_c <= instr_rst;
+		elsif rising_edge(clock) then
+			instr_c <= instr_n;
+		end if;
+	end process state_reg;
+
+	comb_logic: process(instr_next, instr_c, stdin_rdy, count_ok, times_ok, cp_ok, stdin_ack, vecs_found, vec_read)
+	begin
+		--default definition for fsm control signals
+		instr_n    <= instr_rst;
+		step_sig   <= '0';
+		--top
+		reset_fsm  <= '0';
+		start      <= '0';
+		cp_en      <= '0';
+		cp_rest    <= '0';
+		--counter & timer
+		times_en   <= '0';
+		times_max  <= (others => '0');
+		count_en   <= '0';
+		count_max  <= (others => '0');
+		--runtime counter
+		runtime_en <= '0';
+		--ram
+		ram_1      <= ram_instr_z;
+		ram_2      <= ram_instr_z;
+		--assert_uut
+		en_feed    <= '0';
+		en_check   <= '0';
+		--tb interface
+		stopped    <= '0';
+
+		case instr_c.state is
+			when Rst =>
+				--signals
+				reset_fsm    <= '1';
+				ram_1.addr_z <= '1';
+				ram_2.addr_z <= '1';
+				step_sig     <= '1'; --demand for next instruction
+				--transition
+				instr_n <= instr_next;
+
+			when Sig_start =>
+				--signals
+				start    <= '1';
+				step_sig <= '1'; --demand for next instruction
+				--transition
+				instr_n <= instr_next;
+				--if (instr_next.state = Ack_data) then
+					--en_feed <= '1';
+				--end if;
+
+			when Ack_data =>
+				times_max <= instr_c.arg - 1;
+				--signals
+				en_feed <= '1';
+				--transition
+				if (stdin_rdy = '1' and stdin_ack = '1') then
+					times_en <= '1';
+				end if;
+				if (times_ok = '1') then
+					en_feed <= '0';
+					step_sig <= '1';
+					instr_n <= instr_next;
+				else
+					instr_n <= instr_c;
+				end if;
+
+			when Running =>
+				--signals
+				count_max <= instr_c.arg;
+				count_en  <= '1';
+				--en_check  <= '1';
+				--runtime counter
+				if(vecs_found = '0') then
+					runtime_en <= '1';
+				end if;
+				--transition
+				if (count_ok = '1') then
+					step_sig <= '1';
+					instr_n  <= instr_next;
+				else
+					instr_n <= instr_c;
+				end if;
+
+			when Waitfor =>
+				--signals
+				count_max <= instr_c.arg;
+				en_check  <= '1';
+				if(vec_read = '1') then
+					count_en  <= '1';
+				end if;
+				--runtime counter
+				if(vecs_found = '0') then
+					runtime_en <= '1';
+				end if;
+				--transition
+				if (count_ok = '1') then
+					step_sig <= '1';
+					instr_n  <= instr_next;
+				else
+					instr_n <= instr_c;
+				end if;
+
+			when Cp_search =>
+				--signals
+				cp_en <= '1';
+				--transition
+				if (cp_ok = '1') then
+					case instr_c.context_uut is
+						when "01" =>
+							ram_1.we <= '1';
+							ram_1.addr_up  <= '1';
+							ram_1.sel  <= '1';
+						when "10" =>
+							ram_2.we <= '1';
+							ram_2.addr_up  <= '1';
+							ram_2.sel  <= '1';
+						when others =>
+					end case;
+					instr_n  <= (state => Cp_save, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
+				else
+					instr_n <= instr_c;
+				end if;
+
+			when Cp_save =>
+				--signals
+				cp_en    <= '1';
+				case instr_c.context_uut is
+					when "01" =>
+						ram_1.we <= '1';
+						ram_1.addr_up  <= '1';
+						ram_1.sel  <= '1';
+					when "10" =>
+						ram_2.we <= '1';
+						ram_2.addr_up  <= '1';
+						ram_2.sel  <= '1';
+					when others =>
+				end case;
+				--transition
+				if (cp_ok = '0') then
+					case instr_c.context_uut is
+						when "01" =>
+							ram_1.we <= '0';
+							ram_1.addr_up  <= '0';
+						when "10" =>
+							ram_2.we <= '0';
+							ram_2.addr_up  <= '0';
+						when others =>
+					end case;
+					step_sig <= '1';
+					instr_n  <= instr_next;
+				else
+					instr_n  <= instr_c;
+				end if;
+
+			when Idle => 
+				--signals
+				count_max <= instr_c.arg;
+				count_en <= '1';
+				--transition
+				if (count_ok = '1') then
+					step_sig <= '1';
+					instr_n <= instr_next;
+				else
+					instr_n <= instr_c;
+				end if;
+
+			when Rst_uut =>
+				--signals
+				reset_fsm <= '1';
+				ram_1.addr_z <= '1';
+				ram_2.addr_z <= '1';
+				--transition
+				step_sig <= '1';
+				instr_n <= instr_next;
+
+			when Rest_ini0 =>
+				--signals
+				start   <= '1';
+				cp_en   <= '1';
+				cp_rest <= '1';
+				--this is for restoration : reading the first word of the right memory
+				case instr_c.context_uut is
+					when "01" =>
+						ram_1.sel  <= '1';
+					when "10" =>
+						ram_2.sel  <= '1';
+					when others =>
+				end case;
+				--transition
+				instr_n <= (state => Rest_ini1, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
+
+			when Rest_ini1 =>
+				--signals
+				cp_en   <= '1';
+				cp_rest <= '1';
+				case instr_c.context_uut is
+					when "01" =>
+						ram_1.addr_up  <= '1';
+						ram_1.sel  <= '1';
+					when "10" =>
+						ram_2.addr_up  <= '1';
+						ram_2.sel  <= '1';
+					when others =>
+				end case;
+				--transition
+				instr_n <= (state => Rest, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
+
+			when Rest =>
+				--signals
+				cp_en   <= '1';
+				cp_rest <= '1';
+				case instr_c.context_uut is
+					when "01" =>
+						ram_1.addr_up  <= '1';
+						ram_1.sel  <= '1';
+					when "10" =>
+						ram_2.addr_up  <= '1';
+						ram_2.sel  <= '1';
+					when others =>
+				end case;
+				--transition
+				if (cp_ok = '0') then
+					step_sig <= '1';
+					instr_n  <= instr_next;
+				else
+					instr_n  <= instr_c;
+				end if;
+
+			when Stop =>
+				--signals
+				stopped   <= '1';
+				reset_fsm <= '1';
+				report "RUNTIME:" & integer'image(runtime);
+				assert (vecs_found = '0')
+				report "END_OF_SIM ---> Stop state reached, some output vectors were read." severity note;
+				--transition
+				instr_n <= (state => Stop, context_uut => "00", arg => (others => '0')); --hard coded
+
+			when others =>
+		end case;
+	end process comb_logic;
+
+	--*ER reset combo logic
+	--if a step_sig signal is sent, it means a instr_next will be consumed
+	reseter : process(step_sig)
+	begin
+		if (step_sig = '0') then
+			times_z    <= '0';
+			count_z    <= '0';
+		else
+			times_z    <= '1';
+			count_z    <= '1';
+		end if;
+	end process reseter;
+
+	--TIMER
+	timer : process(clock, reset)
+	begin
+		if (reset =  '1') then
+			times    <= (others => '0');
+			times_ok <= '0';
+		elsif rising_edge(clock) then
+			if (times_z = '1') then
+				times    <= (others => '0');
+				times_ok <= '0';
+			else
+				if (times_en = '1') then
+					times <= times + 1;
+					if (times = times_max) then
+						times_ok <= '1';
+					else
+						times_ok <= '0';
+					end if;
+				end if;
+			end if;
+		end if;
+	end process timer;
+
+	--COUNTER
+	counter : process(clock, reset)
+	begin
+		if (reset =  '1') then
+			count <= (others => '0');
+			count_ok <= '0';
+		elsif rising_edge(clock) then
+			--count_ok driving if
+			if (count_z = '1') then
+				count_ok <= '0';
+				count    <= (others => '0');
+			else
+				if (count = count_max) then
+					count_ok <= '1';
+				else
+					count_ok <= '0';
+					if (count_en = '1') then
+						count <= count + 1;
+					end if;
+				end if;
+			end if;
+		end if;
+		end process counter;
+
+	--Runtime counter
+	runtime_counter : process(clock, reset)
+	begin
+		if (reset =  '1') then
+			runtime <= 0;
+		elsif rising_edge(clock) then
+			if (runtime_en = '1') then
+				runtime <= runtime + 1;
+				if ((runtime mod 1000) = 0) then
+					report "Running since:" & integer'image(runtime) severity note;
+				end if;
+			end if;
+		end if;
+	end process runtime_counter;
+
+	-- process only used for reporting current instruction
+	reporter : process(instr_c)
+	begin
+		--report "Instruction: " & state_t'image(instr_c.state) severity note;
+		report "Instruction: " & state_t'image(instr_c.state) & " (context " & integer'image(to_integer(unsigned(instr_c.context_uut))) & ")" severity note;
+	end process reporter;
+
+	--Combinational
+	step <= step_sig;
+	context_uut <= instr_c.context_uut;
+end rtl;
diff --git a/testsuite/gna/issue50/idct.d/fsm_23.vhd b/testsuite/gna/issue50/idct.d/fsm_23.vhd
new file mode 100644
index 000000000..f5285a45b
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/fsm_23.vhd
@@ -0,0 +1,4853 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity fsm_23 is
+	port (
+		clock : in  std_logic;
+		reset : in  std_logic;
+		in0 : in  std_logic;
+		out181 : out std_logic;
+		out182 : out std_logic;
+		out183 : out std_logic;
+		out184 : out std_logic;
+		out185 : out std_logic;
+		out8 : out std_logic;
+		out13 : out std_logic;
+		out14 : out std_logic;
+		out16 : out std_logic;
+		out18 : out std_logic;
+		out19 : out std_logic;
+		out20 : out std_logic;
+		out21 : out std_logic;
+		out22 : out std_logic;
+		in2 : in  std_logic;
+		out23 : out std_logic;
+		out24 : out std_logic;
+		out25 : out std_logic;
+		out26 : out std_logic;
+		out27 : out std_logic;
+		out28 : out std_logic;
+		out29 : out std_logic;
+		out30 : out std_logic;
+		out31 : out std_logic;
+		out33 : out std_logic;
+		out35 : out std_logic;
+		out36 : out std_logic;
+		out38 : out std_logic;
+		out40 : out std_logic;
+		out42 : out std_logic;
+		in3 : in  std_logic;
+		out44 : out std_logic;
+		out46 : out std_logic;
+		out48 : out std_logic;
+		out49 : out std_logic;
+		out50 : out std_logic;
+		out52 : out std_logic;
+		out54 : out std_logic;
+		out56 : out std_logic;
+		out57 : out std_logic;
+		out58 : out std_logic;
+		in4 : in  std_logic;
+		out60 : out std_logic;
+		in5 : in  std_logic;
+		out164 : out std_logic;
+		out165 : out std_logic;
+		out167 : out std_logic;
+		out168 : out std_logic;
+		out170 : out std_logic;
+		out171 : out std_logic;
+		out173 : out std_logic;
+		out174 : out std_logic;
+		out176 : out std_logic;
+		out178 : out std_logic;
+		out0 : out std_logic;
+		out1 : out std_logic;
+		out2 : out std_logic;
+		in1 : in  std_logic;
+		out4 : out std_logic;
+		out90 : out std_logic;
+		out91 : out std_logic;
+		out97 : out std_logic;
+		out99 : out std_logic;
+		out101 : out std_logic;
+		in6 : in  std_logic;
+		out103 : out std_logic;
+		out105 : out std_logic;
+		out106 : out std_logic;
+		out107 : out std_logic;
+		out108 : out std_logic;
+		out135 : out std_logic;
+		out136 : out std_logic;
+		out137 : out std_logic;
+		out138 : out std_logic;
+		in11 : in  std_logic;
+		out140 : out std_logic;
+		out141 : out std_logic;
+		out142 : out std_logic;
+		out143 : out std_logic;
+		out145 : out std_logic;
+		out146 : out std_logic;
+		out148 : out std_logic;
+		out150 : out std_logic;
+		out153 : out std_logic;
+		out154 : out std_logic;
+		out155 : out std_logic;
+		out156 : out std_logic;
+		out157 : out std_logic;
+		out158 : out std_logic;
+		out159 : out std_logic;
+		out160 : out std_logic;
+		out161 : out std_logic;
+		out162 : out std_logic;
+		out111 : out std_logic;
+		out112 : out std_logic;
+		out114 : out std_logic;
+		out116 : out std_logic;
+		out118 : out std_logic;
+		out120 : out std_logic;
+		out121 : out std_logic;
+		out122 : out std_logic;
+		out123 : out std_logic;
+		out124 : out std_logic;
+		out125 : out std_logic;
+		out126 : out std_logic;
+		in7 : in  std_logic;
+		out129 : out std_logic;
+		out130 : out std_logic;
+		in8 : in  std_logic;
+		out131 : out std_logic;
+		in9 : in  std_logic;
+		out132 : out std_logic;
+		out133 : out std_logic;
+		out134 : out std_logic;
+		in10 : in  std_logic;
+		out186 : out std_logic;
+		out187 : out std_logic;
+		out190 : out std_logic;
+		out195 : out std_logic;
+		out197 : out std_logic;
+		out198 : out std_logic;
+		out199 : out std_logic;
+		out200 : out std_logic;
+		out201 : out std_logic;
+		out203 : out std_logic;
+		out204 : out std_logic;
+		out206 : out std_logic;
+		out207 : out std_logic;
+		out209 : out std_logic;
+		out210 : out std_logic;
+		out212 : out std_logic;
+		out213 : out std_logic;
+		out215 : out std_logic;
+		out217 : out std_logic;
+		out220 : out std_logic;
+		out221 : out std_logic;
+		out222 : out std_logic;
+		out223 : out std_logic;
+		out224 : out std_logic;
+		out225 : out std_logic;
+		out226 : out std_logic;
+		out227 : out std_logic;
+		out228 : out std_logic;
+		out229 : out std_logic;
+		out231 : out std_logic;
+		out232 : out std_logic;
+		out234 : out std_logic;
+		out235 : out std_logic;
+		out237 : out std_logic;
+		out238 : out std_logic;
+		out240 : out std_logic;
+		out241 : out std_logic;
+		out243 : out std_logic;
+		out245 : out std_logic;
+		out248 : out std_logic;
+		out249 : out std_logic;
+		out250 : out std_logic;
+		out251 : out std_logic;
+		out252 : out std_logic;
+		out253 : out std_logic;
+		out254 : out std_logic;
+		out255 : out std_logic;
+		out256 : out std_logic;
+		out257 : out std_logic;
+		out259 : out std_logic;
+		out260 : out std_logic;
+		out262 : out std_logic;
+		out263 : out std_logic;
+		out265 : out std_logic;
+		out266 : out std_logic;
+		out268 : out std_logic;
+		out269 : out std_logic;
+		out271 : out std_logic;
+		out273 : out std_logic;
+		out276 : out std_logic;
+		out277 : out std_logic;
+		out278 : out std_logic;
+		out279 : out std_logic;
+		out280 : out std_logic;
+		out281 : out std_logic;
+		out282 : out std_logic;
+		out283 : out std_logic;
+		out284 : out std_logic;
+		out285 : out std_logic;
+		out286 : out std_logic;
+		out287 : out std_logic;
+		out288 : out std_logic;
+		out289 : out std_logic;
+		out290 : out std_logic;
+		out291 : out std_logic;
+		out292 : out std_logic;
+		out293 : out std_logic;
+		out294 : out std_logic;
+		out295 : out std_logic;
+		out296 : out std_logic;
+		out297 : out std_logic;
+		out298 : out std_logic;
+		out311 : out std_logic;
+		out312 : out std_logic;
+		out313 : out std_logic;
+		out314 : out std_logic;
+		out315 : out std_logic;
+		out316 : out std_logic;
+		out318 : out std_logic;
+		out321 : out std_logic;
+		out322 : out std_logic;
+		out323 : out std_logic;
+		out324 : out std_logic;
+		out325 : out std_logic;
+		out326 : out std_logic;
+		out327 : out std_logic;
+		out328 : out std_logic;
+		out329 : out std_logic;
+		out333 : out std_logic;
+		out341 : out std_logic;
+		out342 : out std_logic;
+		out343 : out std_logic;
+		out344 : out std_logic;
+		out345 : out std_logic;
+		out346 : out std_logic;
+		out349 : out std_logic;
+		out350 : out std_logic;
+		out351 : out std_logic;
+		out352 : out std_logic;
+		out353 : out std_logic;
+		out354 : out std_logic;
+		out355 : out std_logic;
+		out357 : out std_logic;
+		out361 : out std_logic;
+		out362 : out std_logic;
+		out363 : out std_logic;
+		out364 : out std_logic;
+		out366 : out std_logic;
+		out367 : out std_logic;
+		out371 : out std_logic;
+		out372 : out std_logic;
+		out373 : out std_logic;
+		out382 : out std_logic;
+		out383 : out std_logic;
+		out385 : out std_logic;
+		out393 : out std_logic;
+		out394 : out std_logic;
+		out395 : out std_logic;
+		out396 : out std_logic;
+		out398 : out std_logic;
+		out400 : out std_logic;
+		out401 : out std_logic;
+		out402 : out std_logic;
+		out404 : out std_logic;
+		out406 : out std_logic;
+		out407 : out std_logic;
+		out408 : out std_logic;
+		out409 : out std_logic;
+		out410 : out std_logic;
+		out411 : out std_logic;
+		out412 : out std_logic;
+		out413 : out std_logic;
+		out414 : out std_logic;
+		out416 : out std_logic;
+		out417 : out std_logic;
+		out418 : out std_logic;
+		out419 : out std_logic;
+		out422 : out std_logic;
+		out423 : out std_logic;
+		out425 : out std_logic;
+		out426 : out std_logic;
+		out428 : out std_logic;
+		out429 : out std_logic;
+		out430 : out std_logic;
+		out431 : out std_logic;
+		out433 : out std_logic;
+		out434 : out std_logic;
+		out435 : out std_logic;
+		out436 : out std_logic;
+		out437 : out std_logic;
+		out438 : out std_logic;
+		out440 : out std_logic;
+		out441 : out std_logic;
+		out443 : out std_logic;
+		out444 : out std_logic;
+		out445 : out std_logic;
+		out446 : out std_logic;
+		out447 : out std_logic;
+		out450 : out std_logic;
+		out451 : out std_logic;
+		out454 : out std_logic;
+		out455 : out std_logic;
+		out457 : out std_logic;
+		out458 : out std_logic;
+		out459 : out std_logic;
+		out460 : out std_logic;
+		out461 : out std_logic;
+		out462 : out std_logic;
+		out463 : out std_logic;
+		out464 : out std_logic;
+		out465 : out std_logic;
+		out466 : out std_logic;
+		out467 : out std_logic;
+		out468 : out std_logic;
+		out469 : out std_logic;
+		out472 : out std_logic;
+		out475 : out std_logic;
+		out481 : out std_logic;
+		out482 : out std_logic;
+		out483 : out std_logic;
+		out484 : out std_logic;
+		out487 : out std_logic;
+		out488 : out std_logic;
+		out491 : out std_logic;
+		out495 : out std_logic;
+		out496 : out std_logic;
+		out497 : out std_logic;
+		out498 : out std_logic;
+		out499 : out std_logic;
+		out500 : out std_logic;
+		out501 : out std_logic;
+		out512 : out std_logic;
+		out513 : out std_logic;
+		out517 : out std_logic;
+		out518 : out std_logic;
+		out519 : out std_logic;
+		out521 : out std_logic;
+		out522 : out std_logic;
+		out524 : out std_logic;
+		out525 : out std_logic;
+		out526 : out std_logic;
+		out527 : out std_logic;
+		out528 : out std_logic;
+		out531 : out std_logic;
+		out540 : out std_logic;
+		out542 : out std_logic;
+		out544 : out std_logic;
+		out545 : out std_logic;
+		out554 : out std_logic;
+		out555 : out std_logic;
+		out559 : out std_logic;
+		out560 : out std_logic;
+		out561 : out std_logic;
+		out562 : out std_logic;
+		out563 : out std_logic;
+		out566 : out std_logic;
+		out567 : out std_logic;
+		out570 : out std_logic;
+		out572 : out std_logic;
+		out575 : out std_logic;
+		out577 : out std_logic;
+		out578 : out std_logic;
+		out580 : out std_logic;
+		out581 : out std_logic
+	);
+end fsm_23;
+
+architecture augh of fsm_23 is
+
+	signal state_cur  : std_logic_vector(0 to 240) := (7 => '1', others => '0');
+	signal state_next : std_logic_vector(0 to 240) := (7 => '1', others => '0');
+
+	-- Buffers for outputs
+	signal out122_buf : std_logic := '0';
+	signal out122_bufn : std_logic;
+	signal out36_buf : std_logic := '0';
+	signal out36_bufn : std_logic;
+	signal out49_buf : std_logic := '0';
+	signal out49_bufn : std_logic;
+	signal out35_buf : std_logic := '0';
+	signal out35_bufn : std_logic;
+	signal out27_buf : std_logic := '0';
+	signal out27_bufn : std_logic;
+	signal out16_buf : std_logic := '0';
+	signal out16_bufn : std_logic;
+	signal out25_buf : std_logic := '0';
+	signal out25_bufn : std_logic;
+	signal out20_buf : std_logic := '0';
+	signal out20_bufn : std_logic;
+	signal out57_buf : std_logic := '0';
+	signal out57_bufn : std_logic;
+	signal out23_buf : std_logic := '0';
+	signal out23_bufn : std_logic;
+	signal out136_buf : std_logic := '0';
+	signal out136_bufn : std_logic;
+	signal out0_buf : std_logic := '0';
+	signal out0_bufn : std_logic;
+	signal out134_buf : std_logic := '0';
+	signal out134_bufn : std_logic;
+	signal out13_buf : std_logic := '0';
+	signal out13_bufn : std_logic;
+	signal out131_buf : std_logic := '0';
+	signal out131_bufn : std_logic;
+	signal out129_buf : std_logic := '0';
+	signal out129_bufn : std_logic;
+	signal out111_buf : std_logic := '0';
+	signal out111_bufn : std_logic;
+	signal out31_buf : std_logic := '0';
+	signal out31_bufn : std_logic;
+	signal out126_buf : std_logic := '0';
+	signal out126_bufn : std_logic;
+	signal out106_buf : std_logic := '0';
+	signal out106_bufn : std_logic;
+	signal out124_buf : std_logic := '0';
+	signal out124_bufn : std_logic;
+	signal out138_buf : std_logic := '0';
+	signal out138_bufn : std_logic;
+	signal out141_buf : std_logic := '0';
+	signal out141_bufn : std_logic;
+	signal out143_buf : std_logic := '0';
+	signal out143_bufn : std_logic;
+	signal out146_buf : std_logic := '0';
+	signal out146_bufn : std_logic;
+	signal out150_buf : std_logic := '0';
+	signal out150_bufn : std_logic;
+	signal out153_buf : std_logic := '0';
+	signal out153_bufn : std_logic;
+	signal out155_buf : std_logic := '0';
+	signal out155_bufn : std_logic;
+	signal out158_buf : std_logic := '0';
+	signal out158_bufn : std_logic;
+	signal out162_buf : std_logic := '0';
+	signal out162_bufn : std_logic;
+	signal out165_buf : std_logic := '0';
+	signal out165_bufn : std_logic;
+	signal out168_buf : std_logic := '0';
+	signal out168_bufn : std_logic;
+	signal out171_buf : std_logic := '0';
+	signal out171_bufn : std_logic;
+	signal out174_buf : std_logic := '0';
+	signal out174_bufn : std_logic;
+	signal out178_buf : std_logic := '0';
+	signal out178_bufn : std_logic;
+	signal out181_buf : std_logic := '0';
+	signal out181_bufn : std_logic;
+	signal out183_buf : std_logic := '0';
+	signal out183_bufn : std_logic;
+	signal out197_buf : std_logic := '0';
+	signal out197_bufn : std_logic;
+	signal out201_buf : std_logic := '0';
+	signal out201_bufn : std_logic;
+	signal out204_buf : std_logic := '0';
+	signal out204_bufn : std_logic;
+	signal out207_buf : std_logic := '0';
+	signal out207_bufn : std_logic;
+	signal out210_buf : std_logic := '0';
+	signal out210_bufn : std_logic;
+	signal out213_buf : std_logic := '0';
+	signal out213_bufn : std_logic;
+	signal out217_buf : std_logic := '0';
+	signal out217_bufn : std_logic;
+	signal out220_buf : std_logic := '0';
+	signal out220_bufn : std_logic;
+	signal out222_buf : std_logic := '0';
+	signal out222_bufn : std_logic;
+	signal out225_buf : std_logic := '0';
+	signal out225_bufn : std_logic;
+	signal out229_buf : std_logic := '0';
+	signal out229_bufn : std_logic;
+	signal out232_buf : std_logic := '0';
+	signal out232_bufn : std_logic;
+	signal out235_buf : std_logic := '0';
+	signal out235_bufn : std_logic;
+	signal out238_buf : std_logic := '0';
+	signal out238_bufn : std_logic;
+	signal out241_buf : std_logic := '0';
+	signal out241_bufn : std_logic;
+	signal out245_buf : std_logic := '0';
+	signal out245_bufn : std_logic;
+	signal out248_buf : std_logic := '0';
+	signal out248_bufn : std_logic;
+	signal out250_buf : std_logic := '0';
+	signal out250_bufn : std_logic;
+	signal out253_buf : std_logic := '0';
+	signal out253_bufn : std_logic;
+	signal out257_buf : std_logic := '0';
+	signal out257_bufn : std_logic;
+	signal out260_buf : std_logic := '0';
+	signal out260_bufn : std_logic;
+	signal out263_buf : std_logic := '0';
+	signal out263_bufn : std_logic;
+	signal out266_buf : std_logic := '0';
+	signal out266_bufn : std_logic;
+	signal out269_buf : std_logic := '0';
+	signal out269_bufn : std_logic;
+	signal out273_buf : std_logic := '0';
+	signal out273_bufn : std_logic;
+	signal out276_buf : std_logic := '0';
+	signal out276_bufn : std_logic;
+	signal out278_buf : std_logic := '0';
+	signal out278_bufn : std_logic;
+	signal out280_buf : std_logic := '0';
+	signal out280_bufn : std_logic;
+	signal out281_buf : std_logic := '0';
+	signal out281_bufn : std_logic;
+	signal out282_buf : std_logic := '0';
+	signal out282_bufn : std_logic;
+	signal out284_buf : std_logic := '0';
+	signal out284_bufn : std_logic;
+	signal out285_buf : std_logic := '0';
+	signal out285_bufn : std_logic;
+	signal out287_buf : std_logic := '0';
+	signal out287_bufn : std_logic;
+	signal out288_buf : std_logic := '0';
+	signal out288_bufn : std_logic;
+	signal out289_buf : std_logic := '0';
+	signal out289_bufn : std_logic;
+	signal out290_buf : std_logic := '0';
+	signal out290_bufn : std_logic;
+	signal out291_buf : std_logic := '0';
+	signal out291_bufn : std_logic;
+	signal out292_buf : std_logic := '0';
+	signal out292_bufn : std_logic;
+	signal out293_buf : std_logic := '0';
+	signal out293_bufn : std_logic;
+	signal out294_buf : std_logic := '0';
+	signal out294_bufn : std_logic;
+	signal out295_buf : std_logic := '0';
+	signal out295_bufn : std_logic;
+	signal out296_buf : std_logic := '0';
+	signal out296_bufn : std_logic;
+	signal out312_buf : std_logic := '0';
+	signal out312_bufn : std_logic;
+	signal out313_buf : std_logic := '0';
+	signal out313_bufn : std_logic;
+	signal out314_buf : std_logic := '0';
+	signal out314_bufn : std_logic;
+	signal out315_buf : std_logic := '0';
+	signal out315_bufn : std_logic;
+	signal out318_buf : std_logic := '0';
+	signal out318_bufn : std_logic;
+	signal out322_buf : std_logic := '0';
+	signal out322_bufn : std_logic;
+	signal out323_buf : std_logic := '0';
+	signal out323_bufn : std_logic;
+	signal out324_buf : std_logic := '0';
+	signal out324_bufn : std_logic;
+	signal out325_buf : std_logic := '0';
+	signal out325_bufn : std_logic;
+	signal out326_buf : std_logic := '0';
+	signal out326_bufn : std_logic;
+	signal out327_buf : std_logic := '0';
+	signal out327_bufn : std_logic;
+	signal out328_buf : std_logic := '0';
+	signal out328_bufn : std_logic;
+	signal out333_buf : std_logic := '0';
+	signal out333_bufn : std_logic;
+	signal out341_buf : std_logic := '0';
+	signal out341_bufn : std_logic;
+	signal out342_buf : std_logic := '0';
+	signal out342_bufn : std_logic;
+	signal out343_buf : std_logic := '0';
+	signal out343_bufn : std_logic;
+	signal out344_buf : std_logic := '0';
+	signal out344_bufn : std_logic;
+	signal out346_buf : std_logic := '0';
+	signal out346_bufn : std_logic;
+	signal out349_buf : std_logic := '0';
+	signal out349_bufn : std_logic;
+	signal out351_buf : std_logic := '0';
+	signal out351_bufn : std_logic;
+	signal out352_buf : std_logic := '0';
+	signal out352_bufn : std_logic;
+	signal out353_buf : std_logic := '0';
+	signal out353_bufn : std_logic;
+	signal out354_buf : std_logic := '0';
+	signal out354_bufn : std_logic;
+	signal out357_buf : std_logic := '0';
+	signal out357_bufn : std_logic;
+	signal out361_buf : std_logic := '0';
+	signal out361_bufn : std_logic;
+	signal out364_buf : std_logic := '0';
+	signal out364_bufn : std_logic;
+	signal out366_buf : std_logic := '0';
+	signal out366_bufn : std_logic;
+	signal out371_buf : std_logic := '0';
+	signal out371_bufn : std_logic;
+	signal out393_buf : std_logic := '0';
+	signal out393_bufn : std_logic;
+	signal out394_buf : std_logic := '0';
+	signal out394_bufn : std_logic;
+	signal out395_buf : std_logic := '0';
+	signal out395_bufn : std_logic;
+	signal out400_buf : std_logic := '0';
+	signal out400_bufn : std_logic;
+	signal out401_buf : std_logic := '0';
+	signal out401_bufn : std_logic;
+	signal out404_buf : std_logic := '0';
+	signal out404_bufn : std_logic;
+	signal out407_buf : std_logic := '0';
+	signal out407_bufn : std_logic;
+	signal out408_buf : std_logic := '0';
+	signal out408_bufn : std_logic;
+	signal out409_buf : std_logic := '0';
+	signal out409_bufn : std_logic;
+	signal out410_buf : std_logic := '0';
+	signal out410_bufn : std_logic;
+	signal out413_buf : std_logic := '0';
+	signal out413_bufn : std_logic;
+	signal out414_buf : std_logic := '0';
+	signal out414_bufn : std_logic;
+	signal out417_buf : std_logic := '0';
+	signal out417_bufn : std_logic;
+	signal out418_buf : std_logic := '0';
+	signal out418_bufn : std_logic;
+	signal out422_buf : std_logic := '0';
+	signal out422_bufn : std_logic;
+	signal out426_buf : std_logic := '0';
+	signal out426_bufn : std_logic;
+	signal out428_buf : std_logic := '0';
+	signal out428_bufn : std_logic;
+	signal out431_buf : std_logic := '0';
+	signal out431_bufn : std_logic;
+	signal out433_buf : std_logic := '0';
+	signal out433_bufn : std_logic;
+	signal out434_buf : std_logic := '0';
+	signal out434_bufn : std_logic;
+	signal out435_buf : std_logic := '0';
+	signal out435_bufn : std_logic;
+	signal out436_buf : std_logic := '0';
+	signal out436_bufn : std_logic;
+	signal out437_buf : std_logic := '0';
+	signal out437_bufn : std_logic;
+	signal out438_buf : std_logic := '0';
+	signal out438_bufn : std_logic;
+	signal out440_buf : std_logic := '0';
+	signal out440_bufn : std_logic;
+	signal out444_buf : std_logic := '0';
+	signal out444_bufn : std_logic;
+	signal out446_buf : std_logic := '0';
+	signal out446_bufn : std_logic;
+	signal out451_buf : std_logic := '0';
+	signal out451_bufn : std_logic;
+	signal out457_buf : std_logic := '0';
+	signal out457_bufn : std_logic;
+	signal out458_buf : std_logic := '0';
+	signal out458_bufn : std_logic;
+	signal out459_buf : std_logic := '0';
+	signal out459_bufn : std_logic;
+	signal out460_buf : std_logic := '0';
+	signal out460_bufn : std_logic;
+	signal out461_buf : std_logic := '0';
+	signal out461_bufn : std_logic;
+	signal out463_buf : std_logic := '0';
+	signal out463_bufn : std_logic;
+	signal out464_buf : std_logic := '0';
+	signal out464_bufn : std_logic;
+	signal out466_buf : std_logic := '0';
+	signal out466_bufn : std_logic;
+	signal out468_buf : std_logic := '0';
+	signal out468_bufn : std_logic;
+	signal out472_buf : std_logic := '0';
+	signal out472_bufn : std_logic;
+	signal out475_buf : std_logic := '0';
+	signal out475_bufn : std_logic;
+	signal out481_buf : std_logic := '0';
+	signal out481_bufn : std_logic;
+	signal out482_buf : std_logic := '0';
+	signal out482_bufn : std_logic;
+	signal out483_buf : std_logic := '0';
+	signal out483_bufn : std_logic;
+	signal out487_buf : std_logic := '0';
+	signal out487_bufn : std_logic;
+	signal out495_buf : std_logic := '0';
+	signal out495_bufn : std_logic;
+	signal out496_buf : std_logic := '0';
+	signal out496_bufn : std_logic;
+	signal out497_buf : std_logic := '0';
+	signal out497_bufn : std_logic;
+	signal out499_buf : std_logic := '0';
+	signal out499_bufn : std_logic;
+	signal out500_buf : std_logic := '0';
+	signal out500_bufn : std_logic;
+	signal out512_buf : std_logic := '0';
+	signal out512_bufn : std_logic;
+	signal out517_buf : std_logic := '0';
+	signal out517_bufn : std_logic;
+	signal out518_buf : std_logic := '0';
+	signal out518_bufn : std_logic;
+	signal out521_buf : std_logic := '0';
+	signal out521_bufn : std_logic;
+	signal out524_buf : std_logic := '0';
+	signal out524_bufn : std_logic;
+	signal out525_buf : std_logic := '0';
+	signal out525_bufn : std_logic;
+	signal out526_buf : std_logic := '0';
+	signal out526_bufn : std_logic;
+	signal out531_buf : std_logic := '0';
+	signal out531_bufn : std_logic;
+	signal out554_buf : std_logic := '0';
+	signal out554_bufn : std_logic;
+	signal out562_buf : std_logic := '0';
+	signal out562_bufn : std_logic;
+	signal out566_buf : std_logic := '0';
+	signal out566_bufn : std_logic;
+
+	-- Retiming: counters
+	signal rtmcounter0 :      unsigned(4 downto 0) := (others => '0');
+	signal rtmcounter0_next : unsigned(4 downto 0);
+
+	-- Retiming: Output of comparators
+	signal rtmcmp90 : std_logic;
+	signal rtmcmp95 : std_logic;
+	signal rtmcmp98 : std_logic;
+	signal rtmcmp104 : std_logic;
+	signal rtmcmp148 : std_logic;
+	signal rtmcmp167 : std_logic;
+	signal rtmcmp174 : std_logic;
+	signal rtmcmp181 : std_logic;
+	signal rtmcmp183 : std_logic;
+	signal rtmcmp194 : std_logic;
+	signal rtmcmp197 : std_logic;
+	signal rtmcmp203 : std_logic;
+	signal rtmcmp205 : std_logic;
+	signal rtmcmp215 : std_logic;
+
+	-- Function calls: return IDs
+
+begin
+
+	-- Sequential process
+	-- Set the current state
+
+	process (clock)
+	begin
+		if rising_edge(clock) then
+
+			-- Next state
+			state_cur <= state_next;
+			-- Buffers for outputs
+			out122_buf <= out122_bufn;
+			out36_buf <= out36_bufn;
+			out49_buf <= out49_bufn;
+			out35_buf <= out35_bufn;
+			out27_buf <= out27_bufn;
+			out16_buf <= out16_bufn;
+			out25_buf <= out25_bufn;
+			out20_buf <= out20_bufn;
+			out57_buf <= out57_bufn;
+			out23_buf <= out23_bufn;
+			out136_buf <= out136_bufn;
+			out0_buf <= out0_bufn;
+			out134_buf <= out134_bufn;
+			out13_buf <= out13_bufn;
+			out131_buf <= out131_bufn;
+			out129_buf <= out129_bufn;
+			out111_buf <= out111_bufn;
+			out31_buf <= out31_bufn;
+			out126_buf <= out126_bufn;
+			out106_buf <= out106_bufn;
+			out124_buf <= out124_bufn;
+			out138_buf <= out138_bufn;
+			out141_buf <= out141_bufn;
+			out143_buf <= out143_bufn;
+			out146_buf <= out146_bufn;
+			out150_buf <= out150_bufn;
+			out153_buf <= out153_bufn;
+			out155_buf <= out155_bufn;
+			out158_buf <= out158_bufn;
+			out162_buf <= out162_bufn;
+			out165_buf <= out165_bufn;
+			out168_buf <= out168_bufn;
+			out171_buf <= out171_bufn;
+			out174_buf <= out174_bufn;
+			out178_buf <= out178_bufn;
+			out181_buf <= out181_bufn;
+			out183_buf <= out183_bufn;
+			out197_buf <= out197_bufn;
+			out201_buf <= out201_bufn;
+			out204_buf <= out204_bufn;
+			out207_buf <= out207_bufn;
+			out210_buf <= out210_bufn;
+			out213_buf <= out213_bufn;
+			out217_buf <= out217_bufn;
+			out220_buf <= out220_bufn;
+			out222_buf <= out222_bufn;
+			out225_buf <= out225_bufn;
+			out229_buf <= out229_bufn;
+			out232_buf <= out232_bufn;
+			out235_buf <= out235_bufn;
+			out238_buf <= out238_bufn;
+			out241_buf <= out241_bufn;
+			out245_buf <= out245_bufn;
+			out248_buf <= out248_bufn;
+			out250_buf <= out250_bufn;
+			out253_buf <= out253_bufn;
+			out257_buf <= out257_bufn;
+			out260_buf <= out260_bufn;
+			out263_buf <= out263_bufn;
+			out266_buf <= out266_bufn;
+			out269_buf <= out269_bufn;
+			out273_buf <= out273_bufn;
+			out276_buf <= out276_bufn;
+			out278_buf <= out278_bufn;
+			out280_buf <= out280_bufn;
+			out281_buf <= out281_bufn;
+			out282_buf <= out282_bufn;
+			out284_buf <= out284_bufn;
+			out285_buf <= out285_bufn;
+			out287_buf <= out287_bufn;
+			out288_buf <= out288_bufn;
+			out289_buf <= out289_bufn;
+			out290_buf <= out290_bufn;
+			out291_buf <= out291_bufn;
+			out292_buf <= out292_bufn;
+			out293_buf <= out293_bufn;
+			out294_buf <= out294_bufn;
+			out295_buf <= out295_bufn;
+			out296_buf <= out296_bufn;
+			out312_buf <= out312_bufn;
+			out313_buf <= out313_bufn;
+			out314_buf <= out314_bufn;
+			out315_buf <= out315_bufn;
+			out318_buf <= out318_bufn;
+			out322_buf <= out322_bufn;
+			out323_buf <= out323_bufn;
+			out324_buf <= out324_bufn;
+			out325_buf <= out325_bufn;
+			out326_buf <= out326_bufn;
+			out327_buf <= out327_bufn;
+			out328_buf <= out328_bufn;
+			out333_buf <= out333_bufn;
+			out341_buf <= out341_bufn;
+			out342_buf <= out342_bufn;
+			out343_buf <= out343_bufn;
+			out344_buf <= out344_bufn;
+			out346_buf <= out346_bufn;
+			out349_buf <= out349_bufn;
+			out351_buf <= out351_bufn;
+			out352_buf <= out352_bufn;
+			out353_buf <= out353_bufn;
+			out354_buf <= out354_bufn;
+			out357_buf <= out357_bufn;
+			out361_buf <= out361_bufn;
+			out364_buf <= out364_bufn;
+			out366_buf <= out366_bufn;
+			out371_buf <= out371_bufn;
+			out393_buf <= out393_bufn;
+			out394_buf <= out394_bufn;
+			out395_buf <= out395_bufn;
+			out400_buf <= out400_bufn;
+			out401_buf <= out401_bufn;
+			out404_buf <= out404_bufn;
+			out407_buf <= out407_bufn;
+			out408_buf <= out408_bufn;
+			out409_buf <= out409_bufn;
+			out410_buf <= out410_bufn;
+			out413_buf <= out413_bufn;
+			out414_buf <= out414_bufn;
+			out417_buf <= out417_bufn;
+			out418_buf <= out418_bufn;
+			out422_buf <= out422_bufn;
+			out426_buf <= out426_bufn;
+			out428_buf <= out428_bufn;
+			out431_buf <= out431_bufn;
+			out433_buf <= out433_bufn;
+			out434_buf <= out434_bufn;
+			out435_buf <= out435_bufn;
+			out436_buf <= out436_bufn;
+			out437_buf <= out437_bufn;
+			out438_buf <= out438_bufn;
+			out440_buf <= out440_bufn;
+			out444_buf <= out444_bufn;
+			out446_buf <= out446_bufn;
+			out451_buf <= out451_bufn;
+			out457_buf <= out457_bufn;
+			out458_buf <= out458_bufn;
+			out459_buf <= out459_bufn;
+			out460_buf <= out460_bufn;
+			out461_buf <= out461_bufn;
+			out463_buf <= out463_bufn;
+			out464_buf <= out464_bufn;
+			out466_buf <= out466_bufn;
+			out468_buf <= out468_bufn;
+			out472_buf <= out472_bufn;
+			out475_buf <= out475_bufn;
+			out481_buf <= out481_bufn;
+			out482_buf <= out482_bufn;
+			out483_buf <= out483_bufn;
+			out487_buf <= out487_bufn;
+			out495_buf <= out495_bufn;
+			out496_buf <= out496_bufn;
+			out497_buf <= out497_bufn;
+			out499_buf <= out499_bufn;
+			out500_buf <= out500_bufn;
+			out512_buf <= out512_bufn;
+			out517_buf <= out517_bufn;
+			out518_buf <= out518_bufn;
+			out521_buf <= out521_bufn;
+			out524_buf <= out524_bufn;
+			out525_buf <= out525_bufn;
+			out526_buf <= out526_bufn;
+			out531_buf <= out531_bufn;
+			out554_buf <= out554_bufn;
+			out562_buf <= out562_bufn;
+			out566_buf <= out566_bufn;
+			-- Retiming: counters
+			rtmcounter0 <= rtmcounter0_next;
+			-- Function calls: return IDs
+
+		end if;
+	end process;
+
+	-- Combinatorial process
+	-- Compute the next state
+	-- Compute the outputs
+
+	process (
+		-- Inputs of the FSM
+		reset, in0, in2, in3, in4, in5, in1, in6, in11, in7, in8, in9, in10,
+		-- Retiming: outputs of the comparators
+		rtmcmp90, rtmcmp95, rtmcmp98, rtmcmp104, rtmcmp148, rtmcmp167, rtmcmp174, rtmcmp181, rtmcmp183, rtmcmp194, rtmcmp197, rtmcmp203, rtmcmp205, rtmcmp215,
+		-- Retiming: the counters
+		rtmcounter0,
+		-- Function calls: return IDs
+		-- Current state
+		state_cur
+	)
+	begin
+
+		-- Reset the next state value
+
+		state_next <= (others => '0');
+
+		-- Default value to the outputs or output buffers
+
+		out22 <= '0';
+		out4 <= '0';
+		out122_bufn <= '0';
+		out50 <= '0';
+		out121 <= '0';
+		out36_bufn <= '0';
+		out49_bufn <= '0';
+		out35_bufn <= '0';
+		out99 <= '0';
+		out52 <= '0';
+		out18 <= '0';
+		out33 <= '0';
+		out123 <= '0';
+		out101 <= '0';
+		out90 <= '0';
+		out91 <= '0';
+		out27_bufn <= '0';
+		out16_bufn <= '0';
+		out26 <= '0';
+		out21 <= '0';
+		out24 <= '0';
+		out54 <= '0';
+		out25_bufn <= '0';
+		out20_bufn <= '0';
+		out58 <= '0';
+		out30 <= '0';
+		out8 <= '0';
+		out57_bufn <= '0';
+		out48 <= '0';
+		out56 <= '0';
+		out23_bufn <= '0';
+		out29 <= '0';
+		out19 <= '0';
+		out136_bufn <= '0';
+		out2 <= '0';
+		out1 <= '0';
+		out46 <= '0';
+		out0_bufn <= '0';
+		out135 <= '0';
+		out118 <= '0';
+		out116 <= '0';
+		out14 <= '0';
+		out134_bufn <= '0';
+		out28 <= '0';
+		out13_bufn <= '0';
+		out133 <= '0';
+		out131_bufn <= '0';
+		out132 <= '0';
+		out114 <= '0';
+		out130 <= '0';
+		out112 <= '0';
+		out38 <= '0';
+		out44 <= '0';
+		out97 <= '0';
+		out129_bufn <= '0';
+		out111_bufn <= '0';
+		out31_bufn <= '0';
+		out126_bufn <= '0';
+		out107 <= '0';
+		out108 <= '0';
+		out105 <= '0';
+		out106_bufn <= '0';
+		out125 <= '0';
+		out120 <= '0';
+		out124_bufn <= '0';
+		out103 <= '0';
+		out42 <= '0';
+		out40 <= '0';
+		out60 <= '0';
+		out137 <= '0';
+		out138_bufn <= '0';
+		out140 <= '0';
+		out141_bufn <= '0';
+		out142 <= '0';
+		out143_bufn <= '0';
+		out145 <= '0';
+		out146_bufn <= '0';
+		out148 <= '0';
+		out150_bufn <= '0';
+		out153_bufn <= '0';
+		out154 <= '0';
+		out155_bufn <= '0';
+		out156 <= '0';
+		out157 <= '0';
+		out158_bufn <= '0';
+		out159 <= '0';
+		out160 <= '0';
+		out161 <= '0';
+		out162_bufn <= '0';
+		out164 <= '0';
+		out165_bufn <= '0';
+		out167 <= '0';
+		out168_bufn <= '0';
+		out170 <= '0';
+		out171_bufn <= '0';
+		out173 <= '0';
+		out174_bufn <= '0';
+		out176 <= '0';
+		out178_bufn <= '0';
+		out181_bufn <= '0';
+		out182 <= '0';
+		out183_bufn <= '0';
+		out184 <= '0';
+		out185 <= '0';
+		out186 <= '0';
+		out187 <= '0';
+		out190 <= '0';
+		out195 <= '0';
+		out197_bufn <= '0';
+		out198 <= '0';
+		out199 <= '0';
+		out200 <= '0';
+		out201_bufn <= '0';
+		out203 <= '0';
+		out204_bufn <= '0';
+		out206 <= '0';
+		out207_bufn <= '0';
+		out209 <= '0';
+		out210_bufn <= '0';
+		out212 <= '0';
+		out213_bufn <= '0';
+		out215 <= '0';
+		out217_bufn <= '0';
+		out220_bufn <= '0';
+		out221 <= '0';
+		out222_bufn <= '0';
+		out223 <= '0';
+		out224 <= '0';
+		out225_bufn <= '0';
+		out226 <= '0';
+		out227 <= '0';
+		out228 <= '0';
+		out229_bufn <= '0';
+		out231 <= '0';
+		out232_bufn <= '0';
+		out234 <= '0';
+		out235_bufn <= '0';
+		out237 <= '0';
+		out238_bufn <= '0';
+		out240 <= '0';
+		out241_bufn <= '0';
+		out243 <= '0';
+		out245_bufn <= '0';
+		out248_bufn <= '0';
+		out249 <= '0';
+		out250_bufn <= '0';
+		out251 <= '0';
+		out252 <= '0';
+		out253_bufn <= '0';
+		out254 <= '0';
+		out255 <= '0';
+		out256 <= '0';
+		out257_bufn <= '0';
+		out259 <= '0';
+		out260_bufn <= '0';
+		out262 <= '0';
+		out263_bufn <= '0';
+		out265 <= '0';
+		out266_bufn <= '0';
+		out268 <= '0';
+		out269_bufn <= '0';
+		out271 <= '0';
+		out273_bufn <= '0';
+		out276_bufn <= '0';
+		out277 <= '0';
+		out278_bufn <= '0';
+		out279 <= '0';
+		out280_bufn <= '0';
+		out281_bufn <= '0';
+		out282_bufn <= '0';
+		out283 <= '0';
+		out284_bufn <= '0';
+		out285_bufn <= '0';
+		out286 <= '0';
+		out287_bufn <= '0';
+		out288_bufn <= '0';
+		out289_bufn <= '0';
+		out290_bufn <= '0';
+		out291_bufn <= '0';
+		out292_bufn <= '0';
+		out293_bufn <= '0';
+		out294_bufn <= '0';
+		out295_bufn <= '0';
+		out296_bufn <= '0';
+		out297 <= '0';
+		out298 <= '0';
+		out311 <= '0';
+		out312_bufn <= '0';
+		out313_bufn <= '0';
+		out314_bufn <= '0';
+		out315_bufn <= '0';
+		out316 <= '0';
+		out318_bufn <= '0';
+		out321 <= '0';
+		out322_bufn <= '0';
+		out323_bufn <= '0';
+		out324_bufn <= '0';
+		out325_bufn <= '0';
+		out326_bufn <= '0';
+		out327_bufn <= '0';
+		out328_bufn <= '0';
+		out329 <= '0';
+		out333_bufn <= '0';
+		out341_bufn <= '0';
+		out342_bufn <= '0';
+		out343_bufn <= '0';
+		out344_bufn <= '0';
+		out345 <= '0';
+		out346_bufn <= '0';
+		out349_bufn <= '0';
+		out350 <= '0';
+		out351_bufn <= '0';
+		out352_bufn <= '0';
+		out353_bufn <= '0';
+		out354_bufn <= '0';
+		out355 <= '0';
+		out357_bufn <= '0';
+		out361_bufn <= '0';
+		out362 <= '0';
+		out363 <= '0';
+		out364_bufn <= '0';
+		out366_bufn <= '0';
+		out367 <= '0';
+		out371_bufn <= '0';
+		out372 <= '0';
+		out373 <= '0';
+		out382 <= '0';
+		out383 <= '0';
+		out385 <= '0';
+		out393_bufn <= '0';
+		out394_bufn <= '0';
+		out395_bufn <= '0';
+		out396 <= '0';
+		out398 <= '0';
+		out400_bufn <= '0';
+		out401_bufn <= '0';
+		out402 <= '0';
+		out404_bufn <= '0';
+		out406 <= '0';
+		out407_bufn <= '0';
+		out408_bufn <= '0';
+		out409_bufn <= '0';
+		out410_bufn <= '0';
+		out411 <= '0';
+		out412 <= '0';
+		out413_bufn <= '0';
+		out414_bufn <= '0';
+		out416 <= '0';
+		out417_bufn <= '0';
+		out418_bufn <= '0';
+		out419 <= '0';
+		out422_bufn <= '0';
+		out423 <= '0';
+		out425 <= '0';
+		out426_bufn <= '0';
+		out428_bufn <= '0';
+		out429 <= '0';
+		out430 <= '0';
+		out431_bufn <= '0';
+		out433_bufn <= '0';
+		out434_bufn <= '0';
+		out435_bufn <= '0';
+		out436_bufn <= '0';
+		out437_bufn <= '0';
+		out438_bufn <= '0';
+		out440_bufn <= '0';
+		out441 <= '0';
+		out443 <= '0';
+		out444_bufn <= '0';
+		out445 <= '0';
+		out446_bufn <= '0';
+		out447 <= '0';
+		out450 <= '0';
+		out451_bufn <= '0';
+		out454 <= '0';
+		out455 <= '0';
+		out457_bufn <= '0';
+		out458_bufn <= '0';
+		out459_bufn <= '0';
+		out460_bufn <= '0';
+		out461_bufn <= '0';
+		out462 <= '0';
+		out463_bufn <= '0';
+		out464_bufn <= '0';
+		out465 <= '0';
+		out466_bufn <= '0';
+		out467 <= '0';
+		out468_bufn <= '0';
+		out469 <= '0';
+		out472_bufn <= '0';
+		out475_bufn <= '0';
+		out481_bufn <= '0';
+		out482_bufn <= '0';
+		out483_bufn <= '0';
+		out484 <= '0';
+		out487_bufn <= '0';
+		out488 <= '0';
+		out491 <= '0';
+		out495_bufn <= '0';
+		out496_bufn <= '0';
+		out497_bufn <= '0';
+		out498 <= '0';
+		out499_bufn <= '0';
+		out500_bufn <= '0';
+		out501 <= '0';
+		out512_bufn <= '0';
+		out513 <= '0';
+		out517_bufn <= '0';
+		out518_bufn <= '0';
+		out519 <= '0';
+		out521_bufn <= '0';
+		out522 <= '0';
+		out524_bufn <= '0';
+		out525_bufn <= '0';
+		out526_bufn <= '0';
+		out527 <= '0';
+		out528 <= '0';
+		out531_bufn <= '0';
+		out540 <= '0';
+		out542 <= '0';
+		out544 <= '0';
+		out545 <= '0';
+		out554_bufn <= '0';
+		out555 <= '0';
+		out559 <= '0';
+		out560 <= '0';
+		out561 <= '0';
+		out562_bufn <= '0';
+		out563 <= '0';
+		out566_bufn <= '0';
+		out567 <= '0';
+		out570 <= '0';
+		out572 <= '0';
+		out575 <= '0';
+		out577 <= '0';
+		out578 <= '0';
+		out580 <= '0';
+		out581 <= '0';
+
+		-- Retiming: default value for counters
+		rtmcounter0_next <= (others => '0');
+
+		-- Function calls: default values (no change)
+
+		-- For all states, compute the next state bits
+		--   And the outputs, and the next value for buffered outputs
+
+		if state_cur(0) = '1' then
+			-- Next state
+			state_next(109) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out1 <= '1';
+			out2 <= '1';
+		end if;
+
+		if state_cur(1) = '1' then
+			-- Next state
+			if (in0) = '1' then
+				state_next(1) <= '1';
+				-- Next values for buffered outputs
+				out13_bufn <= '1';
+			else
+				-- Return from function: memextrct_0
+				state_next(88) <= '1';
+				-- Next values for buffered outputs
+			end if;
+			-- Assignment of non-buffered outputs
+			out14 <= '1';
+			out8 <= '1';
+			out4 <= '1';
+		end if;
+
+		if state_cur(2) = '1' then
+			-- Next state
+			state_next(1) <= '1';
+			-- Next values for buffered outputs
+			out13_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out18 <= '1';
+		end if;
+
+		if state_cur(3) = '1' then
+			-- Next state
+			state_next(0) <= '1';
+			-- Next values for buffered outputs
+			out0_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out21 <= '1';
+			out2 <= '1';
+			out19 <= '1';
+		end if;
+
+		if state_cur(4) = '1' then
+			-- Next state
+			state_next(3) <= '1';
+			-- Next values for buffered outputs
+			out20_bufn <= '1';
+			out0_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out21 <= '1';
+			out2 <= '1';
+			out22 <= '1';
+		end if;
+
+		if state_cur(5) = '1' then
+			-- Next state
+			state_next(4) <= '1';
+			-- Next values for buffered outputs
+			out23_bufn <= '1';
+			out0_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out21 <= '1';
+			out2 <= '1';
+			out24 <= '1';
+		end if;
+
+		if state_cur(6) = '1' then
+			-- Next state
+			state_next(5) <= '1';
+			-- Next values for buffered outputs
+			out25_bufn <= '1';
+			out0_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out21 <= '1';
+			out2 <= '1';
+			out26 <= '1';
+		end if;
+
+		-- Info: This is the init/reset state
+		if state_cur(7) = '1' then
+			-- Next state
+			if (not (in2)) = '1' then
+				state_next(7) <= '1';
+				-- Next values for buffered outputs
+			else
+				if (in1) = '1' then
+					state_next(60) <= '1';
+					-- Next values for buffered outputs
+				else
+					state_next(154) <= '1';
+					-- Next values for buffered outputs
+				end if;
+			end if;
+			-- Assignment of non-buffered outputs
+			out28 <= '1';
+			out29 <= '1';
+		end if;
+
+		if state_cur(8) = '1' then
+			-- Next state
+			state_next(6) <= '1';
+			-- Next values for buffered outputs
+			out27_bufn <= '1';
+			out0_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out21 <= '1';
+			out2 <= '1';
+			out30 <= '1';
+		end if;
+
+		if state_cur(9) = '1' then
+			-- Next state
+			state_next(9) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+		end if;
+
+		if state_cur(10) = '1' then
+			-- Next state
+			state_next(8) <= '1';
+			-- Next values for buffered outputs
+			out31_bufn <= '1';
+			out0_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out21 <= '1';
+			out33 <= '1';
+			out2 <= '1';
+		end if;
+
+		if state_cur(11) = '1' then
+			-- Next state
+			state_next(10) <= '1';
+			-- Next values for buffered outputs
+			out0_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out21 <= '1';
+			out2 <= '1';
+		end if;
+
+		if state_cur(12) = '1' then
+			-- Next state
+			state_next(11) <= '1';
+			-- Next values for buffered outputs
+			out35_bufn <= '1';
+			out0_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out21 <= '1';
+		end if;
+
+		if state_cur(13) = '1' then
+			-- Next state
+			state_next(12) <= '1';
+			-- Next values for buffered outputs
+			out36_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out52 <= '1';
+			out50 <= '1';
+			out48 <= '1';
+			out46 <= '1';
+			out44 <= '1';
+			out42 <= '1';
+			out40 <= '1';
+			out38 <= '1';
+		end if;
+
+		if state_cur(14) = '1' then
+			-- Next state
+			state_next(13) <= '1';
+			-- Next values for buffered outputs
+			out49_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out60 <= '1';
+			out58 <= '1';
+			out56 <= '1';
+			out54 <= '1';
+		end if;
+
+		if state_cur(15) = '1' then
+			-- Next state
+			if (in3) = '1' then
+				state_next(15) <= '1';
+				-- Next values for buffered outputs
+				out13_bufn <= '1';
+			else
+				-- Return from function: memextrct_1
+				state_next(88) <= '1';
+				-- Next values for buffered outputs
+			end if;
+			-- Assignment of non-buffered outputs
+			out14 <= '1';
+			out91 <= '1';
+			out90 <= '1';
+		end if;
+
+		if state_cur(16) = '1' then
+			-- Next state
+			if (in5) = '1' then
+				-- Function call: memextrct_1
+				state_next(19) <= '1';
+				-- Next values for buffered outputs
+				out16_bufn <= '1';
+			else
+				if (in4) = '1' then
+					-- Function call: memextrct_0
+					state_next(2) <= '1';
+					-- Next values for buffered outputs
+					out16_bufn <= '1';
+				else
+					state_next(88) <= '1';
+					-- Next values for buffered outputs
+				end if;
+			end if;
+			-- Assignment of non-buffered outputs
+			out97 <= '1';
+		end if;
+
+		if state_cur(17) = '1' then
+			-- Next state
+			state_next(14) <= '1';
+			-- Next values for buffered outputs
+			out57_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out105 <= '1';
+			out103 <= '1';
+			out101 <= '1';
+			out99 <= '1';
+		end if;
+
+		if state_cur(18) = '1' then
+			-- Next state
+			state_next(17) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out120 <= '1';
+			out118 <= '1';
+			out116 <= '1';
+			out114 <= '1';
+			out112 <= '1';
+			out108 <= '1';
+			out107 <= '1';
+		end if;
+
+		if state_cur(19) = '1' then
+			-- Next state
+			state_next(15) <= '1';
+			-- Next values for buffered outputs
+			out13_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out18 <= '1';
+		end if;
+
+		if state_cur(20) = '1' then
+			-- Next state
+			state_next(18) <= '1';
+			-- Next values for buffered outputs
+			out111_bufn <= '1';
+			out106_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out52 <= '1';
+			out21 <= '1';
+			out125 <= '1';
+			out123 <= '1';
+			out108 <= '1';
+			out121 <= '1';
+		end if;
+
+		if state_cur(21) = '1' then
+			-- Next state
+			state_next(20) <= '1';
+			-- Next values for buffered outputs
+			out126_bufn <= '1';
+			out20_bufn <= '1';
+			out124_bufn <= '1';
+			out122_bufn <= '1';
+			out106_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out132 <= '1';
+			out50 <= '1';
+			out21 <= '1';
+			out130 <= '1';
+			out108 <= '1';
+		end if;
+
+		if state_cur(22) = '1' then
+			-- Next state
+			state_next(21) <= '1';
+			-- Next values for buffered outputs
+			out131_bufn <= '1';
+			out23_bufn <= '1';
+			out129_bufn <= '1';
+			out106_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out48 <= '1';
+			out21 <= '1';
+			out137 <= '1';
+			out135 <= '1';
+			out108 <= '1';
+			out133 <= '1';
+		end if;
+
+		if state_cur(23) = '1' then
+			-- Next state
+			state_next(22) <= '1';
+			-- Next values for buffered outputs
+			out138_bufn <= '1';
+			out25_bufn <= '1';
+			out136_bufn <= '1';
+			out134_bufn <= '1';
+			out106_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out46 <= '1';
+			out21 <= '1';
+			out142 <= '1';
+			out140 <= '1';
+			out108 <= '1';
+		end if;
+
+		if state_cur(24) = '1' then
+			-- Next state
+			state_next(23) <= '1';
+			-- Next values for buffered outputs
+			out143_bufn <= '1';
+			out27_bufn <= '1';
+			out141_bufn <= '1';
+			out106_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out44 <= '1';
+			out21 <= '1';
+			out145 <= '1';
+			out108 <= '1';
+		end if;
+
+		if state_cur(25) = '1' then
+			-- Next state
+			state_next(24) <= '1';
+			-- Next values for buffered outputs
+			out146_bufn <= '1';
+			out31_bufn <= '1';
+			out106_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out42 <= '1';
+			out21 <= '1';
+			out148 <= '1';
+			out108 <= '1';
+		end if;
+
+		if state_cur(26) = '1' then
+			-- Next state
+			state_next(25) <= '1';
+			-- Next values for buffered outputs
+			out150_bufn <= '1';
+			out106_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out154 <= '1';
+			out40 <= '1';
+			out21 <= '1';
+			out108 <= '1';
+		end if;
+
+		if state_cur(27) = '1' then
+			-- Next state
+			state_next(26) <= '1';
+			-- Next values for buffered outputs
+			out153_bufn <= '1';
+			out35_bufn <= '1';
+			out106_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out156 <= '1';
+			out38 <= '1';
+			out21 <= '1';
+		end if;
+
+		if state_cur(28) = '1' then
+			-- Next state
+			state_next(27) <= '1';
+			-- Next values for buffered outputs
+			out155_bufn <= '1';
+			out36_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out50 <= '1';
+			out46 <= '1';
+			out52 <= '1';
+			out48 <= '1';
+			out44 <= '1';
+			out42 <= '1';
+			out40 <= '1';
+			out38 <= '1';
+		end if;
+
+		if state_cur(29) = '1' then
+			-- Next state
+			state_next(28) <= '1';
+			-- Next values for buffered outputs
+			out49_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out60 <= '1';
+			out157 <= '1';
+			out58 <= '1';
+			out56 <= '1';
+			out54 <= '1';
+		end if;
+
+		if state_cur(30) = '1' then
+			-- Next state
+			state_next(29) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out105 <= '1';
+			out103 <= '1';
+			out101 <= '1';
+			out99 <= '1';
+		end if;
+
+		if state_cur(31) = '1' then
+			-- Next state
+			state_next(30) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out120 <= '1';
+			out118 <= '1';
+			out116 <= '1';
+			out114 <= '1';
+			out112 <= '1';
+			out160 <= '1';
+			out159 <= '1';
+		end if;
+
+		if state_cur(32) = '1' then
+			-- Next state
+			state_next(31) <= '1';
+			-- Next values for buffered outputs
+			out111_bufn <= '1';
+			out158_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out52 <= '1';
+			out21 <= '1';
+			out125 <= '1';
+			out123 <= '1';
+			out161 <= '1';
+			out160 <= '1';
+		end if;
+
+		if state_cur(33) = '1' then
+			-- Next state
+			state_next(32) <= '1';
+			-- Next values for buffered outputs
+			out162_bufn <= '1';
+			out20_bufn <= '1';
+			out124_bufn <= '1';
+			out122_bufn <= '1';
+			out158_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out50 <= '1';
+			out21 <= '1';
+			out130 <= '1';
+			out164 <= '1';
+			out160 <= '1';
+		end if;
+
+		if state_cur(34) = '1' then
+			-- Next state
+			state_next(33) <= '1';
+			-- Next values for buffered outputs
+			out165_bufn <= '1';
+			out23_bufn <= '1';
+			out129_bufn <= '1';
+			out158_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out48 <= '1';
+			out21 <= '1';
+			out137 <= '1';
+			out135 <= '1';
+			out167 <= '1';
+			out160 <= '1';
+		end if;
+
+		if state_cur(35) = '1' then
+			-- Next state
+			state_next(34) <= '1';
+			-- Next values for buffered outputs
+			out168_bufn <= '1';
+			out25_bufn <= '1';
+			out136_bufn <= '1';
+			out134_bufn <= '1';
+			out158_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out46 <= '1';
+			out21 <= '1';
+			out142 <= '1';
+			out170 <= '1';
+			out160 <= '1';
+		end if;
+
+		if state_cur(36) = '1' then
+			-- Next state
+			state_next(35) <= '1';
+			-- Next values for buffered outputs
+			out171_bufn <= '1';
+			out27_bufn <= '1';
+			out141_bufn <= '1';
+			out158_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out44 <= '1';
+			out21 <= '1';
+			out173 <= '1';
+			out160 <= '1';
+		end if;
+
+		if state_cur(37) = '1' then
+			-- Next state
+			state_next(36) <= '1';
+			-- Next values for buffered outputs
+			out174_bufn <= '1';
+			out31_bufn <= '1';
+			out158_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out42 <= '1';
+			out21 <= '1';
+			out176 <= '1';
+			out160 <= '1';
+		end if;
+
+		if state_cur(38) = '1' then
+			-- Next state
+			state_next(37) <= '1';
+			-- Next values for buffered outputs
+			out178_bufn <= '1';
+			out158_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out182 <= '1';
+			out40 <= '1';
+			out21 <= '1';
+			out160 <= '1';
+		end if;
+
+		if state_cur(39) = '1' then
+			-- Next state
+			state_next(38) <= '1';
+			-- Next values for buffered outputs
+			out181_bufn <= '1';
+			out35_bufn <= '1';
+			out158_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out184 <= '1';
+			out38 <= '1';
+			out21 <= '1';
+		end if;
+
+		if state_cur(40) = '1' then
+			-- Next state
+			state_next(39) <= '1';
+			-- Next values for buffered outputs
+			out183_bufn <= '1';
+			out36_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out50 <= '1';
+			out46 <= '1';
+			out52 <= '1';
+			out48 <= '1';
+			out44 <= '1';
+			out42 <= '1';
+			out40 <= '1';
+			out38 <= '1';
+		end if;
+
+		if state_cur(41) = '1' then
+			-- Next state
+			state_next(40) <= '1';
+			-- Next values for buffered outputs
+			out49_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out60 <= '1';
+			out185 <= '1';
+			out58 <= '1';
+			out56 <= '1';
+			out54 <= '1';
+		end if;
+
+		if state_cur(42) = '1' then
+			-- Next state
+			state_next(41) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out105 <= '1';
+			out103 <= '1';
+			out101 <= '1';
+			out99 <= '1';
+		end if;
+
+		if state_cur(43) = '1' then
+			-- Next state
+			if (in7) = '1' then
+				state_next(60) <= '1';
+				-- Next values for buffered outputs
+			else
+				if (not (in6)) = '1' then
+					state_next(43) <= '1';
+					-- Next values for buffered outputs
+				else
+					state_next(108) <= '1';
+					-- Next values for buffered outputs
+					out371_bufn <= '1';
+				end if;
+			end if;
+			-- Assignment of non-buffered outputs
+			out190 <= '1';
+			out187 <= '1';
+			out186 <= '1';
+		end if;
+
+		if state_cur(44) = '1' then
+			-- Next state
+			if (in7) = '1' then
+				state_next(60) <= '1';
+				-- Next values for buffered outputs
+			else
+				if (not (in8)) = '1' then
+					state_next(44) <= '1';
+					-- Next values for buffered outputs
+				else
+					state_next(110) <= '1';
+					-- Next values for buffered outputs
+					out371_bufn <= '1';
+				end if;
+			end if;
+			-- Assignment of non-buffered outputs
+			out195 <= '1';
+			out187 <= '1';
+		end if;
+
+		if state_cur(45) = '1' then
+			-- Next state
+			state_next(42) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out120 <= '1';
+			out118 <= '1';
+			out116 <= '1';
+			out114 <= '1';
+			out112 <= '1';
+			out199 <= '1';
+			out198 <= '1';
+		end if;
+
+		if state_cur(46) = '1' then
+			-- Next state
+			state_next(45) <= '1';
+			-- Next values for buffered outputs
+			out111_bufn <= '1';
+			out197_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out52 <= '1';
+			out21 <= '1';
+			out125 <= '1';
+			out123 <= '1';
+			out200 <= '1';
+			out199 <= '1';
+		end if;
+
+		if state_cur(47) = '1' then
+			-- Next state
+			state_next(46) <= '1';
+			-- Next values for buffered outputs
+			out201_bufn <= '1';
+			out20_bufn <= '1';
+			out124_bufn <= '1';
+			out122_bufn <= '1';
+			out197_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out50 <= '1';
+			out21 <= '1';
+			out130 <= '1';
+			out203 <= '1';
+			out199 <= '1';
+		end if;
+
+		if state_cur(48) = '1' then
+			-- Next state
+			state_next(47) <= '1';
+			-- Next values for buffered outputs
+			out204_bufn <= '1';
+			out23_bufn <= '1';
+			out129_bufn <= '1';
+			out197_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out48 <= '1';
+			out21 <= '1';
+			out137 <= '1';
+			out135 <= '1';
+			out206 <= '1';
+			out199 <= '1';
+		end if;
+
+		if state_cur(49) = '1' then
+			-- Next state
+			state_next(48) <= '1';
+			-- Next values for buffered outputs
+			out207_bufn <= '1';
+			out25_bufn <= '1';
+			out136_bufn <= '1';
+			out134_bufn <= '1';
+			out197_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out46 <= '1';
+			out21 <= '1';
+			out142 <= '1';
+			out209 <= '1';
+			out199 <= '1';
+		end if;
+
+		if state_cur(50) = '1' then
+			-- Next state
+			state_next(49) <= '1';
+			-- Next values for buffered outputs
+			out210_bufn <= '1';
+			out27_bufn <= '1';
+			out141_bufn <= '1';
+			out197_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out44 <= '1';
+			out21 <= '1';
+			out212 <= '1';
+			out199 <= '1';
+		end if;
+
+		if state_cur(51) = '1' then
+			-- Next state
+			state_next(50) <= '1';
+			-- Next values for buffered outputs
+			out213_bufn <= '1';
+			out31_bufn <= '1';
+			out197_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out42 <= '1';
+			out21 <= '1';
+			out215 <= '1';
+			out199 <= '1';
+		end if;
+
+		if state_cur(52) = '1' then
+			-- Next state
+			state_next(51) <= '1';
+			-- Next values for buffered outputs
+			out217_bufn <= '1';
+			out197_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out221 <= '1';
+			out40 <= '1';
+			out21 <= '1';
+			out199 <= '1';
+		end if;
+
+		if state_cur(53) = '1' then
+			-- Next state
+			state_next(52) <= '1';
+			-- Next values for buffered outputs
+			out220_bufn <= '1';
+			out35_bufn <= '1';
+			out197_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out223 <= '1';
+			out38 <= '1';
+			out21 <= '1';
+		end if;
+
+		if state_cur(54) = '1' then
+			-- Next state
+			state_next(53) <= '1';
+			-- Next values for buffered outputs
+			out222_bufn <= '1';
+			out36_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out50 <= '1';
+			out46 <= '1';
+			out52 <= '1';
+			out48 <= '1';
+			out44 <= '1';
+			out42 <= '1';
+			out40 <= '1';
+			out38 <= '1';
+		end if;
+
+		if state_cur(55) = '1' then
+			-- Next state
+			state_next(54) <= '1';
+			-- Next values for buffered outputs
+			out49_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out60 <= '1';
+			out224 <= '1';
+			out58 <= '1';
+			out56 <= '1';
+			out54 <= '1';
+		end if;
+
+		if state_cur(56) = '1' then
+			-- Next state
+			state_next(55) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out105 <= '1';
+			out103 <= '1';
+			out101 <= '1';
+			out99 <= '1';
+		end if;
+
+		if state_cur(57) = '1' then
+			-- Next state
+			state_next(56) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out120 <= '1';
+			out118 <= '1';
+			out116 <= '1';
+			out114 <= '1';
+			out112 <= '1';
+			out227 <= '1';
+			out226 <= '1';
+		end if;
+
+		if state_cur(58) = '1' then
+			-- Next state
+			state_next(57) <= '1';
+			-- Next values for buffered outputs
+			out111_bufn <= '1';
+			out225_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out52 <= '1';
+			out21 <= '1';
+			out125 <= '1';
+			out123 <= '1';
+			out228 <= '1';
+			out227 <= '1';
+		end if;
+
+		if state_cur(59) = '1' then
+			-- Next state
+			state_next(58) <= '1';
+			-- Next values for buffered outputs
+			out229_bufn <= '1';
+			out20_bufn <= '1';
+			out124_bufn <= '1';
+			out122_bufn <= '1';
+			out225_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out50 <= '1';
+			out21 <= '1';
+			out130 <= '1';
+			out231 <= '1';
+			out227 <= '1';
+		end if;
+
+		if state_cur(60) = '1' then
+			-- Next state
+			state_next(87) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out18 <= '1';
+		end if;
+
+		if state_cur(61) = '1' then
+			-- Next state
+			state_next(59) <= '1';
+			-- Next values for buffered outputs
+			out232_bufn <= '1';
+			out23_bufn <= '1';
+			out129_bufn <= '1';
+			out225_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out48 <= '1';
+			out21 <= '1';
+			out137 <= '1';
+			out135 <= '1';
+			out234 <= '1';
+			out227 <= '1';
+		end if;
+
+		if state_cur(62) = '1' then
+			-- Next state
+			state_next(61) <= '1';
+			-- Next values for buffered outputs
+			out235_bufn <= '1';
+			out25_bufn <= '1';
+			out136_bufn <= '1';
+			out134_bufn <= '1';
+			out225_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out46 <= '1';
+			out21 <= '1';
+			out142 <= '1';
+			out237 <= '1';
+			out227 <= '1';
+		end if;
+
+		if state_cur(63) = '1' then
+			-- Next state
+			state_next(62) <= '1';
+			-- Next values for buffered outputs
+			out238_bufn <= '1';
+			out27_bufn <= '1';
+			out141_bufn <= '1';
+			out225_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out44 <= '1';
+			out21 <= '1';
+			out240 <= '1';
+			out227 <= '1';
+		end if;
+
+		if state_cur(64) = '1' then
+			-- Next state
+			state_next(63) <= '1';
+			-- Next values for buffered outputs
+			out241_bufn <= '1';
+			out31_bufn <= '1';
+			out225_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out42 <= '1';
+			out21 <= '1';
+			out243 <= '1';
+			out227 <= '1';
+		end if;
+
+		if state_cur(65) = '1' then
+			-- Next state
+			state_next(64) <= '1';
+			-- Next values for buffered outputs
+			out245_bufn <= '1';
+			out225_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out249 <= '1';
+			out40 <= '1';
+			out21 <= '1';
+			out227 <= '1';
+		end if;
+
+		if state_cur(66) = '1' then
+			-- Next state
+			state_next(65) <= '1';
+			-- Next values for buffered outputs
+			out248_bufn <= '1';
+			out35_bufn <= '1';
+			out225_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out251 <= '1';
+			out38 <= '1';
+			out21 <= '1';
+		end if;
+
+		if state_cur(67) = '1' then
+			-- Next state
+			state_next(66) <= '1';
+			-- Next values for buffered outputs
+			out250_bufn <= '1';
+			out36_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out50 <= '1';
+			out46 <= '1';
+			out52 <= '1';
+			out48 <= '1';
+			out44 <= '1';
+			out42 <= '1';
+			out40 <= '1';
+			out38 <= '1';
+		end if;
+
+		if state_cur(68) = '1' then
+			-- Next state
+			state_next(67) <= '1';
+			-- Next values for buffered outputs
+			out49_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out60 <= '1';
+			out252 <= '1';
+			out58 <= '1';
+			out56 <= '1';
+			out54 <= '1';
+		end if;
+
+		if state_cur(69) = '1' then
+			-- Next state
+			state_next(68) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out105 <= '1';
+			out103 <= '1';
+			out101 <= '1';
+			out99 <= '1';
+		end if;
+
+		if state_cur(70) = '1' then
+			-- Next state
+			state_next(69) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out120 <= '1';
+			out118 <= '1';
+			out116 <= '1';
+			out114 <= '1';
+			out112 <= '1';
+			out255 <= '1';
+			out254 <= '1';
+		end if;
+
+		if state_cur(71) = '1' then
+			-- Next state
+			state_next(70) <= '1';
+			-- Next values for buffered outputs
+			out111_bufn <= '1';
+			out253_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out52 <= '1';
+			out21 <= '1';
+			out125 <= '1';
+			out123 <= '1';
+			out256 <= '1';
+			out255 <= '1';
+		end if;
+
+		if state_cur(72) = '1' then
+			-- Next state
+			state_next(71) <= '1';
+			-- Next values for buffered outputs
+			out257_bufn <= '1';
+			out20_bufn <= '1';
+			out124_bufn <= '1';
+			out122_bufn <= '1';
+			out253_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out50 <= '1';
+			out21 <= '1';
+			out130 <= '1';
+			out259 <= '1';
+			out255 <= '1';
+		end if;
+
+		if state_cur(73) = '1' then
+			-- Next state
+			state_next(72) <= '1';
+			-- Next values for buffered outputs
+			out260_bufn <= '1';
+			out23_bufn <= '1';
+			out129_bufn <= '1';
+			out253_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out48 <= '1';
+			out21 <= '1';
+			out137 <= '1';
+			out135 <= '1';
+			out262 <= '1';
+			out255 <= '1';
+		end if;
+
+		if state_cur(74) = '1' then
+			-- Next state
+			state_next(73) <= '1';
+			-- Next values for buffered outputs
+			out263_bufn <= '1';
+			out25_bufn <= '1';
+			out136_bufn <= '1';
+			out134_bufn <= '1';
+			out253_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out46 <= '1';
+			out21 <= '1';
+			out142 <= '1';
+			out265 <= '1';
+			out255 <= '1';
+		end if;
+
+		if state_cur(75) = '1' then
+			-- Next state
+			state_next(74) <= '1';
+			-- Next values for buffered outputs
+			out266_bufn <= '1';
+			out27_bufn <= '1';
+			out141_bufn <= '1';
+			out253_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out44 <= '1';
+			out21 <= '1';
+			out268 <= '1';
+			out255 <= '1';
+		end if;
+
+		if state_cur(76) = '1' then
+			-- Next state
+			state_next(75) <= '1';
+			-- Next values for buffered outputs
+			out269_bufn <= '1';
+			out31_bufn <= '1';
+			out253_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out42 <= '1';
+			out21 <= '1';
+			out271 <= '1';
+			out255 <= '1';
+		end if;
+
+		if state_cur(77) = '1' then
+			-- Next state
+			state_next(76) <= '1';
+			-- Next values for buffered outputs
+			out273_bufn <= '1';
+			out253_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out277 <= '1';
+			out40 <= '1';
+			out21 <= '1';
+			out255 <= '1';
+		end if;
+
+		if state_cur(78) = '1' then
+			-- Next state
+			state_next(77) <= '1';
+			-- Next values for buffered outputs
+			out276_bufn <= '1';
+			out35_bufn <= '1';
+			out253_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out279 <= '1';
+			out38 <= '1';
+			out21 <= '1';
+		end if;
+
+		if state_cur(79) = '1' then
+			-- Next state
+			state_next(80) <= '1';
+			-- Next values for buffered outputs
+			out285_bufn <= '1';
+			out284_bufn <= '1';
+			out269_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(80) = '1' then
+			-- Next state
+			state_next(113) <= '1';
+			-- Next values for buffered outputs
+			out395_bufn <= '1';
+			out284_bufn <= '1';
+			out146_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(81) = '1' then
+			-- Next state
+			state_next(82) <= '1';
+			-- Next values for buffered outputs
+			out290_bufn <= '1';
+			out289_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(82) = '1' then
+			-- Next state
+			state_next(83) <= '1';
+			-- Next values for buffered outputs
+			out57_bufn <= '1';
+			out292_bufn <= '1';
+			out291_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(83) = '1' then
+			-- Next state
+			state_next(85) <= '1';
+			-- Next values for buffered outputs
+			out295_bufn <= '1';
+			out294_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out58 <= '1';
+			out118 <= '1';
+			out286 <= '1';
+		end if;
+
+		if state_cur(84) = '1' then
+			-- Next state
+			state_next(89) <= '1';
+			-- Next values for buffered outputs
+			out313_bufn <= '1';
+			out281_bufn <= '1';
+			out312_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(85) = '1' then
+			-- Next state
+			state_next(86) <= '1';
+			-- Next values for buffered outputs
+			out296_bufn <= '1';
+			out291_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(86) = '1' then
+			-- Next state
+			state_next(90) <= '1';
+			-- Next values for buffered outputs
+			out318_bufn <= '1';
+			out280_bufn <= '1';
+			out315_bufn <= '1';
+			out314_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(87) = '1' then
+			-- Next state
+			if (in9) = '1' then
+				state_next(87) <= '1';
+				-- Next values for buffered outputs
+			else
+				state_next(16) <= '1';
+				-- Next values for buffered outputs
+				out16_bufn <= '1';
+			end if;
+			-- Assignment of non-buffered outputs
+			out14 <= '1';
+			out298 <= '1';
+			out297 <= '1';
+		end if;
+
+		if state_cur(88) = '1' then
+			-- Next state
+			if (in1) = '1' then
+				if (in5) = '1' then
+					state_next(43) <= '1';
+					-- Next values for buffered outputs
+				else
+					state_next(44) <= '1';
+					-- Next values for buffered outputs
+				end if;
+			else
+				state_next(9) <= '1';
+				-- Next values for buffered outputs
+			end if;
+			-- Assignment of non-buffered outputs
+			out311 <= '1';
+		end if;
+
+		if state_cur(89) = '1' then
+			-- Next state
+			state_next(112) <= '1';
+			-- Next values for buffered outputs
+			out394_bufn <= '1';
+			out284_bufn <= '1';
+			out393_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(90) = '1' then
+			if rtmcmp90 = '1' then
+				-- Next state
+				state_next(93) <= '1';
+				-- Next values for buffered outputs
+				out57_bufn <= '1';
+				out325_bufn <= '1';
+				out324_bufn <= '1';
+				-- Last cycle of current state: assignment of non-buffered outputs
+				out103 <= '1';
+				out105 <= '1';
+				out56 <= '1';
+				out137 <= '1';
+				out125 <= '1';
+				out116 <= '1';
+				out283 <= '1';
+			else  -- Stay in the current state
+				state_next(90) <= '1';
+				rtmcounter0_next <= rtmcounter0 + 1;
+				-- Maintain buffered outputs
+				out318_bufn <= '1';
+				out280_bufn <= '1';
+				out315_bufn <= '1';
+				out314_bufn <= '1';
+			end if;
+			-- Assignment of non-buffered outputs;
+				out316 <= '1';
+		end if;
+
+		if state_cur(91) = '1' then
+			-- Next state
+			state_next(170) <= '1';
+			-- Next values for buffered outputs
+			out487_bufn <= '1';
+			out284_bufn <= '1';
+			out266_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+			out321 <= '1';
+		end if;
+
+		if state_cur(92) = '1' then
+			-- Next state
+			state_next(240) <= '1';
+			-- Next values for buffered outputs
+			out217_bufn <= '1';
+			out295_bufn <= '1';
+			out281_bufn <= '1';
+			out562_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(93) = '1' then
+			-- Next state
+			state_next(101) <= '1';
+			-- Next values for buffered outputs
+			out323_bufn <= '1';
+			out291_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out118 <= '1';
+			out58 <= '1';
+			out286 <= '1';
+		end if;
+
+		if state_cur(94) = '1' then
+			-- Next state
+			state_next(96) <= '1';
+			-- Next values for buffered outputs
+			out341_bufn <= '1';
+			out281_bufn <= '1';
+			out241_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(95) = '1' then
+			if rtmcmp95 = '1' then
+				-- Next state
+				state_next(210) <= '1';
+				-- Next values for buffered outputs
+				out418_bufn <= '1';
+				out351_bufn <= '1';
+				-- Last cycle of current state: assignment of non-buffered outputs
+				out130 <= '1';
+				out101 <= '1';
+				out142 <= '1';
+				out112 <= '1';
+				out99 <= '1';
+				out54 <= '1';
+				out123 <= '1';
+				out135 <= '1';
+				out114 <= '1';
+				out286 <= '1';
+			else  -- Stay in the current state
+				state_next(95) <= '1';
+				rtmcounter0_next <= rtmcounter0 + 1;
+				-- Maintain buffered outputs
+				out333_bufn <= '1';
+				out245_bufn <= '1';
+				out318_bufn <= '1';
+				out328_bufn <= '1';
+				out327_bufn <= '1';
+			end if;
+			-- Assignment of non-buffered outputs;
+				out329 <= '1';
+		end if;
+
+		if state_cur(96) = '1' then
+			-- Next state
+			state_next(91) <= '1';
+			-- Next values for buffered outputs
+			out322_bufn <= '1';
+			out281_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(97) = '1' then
+			-- Next state
+			state_next(95) <= '1';
+			-- Next values for buffered outputs
+			out333_bufn <= '1';
+			out245_bufn <= '1';
+			out318_bufn <= '1';
+			out328_bufn <= '1';
+			out327_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(98) = '1' then
+			if rtmcmp98 = '1' then
+				-- Next state
+				state_next(97) <= '1';
+				-- Next values for buffered outputs
+				out342_bufn <= '1';
+				out324_bufn <= '1';
+				-- Last cycle of current state: assignment of non-buffered outputs
+				out125 <= '1';
+				out137 <= '1';
+				out116 <= '1';
+				out56 <= '1';
+				out283 <= '1';
+			else  -- Stay in the current state
+				state_next(98) <= '1';
+				rtmcounter0_next <= rtmcounter0 + 1;
+				-- Maintain buffered outputs
+				out346_bufn <= '1';
+				out344_bufn <= '1';
+				out312_bufn <= '1';
+				out343_bufn <= '1';
+				out314_bufn <= '1';
+			end if;
+			-- Assignment of non-buffered outputs;
+				out345 <= '1';
+		end if;
+
+		if state_cur(99) = '1' then
+			-- Next state
+			state_next(119) <= '1';
+			-- Next values for buffered outputs
+			out36_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out50 <= '1';
+			out46 <= '1';
+			out52 <= '1';
+			out48 <= '1';
+			out44 <= '1';
+			out42 <= '1';
+			out40 <= '1';
+			out38 <= '1';
+		end if;
+
+		if state_cur(100) = '1' then
+			-- Next state
+			state_next(233) <= '1';
+			-- Next values for buffered outputs
+			out566_bufn <= '1';
+			out289_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out125 <= '1';
+			out286 <= '1';
+		end if;
+
+		if state_cur(101) = '1' then
+			-- Next state
+			state_next(98) <= '1';
+			-- Next values for buffered outputs
+			out346_bufn <= '1';
+			out344_bufn <= '1';
+			out312_bufn <= '1';
+			out343_bufn <= '1';
+			out314_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(102) = '1' then
+			-- Next state
+			state_next(239) <= '1';
+			-- Next values for buffered outputs
+			out49_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out60 <= '1';
+			out350 <= '1';
+			out58 <= '1';
+			out56 <= '1';
+			out54 <= '1';
+		end if;
+
+		if state_cur(103) = '1' then
+			-- Next state
+			state_next(146) <= '1';
+			-- Next values for buffered outputs
+			out401_bufn <= '1';
+			out444_bufn <= '1';
+			out294_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out120 <= '1';
+			out60 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(104) = '1' then
+			if rtmcmp104 = '1' then
+				-- Next state
+				state_next(103) <= '1';
+				-- Next values for buffered outputs
+				out352_bufn <= '1';
+				out351_bufn <= '1';
+				-- Last cycle of current state: assignment of non-buffered outputs
+				out142 <= '1';
+				out99 <= '1';
+				out130 <= '1';
+				out101 <= '1';
+				out54 <= '1';
+				out135 <= '1';
+				out123 <= '1';
+				out114 <= '1';
+				out286 <= '1';
+			else  -- Stay in the current state
+				state_next(104) <= '1';
+				rtmcounter0_next <= rtmcounter0 + 1;
+				-- Maintain buffered outputs
+				out129_bufn <= '1';
+				out357_bufn <= '1';
+				out354_bufn <= '1';
+				out353_bufn <= '1';
+				out327_bufn <= '1';
+			end if;
+			-- Assignment of non-buffered outputs;
+				out355 <= '1';
+		end if;
+
+		if state_cur(105) = '1' then
+			-- Next state
+			state_next(133) <= '1';
+			-- Next values for buffered outputs
+			out431_bufn <= '1';
+			out23_bufn <= '1';
+			out129_bufn <= '1';
+			out361_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out48 <= '1';
+			out21 <= '1';
+			out137 <= '1';
+			out135 <= '1';
+			out363 <= '1';
+			out362 <= '1';
+		end if;
+
+		if state_cur(106) = '1' then
+			-- Next state
+			state_next(186) <= '1';
+			-- Next values for buffered outputs
+			out518_bufn <= '1';
+			out284_bufn <= '1';
+			out153_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(107) = '1' then
+			-- Next state
+			state_next(148) <= '1';
+			-- Next values for buffered outputs
+			out446_bufn <= '1';
+			out413_bufn <= '1';
+			out281_bufn <= '1';
+			out250_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out112 <= '1';
+			out367 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(108) = '1' then
+			-- Next state
+			if (in10) = '1' then
+				state_next(109) <= '1';
+				-- Next values for buffered outputs
+			else
+				state_next(154) <= '1';
+				-- Next values for buffered outputs
+			end if;
+			-- Assignment of non-buffered outputs
+			out372 <= '1';
+		end if;
+
+		if state_cur(109) = '1' then
+			-- Next state
+			state_next(43) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out382 <= '1';
+			out373 <= '1';
+		end if;
+
+		if state_cur(110) = '1' then
+			-- Next state
+			if (in11) = '1' then
+				state_next(44) <= '1';
+				-- Next values for buffered outputs
+			else
+				state_next(111) <= '1';
+				-- Next values for buffered outputs
+				out284_bufn <= '1';
+			end if;
+			-- Assignment of non-buffered outputs
+			out372 <= '1';
+			out385 <= '1';
+			out383 <= '1';
+		end if;
+
+		if state_cur(111) = '1' then
+			-- Next state
+			state_next(153) <= '1';
+			-- Next values for buffered outputs
+			out422_bufn <= '1';
+			out284_bufn <= '1';
+			out278_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out372 <= '1';
+			out286 <= '1';
+		end if;
+
+		if state_cur(112) = '1' then
+			-- Next state
+			state_next(94) <= '1';
+			-- Next values for buffered outputs
+			out326_bufn <= '1';
+			out284_bufn <= '1';
+			out210_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(113) = '1' then
+			-- Next state
+			state_next(160) <= '1';
+			-- Next values for buffered outputs
+			out461_bufn <= '1';
+			out281_bufn <= '1';
+			out178_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(114) = '1' then
+			-- Next state
+			state_next(196) <= '1';
+			-- Next values for buffered outputs
+			out328_bufn <= '1';
+			out284_bufn <= '1';
+			out155_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out142 <= '1';
+			out396 <= '1';
+			out286 <= '1';
+		end if;
+
+		if state_cur(115) = '1' then
+			-- Next state
+			state_next(105) <= '1';
+			-- Next values for buffered outputs
+			out364_bufn <= '1';
+			out25_bufn <= '1';
+			out136_bufn <= '1';
+			out134_bufn <= '1';
+			out361_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out46 <= '1';
+			out21 <= '1';
+			out142 <= '1';
+			out398 <= '1';
+			out363 <= '1';
+		end if;
+
+		if state_cur(116) = '1' then
+			-- Next state
+			state_next(120) <= '1';
+			-- Next values for buffered outputs
+			out407_bufn <= '1';
+			out281_bufn <= '1';
+			out168_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(117) = '1' then
+			-- Next state
+			state_next(211) <= '1';
+			-- Next values for buffered outputs
+			out458_bufn <= '1';
+			out475_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(118) = '1' then
+			-- Next state
+			state_next(151) <= '1';
+			-- Next values for buffered outputs
+			out333_bufn <= '1';
+			out31_bufn <= '1';
+			out361_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out42 <= '1';
+			out21 <= '1';
+			out402 <= '1';
+			out363 <= '1';
+		end if;
+
+		if state_cur(119) = '1' then
+			-- Next state
+			state_next(150) <= '1';
+			-- Next values for buffered outputs
+			out366_bufn <= '1';
+			out35_bufn <= '1';
+			out361_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out406 <= '1';
+			out38 <= '1';
+			out21 <= '1';
+		end if;
+
+		if state_cur(120) = '1' then
+			-- Next state
+			state_next(121) <= '1';
+			-- Next values for buffered outputs
+			out409_bufn <= '1';
+			out281_bufn <= '1';
+			out408_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(121) = '1' then
+			-- Next state
+			state_next(139) <= '1';
+			-- Next values for buffered outputs
+			out438_bufn <= '1';
+			out284_bufn <= '1';
+			out431_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(122) = '1' then
+			-- Next state
+			state_next(123) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out120 <= '1';
+			out118 <= '1';
+			out116 <= '1';
+			out114 <= '1';
+			out112 <= '1';
+			out412 <= '1';
+			out411 <= '1';
+		end if;
+
+		if state_cur(123) = '1' then
+			-- Next state
+			state_next(212) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out103 <= '1';
+			out105 <= '1';
+			out99 <= '1';
+			out101 <= '1';
+		end if;
+
+		if state_cur(124) = '1' then
+			-- Next state
+			state_next(81) <= '1';
+			-- Next values for buffered outputs
+			out288_bufn <= '1';
+			out287_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out120 <= '1';
+			out60 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(125) = '1' then
+			-- Next state
+			state_next(128) <= '1';
+			-- Next values for buffered outputs
+			out422_bufn <= '1';
+			out287_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(126) = '1' then
+			-- Next state
+			state_next(125) <= '1';
+			-- Next values for buffered outputs
+			out414_bufn <= '1';
+			out294_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out416 <= '1';
+			out38 <= '1';
+			out286 <= '1';
+		end if;
+
+		if state_cur(127) = '1' then
+			-- Next state
+			state_next(169) <= '1';
+			-- Next values for buffered outputs
+			out417_bufn <= '1';
+			out483_bufn <= '1';
+			out482_bufn <= '1';
+			out318_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out112 <= '1';
+			out419 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(128) = '1' then
+			-- Next state
+			state_next(124) <= '1';
+			-- Next values for buffered outputs
+			out413_bufn <= '1';
+			out289_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(129) = '1' then
+			-- Next state
+			state_next(130) <= '1';
+			-- Next values for buffered outputs
+			out426_bufn <= '1';
+			out27_bufn <= '1';
+			out141_bufn <= '1';
+			out410_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out44 <= '1';
+			out21 <= '1';
+			out423 <= '1';
+			out412 <= '1';
+		end if;
+
+		if state_cur(130) = '1' then
+			-- Next state
+			state_next(143) <= '1';
+			-- Next values for buffered outputs
+			out435_bufn <= '1';
+			out25_bufn <= '1';
+			out136_bufn <= '1';
+			out134_bufn <= '1';
+			out410_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out46 <= '1';
+			out21 <= '1';
+			out142 <= '1';
+			out425 <= '1';
+			out412 <= '1';
+		end if;
+
+		if state_cur(131) = '1' then
+			-- Next state
+			state_next(102) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out103 <= '1';
+			out105 <= '1';
+			out99 <= '1';
+			out101 <= '1';
+		end if;
+
+		if state_cur(132) = '1' then
+			-- Next state
+			state_next(144) <= '1';
+			-- Next values for buffered outputs
+			out111_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out114 <= '1';
+			out429 <= '1';
+			out52 <= '1';
+			out286 <= '1';
+		end if;
+
+		if state_cur(133) = '1' then
+			-- Next state
+			state_next(237) <= '1';
+			-- Next values for buffered outputs
+			out475_bufn <= '1';
+			out20_bufn <= '1';
+			out124_bufn <= '1';
+			out122_bufn <= '1';
+			out361_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out50 <= '1';
+			out21 <= '1';
+			out130 <= '1';
+			out430 <= '1';
+			out363 <= '1';
+		end if;
+
+		if state_cur(134) = '1' then
+			-- Next state
+			state_next(227) <= '1';
+			-- Next values for buffered outputs
+			out496_bufn <= '1';
+			out284_bufn <= '1';
+			out263_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(135) = '1' then
+			-- Next state
+			state_next(117) <= '1';
+			-- Next values for buffered outputs
+			out352_bufn <= '1';
+			out281_bufn <= '1';
+			out401_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(136) = '1' then
+			-- Next state
+			state_next(135) <= '1';
+			-- Next values for buffered outputs
+			out434_bufn <= '1';
+			out281_bufn <= '1';
+			out165_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(137) = '1' then
+			-- Next state
+			state_next(228) <= '1';
+			-- Next values for buffered outputs
+			out463_bufn <= '1';
+			out284_bufn <= '1';
+			out260_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(138) = '1' then
+			-- Next state
+			state_next(137) <= '1';
+			-- Next values for buffered outputs
+			out436_bufn <= '1';
+			out281_bufn <= '1';
+			out435_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(139) = '1' then
+			-- Next state
+			state_next(229) <= '1';
+			-- Next values for buffered outputs
+			out495_bufn <= '1';
+			out284_bufn <= '1';
+			out204_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(140) = '1' then
+			-- Next state
+			state_next(126) <= '1';
+			-- Next values for buffered outputs
+			out324_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(141) = '1' then
+			-- Next state
+			state_next(142) <= '1';
+			-- Next values for buffered outputs
+			out122_bufn <= '1';
+			out134_bufn <= '1';
+			out400_bufn <= '1';
+			out327_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out116 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(142) = '1' then
+			-- Next state
+			state_next(168) <= '1';
+			-- Next values for buffered outputs
+			out481_bufn <= '1';
+			out351_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out54 <= '1';
+			out123 <= '1';
+			out135 <= '1';
+			out114 <= '1';
+			out286 <= '1';
+		end if;
+
+		if state_cur(143) = '1' then
+			-- Next state
+			state_next(149) <= '1';
+			-- Next values for buffered outputs
+			out451_bufn <= '1';
+			out23_bufn <= '1';
+			out129_bufn <= '1';
+			out410_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out48 <= '1';
+			out21 <= '1';
+			out137 <= '1';
+			out135 <= '1';
+			out441 <= '1';
+			out412 <= '1';
+		end if;
+
+		if state_cur(144) = '1' then
+			-- Next state
+			state_next(178) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out112 <= '1';
+		end if;
+
+		if state_cur(145) = '1' then
+			-- Next state
+			state_next(99) <= '1';
+			-- Next values for buffered outputs
+			out49_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out60 <= '1';
+			out443 <= '1';
+			out58 <= '1';
+			out56 <= '1';
+			out54 <= '1';
+		end if;
+
+		if state_cur(146) = '1' then
+			-- Next state
+			state_next(100) <= '1';
+			-- Next values for buffered outputs
+			out124_bufn <= '1';
+			out349_bufn <= '1';
+			out287_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out445 <= '1';
+			out50 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(147) = '1' then
+			-- Next state
+			state_next(78) <= '1';
+			-- Next values for buffered outputs
+			out278_bufn <= '1';
+			out36_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out50 <= '1';
+			out46 <= '1';
+			out52 <= '1';
+			out48 <= '1';
+			out44 <= '1';
+			out42 <= '1';
+			out40 <= '1';
+			out38 <= '1';
+		end if;
+
+		if state_cur(148) = '1' then
+			if rtmcmp148 = '1' then
+				-- Next state
+				state_next(172) <= '1';
+				-- Next values for buffered outputs
+				out296_bufn <= '1';
+				out284_bufn <= '1';
+				out220_bufn <= '1';
+				-- Last cycle of current state: assignment of non-buffered outputs
+				out103 <= '1';
+				out125 <= '1';
+				out99 <= '1';
+				out123 <= '1';
+				out283 <= '1';
+			else  -- Stay in the current state
+				state_next(148) <= '1';
+				rtmcounter0_next <= rtmcounter0 + 1;
+				-- Maintain buffered outputs
+				out446_bufn <= '1';
+				out413_bufn <= '1';
+				out281_bufn <= '1';
+				out250_bufn <= '1';
+			end if;
+			-- Assignment of non-buffered outputs;
+				out447 <= '1';
+		end if;
+
+		if state_cur(149) = '1' then
+			-- Next state
+			state_next(226) <= '1';
+			-- Next values for buffered outputs
+			out354_bufn <= '1';
+			out20_bufn <= '1';
+			out124_bufn <= '1';
+			out122_bufn <= '1';
+			out410_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out50 <= '1';
+			out21 <= '1';
+			out130 <= '1';
+			out450 <= '1';
+			out412 <= '1';
+		end if;
+
+		if state_cur(150) = '1' then
+			-- Next state
+			state_next(118) <= '1';
+			-- Next values for buffered outputs
+			out404_bufn <= '1';
+			out361_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out454 <= '1';
+			out40 <= '1';
+			out21 <= '1';
+			out363 <= '1';
+		end if;
+
+		if state_cur(151) = '1' then
+			-- Next state
+			state_next(115) <= '1';
+			-- Next values for buffered outputs
+			out393_bufn <= '1';
+			out27_bufn <= '1';
+			out141_bufn <= '1';
+			out361_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out44 <= '1';
+			out21 <= '1';
+			out455 <= '1';
+			out363 <= '1';
+		end if;
+
+		if state_cur(152) = '1' then
+			-- Next state
+			state_next(230) <= '1';
+			-- Next values for buffered outputs
+			out512_bufn <= '1';
+			out281_bufn <= '1';
+			out171_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(153) = '1' then
+			-- Next state
+			state_next(114) <= '1';
+			-- Next values for buffered outputs
+			out292_bufn <= '1';
+			out284_bufn <= '1';
+			out222_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(154) = '1' then
+			-- Next state
+			state_next(44) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out372 <= '1';
+		end if;
+
+		if state_cur(155) = '1' then
+			-- Next state
+			state_next(232) <= '1';
+			-- Next values for buffered outputs
+			out517_bufn <= '1';
+			out284_bufn <= '1';
+			out207_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(156) = '1' then
+			-- Next state
+			state_next(104) <= '1';
+			-- Next values for buffered outputs
+			out129_bufn <= '1';
+			out357_bufn <= '1';
+			out354_bufn <= '1';
+			out353_bufn <= '1';
+			out327_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(157) = '1' then
+			-- Next state
+			state_next(156) <= '1';
+			-- Next values for buffered outputs
+			out458_bufn <= '1';
+			out324_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out56 <= '1';
+			out137 <= '1';
+			out116 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(158) = '1' then
+			-- Next state
+			state_next(157) <= '1';
+			-- Next values for buffered outputs
+			out136_bufn <= '1';
+			out434_bufn <= '1';
+			out314_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(159) = '1' then
+			-- Next state
+			state_next(158) <= '1';
+			-- Next values for buffered outputs
+			out459_bufn <= '1';
+			out291_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(160) = '1' then
+			-- Next state
+			state_next(189) <= '1';
+			-- Next values for buffered outputs
+			out525_bufn <= '1';
+			out281_bufn <= '1';
+			out245_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(161) = '1' then
+			-- Next state
+			state_next(106) <= '1';
+			-- Next values for buffered outputs
+			out288_bufn <= '1';
+			out284_bufn <= '1';
+			out276_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out60 <= '1';
+			out58 <= '1';
+			out56 <= '1';
+			out54 <= '1';
+			out462 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(162) = '1' then
+			-- Next state
+			state_next(159) <= '1';
+			-- Next values for buffered outputs
+			out460_bufn <= '1';
+			out289_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(163) = '1' then
+			-- Next state
+			state_next(162) <= '1';
+			-- Next values for buffered outputs
+			out463_bufn <= '1';
+			out287_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out118 <= '1';
+			out58 <= '1';
+			out465 <= '1';
+			out48 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(164) = '1' then
+			-- Next state
+			state_next(163) <= '1';
+			-- Next values for buffered outputs
+			out57_bufn <= '1';
+			out408_bufn <= '1';
+			out464_bufn <= '1';
+			out294_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out120 <= '1';
+			out60 <= '1';
+			out103 <= '1';
+			out105 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(165) = '1' then
+			-- Next state
+			state_next(166) <= '1';
+			-- Next values for buffered outputs
+			out273_bufn <= '1';
+			out343_bufn <= '1';
+			out281_bufn <= '1';
+			out181_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(166) = '1' then
+			-- Next state
+			state_next(215) <= '1';
+			-- Next values for buffered outputs
+			out562_bufn <= '1';
+			out342_bufn <= '1';
+			out284_bufn <= '1';
+			out404_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out467 <= '1';
+			out142 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(167) = '1' then
+			if rtmcmp167 = '1' then
+				-- Next state
+				state_next(164) <= '1';
+				-- Next values for buffered outputs
+				out409_bufn <= '1';
+				out351_bufn <= '1';
+				-- Last cycle of current state: assignment of non-buffered outputs
+				out130 <= '1';
+				out101 <= '1';
+				out112 <= '1';
+				out142 <= '1';
+				out99 <= '1';
+				out54 <= '1';
+				out135 <= '1';
+				out123 <= '1';
+				out114 <= '1';
+				out286 <= '1';
+			else  -- Stay in the current state
+				state_next(167) <= '1';
+				rtmcounter0_next <= rtmcounter0 + 1;
+				-- Maintain buffered outputs
+				out475_bufn <= '1';
+				out257_bufn <= '1';
+				out472_bufn <= '1';
+				out451_bufn <= '1';
+				out468_bufn <= '1';
+				out327_bufn <= '1';
+			end if;
+			-- Assignment of non-buffered outputs;
+				out469 <= '1';
+		end if;
+
+		if state_cur(168) = '1' then
+			-- Next state
+			state_next(132) <= '1';
+			-- Next values for buffered outputs
+			out357_bufn <= '1';
+			out428_bufn <= '1';
+			out327_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out120 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(169) = '1' then
+			-- Next state
+			state_next(225) <= '1';
+			-- Next values for buffered outputs
+			out554_bufn <= '1';
+			out284_bufn <= '1';
+			out333_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out137 <= '1';
+			out135 <= '1';
+			out484 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(170) = '1' then
+			-- Next state
+			state_next(152) <= '1';
+			-- Next values for buffered outputs
+			out353_bufn <= '1';
+			out284_bufn <= '1';
+			out138_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(171) = '1' then
+			-- Next state
+			state_next(167) <= '1';
+			-- Next values for buffered outputs
+			out475_bufn <= '1';
+			out257_bufn <= '1';
+			out472_bufn <= '1';
+			out451_bufn <= '1';
+			out468_bufn <= '1';
+			out327_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(172) = '1' then
+			-- Next state
+			state_next(187) <= '1';
+			-- Next values for buffered outputs
+			out521_bufn <= '1';
+			out284_bufn <= '1';
+			out150_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out137 <= '1';
+			out135 <= '1';
+			out488 <= '1';
+			out286 <= '1';
+		end if;
+
+		if state_cur(173) = '1' then
+			-- Next state
+			state_next(84) <= '1';
+			-- Next values for buffered outputs
+			out293_bufn <= '1';
+			out281_bufn <= '1';
+			out174_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(174) = '1' then
+			if rtmcmp174 = '1' then
+				-- Next state
+				state_next(171) <= '1';
+				-- Next values for buffered outputs
+				out438_bufn <= '1';
+				out324_bufn <= '1';
+				-- Last cycle of current state: assignment of non-buffered outputs
+				out125 <= '1';
+				out137 <= '1';
+				out116 <= '1';
+				out56 <= '1';
+				out283 <= '1';
+			else  -- Stay in the current state
+				state_next(174) <= '1';
+				rtmcounter0_next <= rtmcounter0 + 1;
+				-- Maintain buffered outputs
+				out229_bufn <= '1';
+				out357_bufn <= '1';
+				out407_bufn <= '1';
+				out314_bufn <= '1';
+			end if;
+			-- Assignment of non-buffered outputs;
+				out491 <= '1';
+		end if;
+
+		if state_cur(175) = '1' then
+			-- Next state
+			state_next(174) <= '1';
+			-- Next values for buffered outputs
+			out229_bufn <= '1';
+			out357_bufn <= '1';
+			out407_bufn <= '1';
+			out314_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(176) = '1' then
+			-- Next state
+			state_next(175) <= '1';
+			-- Next values for buffered outputs
+			out495_bufn <= '1';
+			out291_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(177) = '1' then
+			-- Next state
+			state_next(176) <= '1';
+			-- Next values for buffered outputs
+			out437_bufn <= '1';
+			out289_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(178) = '1' then
+			-- Next state
+			state_next(145) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out103 <= '1';
+			out105 <= '1';
+			out99 <= '1';
+			out101 <= '1';
+		end if;
+
+		if state_cur(179) = '1' then
+			-- Next state
+			state_next(177) <= '1';
+			-- Next values for buffered outputs
+			out496_bufn <= '1';
+			out287_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out58 <= '1';
+			out118 <= '1';
+			out498 <= '1';
+			out46 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(180) = '1' then
+			-- Next state
+			state_next(179) <= '1';
+			-- Next values for buffered outputs
+			out57_bufn <= '1';
+			out497_bufn <= '1';
+			out436_bufn <= '1';
+			out294_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out120 <= '1';
+			out60 <= '1';
+			out103 <= '1';
+			out105 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(181) = '1' then
+			if rtmcmp181 = '1' then
+				-- Next state
+				state_next(180) <= '1';
+				-- Next values for buffered outputs
+				out499_bufn <= '1';
+				out351_bufn <= '1';
+				-- Last cycle of current state: assignment of non-buffered outputs
+				out130 <= '1';
+				out101 <= '1';
+				out112 <= '1';
+				out142 <= '1';
+				out99 <= '1';
+				out54 <= '1';
+				out135 <= '1';
+				out123 <= '1';
+				out114 <= '1';
+				out286 <= '1';
+			else  -- Stay in the current state
+				state_next(181) <= '1';
+				rtmcounter0_next <= rtmcounter0 + 1;
+				-- Maintain buffered outputs
+				out260_bufn <= '1';
+				out500_bufn <= '1';
+				out435_bufn <= '1';
+				out395_bufn <= '1';
+				out327_bufn <= '1';
+			end if;
+			-- Assignment of non-buffered outputs;
+				out501 <= '1';
+		end if;
+
+		if state_cur(182) = '1' then
+			-- Next state
+			state_next(181) <= '1';
+			-- Next values for buffered outputs
+			out260_bufn <= '1';
+			out500_bufn <= '1';
+			out435_bufn <= '1';
+			out395_bufn <= '1';
+			out327_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(183) = '1' then
+			if rtmcmp183 = '1' then
+				-- Next state
+				state_next(182) <= '1';
+				-- Next values for buffered outputs
+				out457_bufn <= '1';
+				out324_bufn <= '1';
+				-- Last cycle of current state: assignment of non-buffered outputs
+				out125 <= '1';
+				out137 <= '1';
+				out116 <= '1';
+				out56 <= '1';
+				out283 <= '1';
+			else  -- Stay in the current state
+				state_next(183) <= '1';
+				rtmcounter0_next <= rtmcounter0 + 1;
+				-- Maintain buffered outputs
+				out472_bufn <= '1';
+				out401_bufn <= '1';
+				out512_bufn <= '1';
+				out314_bufn <= '1';
+			end if;
+			-- Assignment of non-buffered outputs;
+				out513 <= '1';
+		end if;
+
+		if state_cur(184) = '1' then
+			-- Next state
+			state_next(183) <= '1';
+			-- Next values for buffered outputs
+			out472_bufn <= '1';
+			out401_bufn <= '1';
+			out512_bufn <= '1';
+			out314_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(185) = '1' then
+			-- Next state
+			state_next(92) <= '1';
+			-- Next values for buffered outputs
+			out323_bufn <= '1';
+			out284_bufn <= '1';
+			out217_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out105 <= '1';
+			out101 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(186) = '1' then
+			-- Next state
+			state_next(107) <= '1';
+			-- Next values for buffered outputs
+			out366_bufn <= '1';
+			out315_bufn <= '1';
+			out281_bufn <= '1';
+			out183_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out142 <= '1';
+			out519 <= '1';
+			out286 <= '1';
+		end if;
+
+		if state_cur(187) = '1' then
+			-- Next state
+			state_next(185) <= '1';
+			-- Next values for buffered outputs
+			out290_bufn <= '1';
+			out281_bufn <= '1';
+			out248_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out120 <= '1';
+			out118 <= '1';
+			out116 <= '1';
+			out114 <= '1';
+			out130 <= '1';
+			out522 <= '1';
+			out286 <= '1';
+		end if;
+
+		if state_cur(188) = '1' then
+			-- Next state
+			state_next(184) <= '1';
+			-- Next values for buffered outputs
+			out517_bufn <= '1';
+			out291_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(189) = '1' then
+			-- Next state
+			state_next(190) <= '1';
+			-- Next values for buffered outputs
+			out526_bufn <= '1';
+			out284_bufn <= '1';
+			out213_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(190) = '1' then
+			-- Next state
+			state_next(173) <= '1';
+			-- Next values for buffered outputs
+			out468_bufn <= '1';
+			out284_bufn <= '1';
+			out143_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(191) = '1' then
+			-- Next state
+			state_next(188) <= '1';
+			-- Next values for buffered outputs
+			out524_bufn <= '1';
+			out289_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(192) = '1' then
+			-- Next state
+			state_next(191) <= '1';
+			-- Next values for buffered outputs
+			out487_bufn <= '1';
+			out287_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out58 <= '1';
+			out118 <= '1';
+			out527 <= '1';
+			out44 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(193) = '1' then
+			-- Next state
+			state_next(192) <= '1';
+			-- Next values for buffered outputs
+			out57_bufn <= '1';
+			out312_bufn <= '1';
+			out433_bufn <= '1';
+			out294_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out120 <= '1';
+			out60 <= '1';
+			out103 <= '1';
+			out105 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(194) = '1' then
+			if rtmcmp194 = '1' then
+				-- Next state
+				state_next(193) <= '1';
+				-- Next values for buffered outputs
+				out351_bufn <= '1';
+				out313_bufn <= '1';
+				-- Last cycle of current state: assignment of non-buffered outputs
+				out130 <= '1';
+				out101 <= '1';
+				out112 <= '1';
+				out142 <= '1';
+				out99 <= '1';
+				out54 <= '1';
+				out123 <= '1';
+				out135 <= '1';
+				out114 <= '1';
+				out286 <= '1';
+			else  -- Stay in the current state
+				state_next(194) <= '1';
+				rtmcounter0_next <= rtmcounter0 + 1;
+				-- Maintain buffered outputs
+				out263_bufn <= '1';
+				out531_bufn <= '1';
+				out497_bufn <= '1';
+				out521_bufn <= '1';
+				out327_bufn <= '1';
+			end if;
+			-- Assignment of non-buffered outputs;
+				out528 <= '1';
+		end if;
+
+		if state_cur(195) = '1' then
+			-- Next state
+			state_next(194) <= '1';
+			-- Next values for buffered outputs
+			out263_bufn <= '1';
+			out531_bufn <= '1';
+			out497_bufn <= '1';
+			out521_bufn <= '1';
+			out327_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(196) = '1' then
+			-- Next state
+			state_next(221) <= '1';
+			-- Next values for buffered outputs
+			out281_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out130 <= '1';
+			out540 <= '1';
+			out286 <= '1';
+		end if;
+
+		if state_cur(197) = '1' then
+			if rtmcmp197 = '1' then
+				-- Next state
+				state_next(195) <= '1';
+				-- Next values for buffered outputs
+				out394_bufn <= '1';
+				out324_bufn <= '1';
+				-- Last cycle of current state: assignment of non-buffered outputs
+				out137 <= '1';
+				out125 <= '1';
+				out116 <= '1';
+				out56 <= '1';
+				out283 <= '1';
+			else  -- Stay in the current state
+				state_next(197) <= '1';
+				rtmcounter0_next <= rtmcounter0 + 1;
+				-- Maintain buffered outputs
+				out500_bufn <= '1';
+				out435_bufn <= '1';
+				out314_bufn <= '1';
+				out293_bufn <= '1';
+			end if;
+			-- Assignment of non-buffered outputs;
+				out542 <= '1';
+		end if;
+
+		if state_cur(198) = '1' then
+			-- Next state
+			state_next(197) <= '1';
+			-- Next values for buffered outputs
+			out500_bufn <= '1';
+			out435_bufn <= '1';
+			out314_bufn <= '1';
+			out293_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(199) = '1' then
+			-- Next state
+			state_next(198) <= '1';
+			-- Next values for buffered outputs
+			out326_bufn <= '1';
+			out291_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(200) = '1' then
+			-- Next state
+			state_next(199) <= '1';
+			-- Next values for buffered outputs
+			out341_bufn <= '1';
+			out289_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(201) = '1' then
+			-- Next state
+			state_next(200) <= '1';
+			-- Next values for buffered outputs
+			out287_bufn <= '1';
+			out285_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out58 <= '1';
+			out118 <= '1';
+			out544 <= '1';
+			out42 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(202) = '1' then
+			-- Next state
+			state_next(201) <= '1';
+			-- Next values for buffered outputs
+			out57_bufn <= '1';
+			out318_bufn <= '1';
+			out322_bufn <= '1';
+			out294_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out120 <= '1';
+			out60 <= '1';
+			out103 <= '1';
+			out105 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(203) = '1' then
+			if rtmcmp203 = '1' then
+				-- Next state
+				state_next(202) <= '1';
+				-- Next values for buffered outputs
+				out483_bufn <= '1';
+				out351_bufn <= '1';
+				-- Last cycle of current state: assignment of non-buffered outputs
+				out130 <= '1';
+				out101 <= '1';
+				out142 <= '1';
+				out112 <= '1';
+				out99 <= '1';
+				out54 <= '1';
+				out123 <= '1';
+				out135 <= '1';
+				out114 <= '1';
+				out286 <= '1';
+			else  -- Stay in the current state
+				state_next(203) <= '1';
+				rtmcounter0_next <= rtmcounter0 + 1;
+				-- Maintain buffered outputs
+				out393_bufn <= '1';
+				out346_bufn <= '1';
+				out344_bufn <= '1';
+				out312_bufn <= '1';
+				out518_bufn <= '1';
+				out327_bufn <= '1';
+			end if;
+			-- Assignment of non-buffered outputs;
+				out545 <= '1';
+		end if;
+
+		if state_cur(204) = '1' then
+			-- Next state
+			state_next(203) <= '1';
+			-- Next values for buffered outputs
+			out393_bufn <= '1';
+			out346_bufn <= '1';
+			out344_bufn <= '1';
+			out312_bufn <= '1';
+			out518_bufn <= '1';
+			out327_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(205) = '1' then
+			if rtmcmp205 = '1' then
+				-- Next state
+				state_next(204) <= '1';
+				-- Next values for buffered outputs
+				out554_bufn <= '1';
+				out324_bufn <= '1';
+				-- Last cycle of current state: assignment of non-buffered outputs
+				out137 <= '1';
+				out125 <= '1';
+				out116 <= '1';
+				out56 <= '1';
+				out283 <= '1';
+			else  -- Stay in the current state
+				state_next(205) <= '1';
+				rtmcounter0_next <= rtmcounter0 + 1;
+				-- Maintain buffered outputs
+				out531_bufn <= '1';
+				out426_bufn <= '1';
+				out461_bufn <= '1';
+				out314_bufn <= '1';
+			end if;
+			-- Assignment of non-buffered outputs;
+				out555 <= '1';
+		end if;
+
+		if state_cur(206) = '1' then
+			-- Next state
+			state_next(205) <= '1';
+			-- Next values for buffered outputs
+			out531_bufn <= '1';
+			out426_bufn <= '1';
+			out461_bufn <= '1';
+			out314_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(207) = '1' then
+			-- Next state
+			state_next(206) <= '1';
+			-- Next values for buffered outputs
+			out526_bufn <= '1';
+			out291_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(208) = '1' then
+			-- Next state
+			state_next(207) <= '1';
+			-- Next values for buffered outputs
+			out525_bufn <= '1';
+			out289_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(209) = '1' then
+			-- Next state
+			state_next(208) <= '1';
+			-- Next values for buffered outputs
+			out466_bufn <= '1';
+			out287_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out58 <= '1';
+			out118 <= '1';
+			out559 <= '1';
+			out40 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(210) = '1' then
+			-- Next state
+			state_next(209) <= '1';
+			-- Next values for buffered outputs
+			out57_bufn <= '1';
+			out417_bufn <= '1';
+			out294_bufn <= '1';
+			out282_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out120 <= '1';
+			out60 <= '1';
+			out103 <= '1';
+			out105 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(211) = '1' then
+			-- Next state
+			state_next(224) <= '1';
+			-- Next values for buffered outputs
+			out459_bufn <= '1';
+			out284_bufn <= '1';
+			out201_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out560 <= '1';
+			out286 <= '1';
+		end if;
+
+		if state_cur(212) = '1' then
+			-- Next state
+			state_next(147) <= '1';
+			-- Next values for buffered outputs
+			out49_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out60 <= '1';
+			out561 <= '1';
+			out58 <= '1';
+			out56 <= '1';
+			out54 <= '1';
+		end if;
+
+		if state_cur(213) = '1' then
+			-- Next state
+			state_next(134) <= '1';
+			-- Next values for buffered outputs
+			out433_bufn <= '1';
+			out281_bufn <= '1';
+			out426_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(214) = '1' then
+			-- Next state
+			state_next(140) <= '1';
+			-- Next values for buffered outputs
+			out351_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(215) = '1' then
+			if rtmcmp215 = '1' then
+				-- Next state
+				state_next(127) <= '1';
+				-- Next values for buffered outputs
+				out404_bufn <= '1';
+				out418_bufn <= '1';
+				out281_bufn <= '1';
+				out417_bufn <= '1';
+				-- Last cycle of current state: assignment of non-buffered outputs
+				out125 <= '1';
+				out123 <= '1';
+				out286 <= '1';
+			else  -- Stay in the current state
+				state_next(215) <= '1';
+				rtmcounter0_next <= rtmcounter0 + 1;
+				-- Maintain buffered outputs
+				out562_bufn <= '1';
+				out342_bufn <= '1';
+				out284_bufn <= '1';
+				out404_bufn <= '1';
+			end if;
+			-- Assignment of non-buffered outputs;
+				out563 <= '1';
+		end if;
+
+		if state_cur(216) = '1' then
+			-- Next state
+			state_next(214) <= '1';
+			-- Next values for buffered outputs
+			out482_bufn <= '1';
+			out481_bufn <= '1';
+			out357_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(217) = '1' then
+			-- Next state
+			state_next(216) <= '1';
+			-- Next values for buffered outputs
+			out444_bufn <= '1';
+			out281_bufn <= '1';
+			out354_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(218) = '1' then
+			-- Next state
+			state_next(217) <= '1';
+			-- Next values for buffered outputs
+			out566_bufn <= '1';
+			out281_bufn <= '1';
+			out229_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(219) = '1' then
+			-- Next state
+			state_next(218) <= '1';
+			-- Next values for buffered outputs
+			out440_bufn <= '1';
+			out281_bufn <= '1';
+			out162_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(220) = '1' then
+			-- Next state
+			state_next(219) <= '1';
+			-- Next values for buffered outputs
+			out349_bufn <= '1';
+			out284_bufn <= '1';
+			out257_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(221) = '1' then
+			-- Next state
+			state_next(223) <= '1';
+			-- Next values for buffered outputs
+			out325_bufn <= '1';
+			out284_bufn <= '1';
+			out366_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out112 <= '1';
+			out567 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(222) = '1' then
+			-- Next state
+			state_next(220) <= '1';
+			-- Next values for buffered outputs
+			out464_bufn <= '1';
+			out281_bufn <= '1';
+			out451_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(223) = '1' then
+			-- Next state
+			state_next(161) <= '1';
+			-- Next values for buffered outputs
+			out57_bufn <= '1';
+			out414_bufn <= '1';
+			out446_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out105 <= '1';
+			out103 <= '1';
+			out101 <= '1';
+			out99 <= '1';
+			out286 <= '1';
+		end if;
+
+		if state_cur(224) = '1' then
+			-- Next state
+			state_next(222) <= '1';
+			-- Next values for buffered outputs
+			out460_bufn <= '1';
+			out281_bufn <= '1';
+			out232_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(225) = '1' then
+			-- Next state
+			state_next(79) <= '1';
+			-- Next values for buffered outputs
+			out282_bufn <= '1';
+			out281_bufn <= '1';
+			out280_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(226) = '1' then
+			-- Next state
+			state_next(122) <= '1';
+			-- Next values for buffered outputs
+			out111_bufn <= '1';
+			out410_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out52 <= '1';
+			out21 <= '1';
+			out125 <= '1';
+			out123 <= '1';
+			out570 <= '1';
+			out412 <= '1';
+		end if;
+
+		if state_cur(227) = '1' then
+			-- Next state
+			state_next(116) <= '1';
+			-- Next values for buffered outputs
+			out400_bufn <= '1';
+			out284_bufn <= '1';
+			out131_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(228) = '1' then
+			-- Next state
+			state_next(136) <= '1';
+			-- Next values for buffered outputs
+			out428_bufn <= '1';
+			out284_bufn <= '1';
+			out126_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(229) = '1' then
+			-- Next state
+			state_next(138) <= '1';
+			-- Next values for buffered outputs
+			out437_bufn <= '1';
+			out281_bufn <= '1';
+			out235_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(230) = '1' then
+			-- Next state
+			state_next(231) <= '1';
+			-- Next values for buffered outputs
+			out499_bufn <= '1';
+			out281_bufn <= '1';
+			out497_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(231) = '1' then
+			-- Next state
+			state_next(155) <= '1';
+			-- Next values for buffered outputs
+			out457_bufn <= '1';
+			out284_bufn <= '1';
+			out364_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out283 <= '1';
+		end if;
+
+		if state_cur(232) = '1' then
+			-- Next state
+			state_next(213) <= '1';
+			-- Next values for buffered outputs
+			out524_bufn <= '1';
+			out281_bufn <= '1';
+			out238_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out286 <= '1';
+		end if;
+
+		if state_cur(233) = '1' then
+			-- Next state
+			state_next(141) <= '1';
+			-- Next values for buffered outputs
+			out440_bufn <= '1';
+			out314_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out118 <= '1';
+			out283 <= '1';
+		end if;
+
+		if state_cur(234) = '1' then
+			-- Next state
+			state_next(129) <= '1';
+			-- Next values for buffered outputs
+			out346_bufn <= '1';
+			out31_bufn <= '1';
+			out410_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out42 <= '1';
+			out21 <= '1';
+			out572 <= '1';
+			out412 <= '1';
+		end if;
+
+		if state_cur(235) = '1' then
+			-- Next state
+			state_next(131) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out120 <= '1';
+			out118 <= '1';
+			out116 <= '1';
+			out114 <= '1';
+			out112 <= '1';
+			out575 <= '1';
+			out363 <= '1';
+		end if;
+
+		if state_cur(236) = '1' then
+			-- Next state
+			state_next(234) <= '1';
+			-- Next values for buffered outputs
+			out280_bufn <= '1';
+			out410_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out577 <= '1';
+			out40 <= '1';
+			out21 <= '1';
+			out412 <= '1';
+		end if;
+
+		if state_cur(237) = '1' then
+			-- Next state
+			state_next(235) <= '1';
+			-- Next values for buffered outputs
+			out111_bufn <= '1';
+			out361_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out52 <= '1';
+			out21 <= '1';
+			out125 <= '1';
+			out123 <= '1';
+			out578 <= '1';
+			out363 <= '1';
+		end if;
+
+		if state_cur(238) = '1' then
+			-- Next state
+			state_next(236) <= '1';
+			-- Next values for buffered outputs
+			out562_bufn <= '1';
+			out35_bufn <= '1';
+			out410_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out580 <= '1';
+			out38 <= '1';
+			out21 <= '1';
+		end if;
+
+		if state_cur(239) = '1' then
+			-- Next state
+			state_next(238) <= '1';
+			-- Next values for buffered outputs
+			out446_bufn <= '1';
+			out36_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out50 <= '1';
+			out46 <= '1';
+			out52 <= '1';
+			out48 <= '1';
+			out44 <= '1';
+			out42 <= '1';
+			out40 <= '1';
+			out38 <= '1';
+		end if;
+
+		if state_cur(240) = '1' then
+			-- Next state
+			state_next(165) <= '1';
+			-- Next values for buffered outputs
+			out466_bufn <= '1';
+			out284_bufn <= '1';
+			out273_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out581 <= '1';
+			out130 <= '1';
+			out283 <= '1';
+		end if;
+
+		-- Reset input
+		if reset = '1' then
+			-- Set the reset state
+			state_next <= (7 => '1', others => '0');
+			-- Note: Resetting all buffers for outputs here is not necessary.
+			-- It would cost hardware. They will be reset at the next clock front.
+			-- Retiming: counters
+			rtmcounter0_next <= (others => '0');
+			-- Reset state: set the buffered outputs
+		end if;
+
+	end process;
+
+	-- Assignment of buffered outputs
+
+	out122 <= out122_buf;
+	out36 <= out36_buf;
+	out49 <= out49_buf;
+	out35 <= out35_buf;
+	out27 <= out27_buf;
+	out16 <= out16_buf;
+	out25 <= out25_buf;
+	out20 <= out20_buf;
+	out57 <= out57_buf;
+	out23 <= out23_buf;
+	out136 <= out136_buf;
+	out0 <= out0_buf;
+	out134 <= out134_buf;
+	out13 <= out13_buf;
+	out131 <= out131_buf;
+	out129 <= out129_buf;
+	out111 <= out111_buf;
+	out31 <= out31_buf;
+	out126 <= out126_buf;
+	out106 <= out106_buf;
+	out124 <= out124_buf;
+	out138 <= out138_buf;
+	out141 <= out141_buf;
+	out143 <= out143_buf;
+	out146 <= out146_buf;
+	out150 <= out150_buf;
+	out153 <= out153_buf;
+	out155 <= out155_buf;
+	out158 <= out158_buf;
+	out162 <= out162_buf;
+	out165 <= out165_buf;
+	out168 <= out168_buf;
+	out171 <= out171_buf;
+	out174 <= out174_buf;
+	out178 <= out178_buf;
+	out181 <= out181_buf;
+	out183 <= out183_buf;
+	out197 <= out197_buf;
+	out201 <= out201_buf;
+	out204 <= out204_buf;
+	out207 <= out207_buf;
+	out210 <= out210_buf;
+	out213 <= out213_buf;
+	out217 <= out217_buf;
+	out220 <= out220_buf;
+	out222 <= out222_buf;
+	out225 <= out225_buf;
+	out229 <= out229_buf;
+	out232 <= out232_buf;
+	out235 <= out235_buf;
+	out238 <= out238_buf;
+	out241 <= out241_buf;
+	out245 <= out245_buf;
+	out248 <= out248_buf;
+	out250 <= out250_buf;
+	out253 <= out253_buf;
+	out257 <= out257_buf;
+	out260 <= out260_buf;
+	out263 <= out263_buf;
+	out266 <= out266_buf;
+	out269 <= out269_buf;
+	out273 <= out273_buf;
+	out276 <= out276_buf;
+	out278 <= out278_buf;
+	out280 <= out280_buf;
+	out281 <= out281_buf;
+	out282 <= out282_buf;
+	out284 <= out284_buf;
+	out285 <= out285_buf;
+	out287 <= out287_buf;
+	out288 <= out288_buf;
+	out289 <= out289_buf;
+	out290 <= out290_buf;
+	out291 <= out291_buf;
+	out292 <= out292_buf;
+	out293 <= out293_buf;
+	out294 <= out294_buf;
+	out295 <= out295_buf;
+	out296 <= out296_buf;
+	out312 <= out312_buf;
+	out313 <= out313_buf;
+	out314 <= out314_buf;
+	out315 <= out315_buf;
+	out318 <= out318_buf;
+	out322 <= out322_buf;
+	out323 <= out323_buf;
+	out324 <= out324_buf;
+	out325 <= out325_buf;
+	out326 <= out326_buf;
+	out327 <= out327_buf;
+	out328 <= out328_buf;
+	out333 <= out333_buf;
+	out341 <= out341_buf;
+	out342 <= out342_buf;
+	out343 <= out343_buf;
+	out344 <= out344_buf;
+	out346 <= out346_buf;
+	out349 <= out349_buf;
+	out351 <= out351_buf;
+	out352 <= out352_buf;
+	out353 <= out353_buf;
+	out354 <= out354_buf;
+	out357 <= out357_buf;
+	out361 <= out361_buf;
+	out364 <= out364_buf;
+	out366 <= out366_buf;
+	out371 <= out371_buf;
+	out393 <= out393_buf;
+	out394 <= out394_buf;
+	out395 <= out395_buf;
+	out400 <= out400_buf;
+	out401 <= out401_buf;
+	out404 <= out404_buf;
+	out407 <= out407_buf;
+	out408 <= out408_buf;
+	out409 <= out409_buf;
+	out410 <= out410_buf;
+	out413 <= out413_buf;
+	out414 <= out414_buf;
+	out417 <= out417_buf;
+	out418 <= out418_buf;
+	out422 <= out422_buf;
+	out426 <= out426_buf;
+	out428 <= out428_buf;
+	out431 <= out431_buf;
+	out433 <= out433_buf;
+	out434 <= out434_buf;
+	out435 <= out435_buf;
+	out436 <= out436_buf;
+	out437 <= out437_buf;
+	out438 <= out438_buf;
+	out440 <= out440_buf;
+	out444 <= out444_buf;
+	out446 <= out446_buf;
+	out451 <= out451_buf;
+	out457 <= out457_buf;
+	out458 <= out458_buf;
+	out459 <= out459_buf;
+	out460 <= out460_buf;
+	out461 <= out461_buf;
+	out463 <= out463_buf;
+	out464 <= out464_buf;
+	out466 <= out466_buf;
+	out468 <= out468_buf;
+	out472 <= out472_buf;
+	out475 <= out475_buf;
+	out481 <= out481_buf;
+	out482 <= out482_buf;
+	out483 <= out483_buf;
+	out487 <= out487_buf;
+	out495 <= out495_buf;
+	out496 <= out496_buf;
+	out497 <= out497_buf;
+	out499 <= out499_buf;
+	out500 <= out500_buf;
+	out512 <= out512_buf;
+	out517 <= out517_buf;
+	out518 <= out518_buf;
+	out521 <= out521_buf;
+	out524 <= out524_buf;
+	out525 <= out525_buf;
+	out526 <= out526_buf;
+	out531 <= out531_buf;
+	out554 <= out554_buf;
+	out562 <= out562_buf;
+	out566 <= out566_buf;
+
+	-- Retiming: the comparators
+
+	rtmcmp90 <= '1' when state_cur(90) = '1' and rtmcounter0 = 1 else '0';
+	rtmcmp95 <= '1' when state_cur(95) = '1' and rtmcounter0 = 1 else '0';
+	rtmcmp98 <= '1' when state_cur(98) = '1' and rtmcounter0 = 1 else '0';
+	rtmcmp104 <= '1' when state_cur(104) = '1' and rtmcounter0 = 1 else '0';
+	rtmcmp148 <= '1' when state_cur(148) = '1' and rtmcounter0 = 1 else '0';
+	rtmcmp167 <= '1' when state_cur(167) = '1' and rtmcounter0 = 1 else '0';
+	rtmcmp174 <= '1' when state_cur(174) = '1' and rtmcounter0 = 1 else '0';
+	rtmcmp181 <= '1' when state_cur(181) = '1' and rtmcounter0 = 1 else '0';
+	rtmcmp183 <= '1' when state_cur(183) = '1' and rtmcounter0 = 1 else '0';
+	rtmcmp194 <= '1' when state_cur(194) = '1' and rtmcounter0 = 1 else '0';
+	rtmcmp197 <= '1' when state_cur(197) = '1' and rtmcounter0 = 1 else '0';
+	rtmcmp203 <= '1' when state_cur(203) = '1' and rtmcounter0 = 1 else '0';
+	rtmcmp205 <= '1' when state_cur(205) = '1' and rtmcounter0 = 1 else '0';
+	rtmcmp215 <= '1' when state_cur(215) = '1' and rtmcounter0 = 1 else '0';
+
+end architecture;
+
diff --git a/testsuite/gna/issue50/idct.d/input_split0.vhd b/testsuite/gna/issue50/idct.d/input_split0.vhd
new file mode 100644
index 000000000..56f2716b9
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/input_split0.vhd
@@ -0,0 +1,74 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity input_split0 is
+	port (
+		ra0_data : out std_logic_vector(31 downto 0);
+		ra0_addr : in  std_logic_vector(4 downto 0);
+		ra1_data : out std_logic_vector(31 downto 0);
+		ra1_addr : in  std_logic_vector(4 downto 0);
+		ra2_data : out std_logic_vector(31 downto 0);
+		ra2_addr : in  std_logic_vector(4 downto 0);
+		ra3_data : out std_logic_vector(31 downto 0);
+		ra3_addr : in  std_logic_vector(4 downto 0);
+		clk : in  std_logic;
+		wa2_data : in  std_logic_vector(31 downto 0);
+		wa2_addr : in  std_logic_vector(4 downto 0);
+		wa2_en : in  std_logic
+	);
+end input_split0;
+architecture augh of input_split0 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 31) of std_logic_vector(31 downto 0);
+	signal ram : ram_type := (others => (others => '0'));
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa2_en = '1' then
+				ram( to_integer(wa2_addr) ) <= wa2_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+	ra3_data <= ram( to_integer(ra3_addr) );
+	ra1_data <= ram( to_integer(ra1_addr) );
+	ra2_data <= ram( to_integer(ra2_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/input_split1.vhd b/testsuite/gna/issue50/idct.d/input_split1.vhd
new file mode 100644
index 000000000..8ddb9665f
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/input_split1.vhd
@@ -0,0 +1,74 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity input_split1 is
+	port (
+		wa0_data : in  std_logic_vector(31 downto 0);
+		wa0_addr : in  std_logic_vector(4 downto 0);
+		ra0_data : out std_logic_vector(31 downto 0);
+		ra0_addr : in  std_logic_vector(4 downto 0);
+		wa0_en : in  std_logic;
+		ra1_data : out std_logic_vector(31 downto 0);
+		ra1_addr : in  std_logic_vector(4 downto 0);
+		ra2_data : out std_logic_vector(31 downto 0);
+		ra2_addr : in  std_logic_vector(4 downto 0);
+		ra3_data : out std_logic_vector(31 downto 0);
+		ra3_addr : in  std_logic_vector(4 downto 0);
+		clk : in  std_logic
+	);
+end input_split1;
+architecture augh of input_split1 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 31) of std_logic_vector(31 downto 0);
+	signal ram : ram_type := (others => (others => '0'));
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+	ra3_data <= ram( to_integer(ra3_addr) );
+	ra1_data <= ram( to_integer(ra1_addr) );
+	ra2_data <= ram( to_integer(ra2_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_189.vhd b/testsuite/gna/issue50/idct.d/mul_189.vhd
new file mode 100644
index 000000000..af014926c
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_189.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_189 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(13 downto 0)
+	);
+end mul_189;
+
+architecture augh of mul_189 is
+
+	signal tmp_res : signed(44 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_190.vhd b/testsuite/gna/issue50/idct.d/mul_190.vhd
new file mode 100644
index 000000000..dbdc10130
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_190.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_190 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_190;
+
+architecture augh of mul_190 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_192.vhd b/testsuite/gna/issue50/idct.d/mul_192.vhd
new file mode 100644
index 000000000..914e1f292
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_192.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_192 is
+	port (
+		result : out std_logic_vector(29 downto 0);
+		in_a : in  std_logic_vector(29 downto 0);
+		in_b : in  std_logic_vector(10 downto 0)
+	);
+end mul_192;
+
+architecture augh of mul_192 is
+
+	signal tmp_res : signed(40 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(29 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_193.vhd b/testsuite/gna/issue50/idct.d/mul_193.vhd
new file mode 100644
index 000000000..4935cf696
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_193.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_193 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_193;
+
+architecture augh of mul_193 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_195.vhd b/testsuite/gna/issue50/idct.d/mul_195.vhd
new file mode 100644
index 000000000..22492f3b4
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_195.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_195 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_195;
+
+architecture augh of mul_195 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_196.vhd b/testsuite/gna/issue50/idct.d/mul_196.vhd
new file mode 100644
index 000000000..e298a92d2
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_196.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_196 is
+	port (
+		result : out std_logic_vector(29 downto 0);
+		in_a : in  std_logic_vector(29 downto 0);
+		in_b : in  std_logic_vector(10 downto 0)
+	);
+end mul_196;
+
+architecture augh of mul_196 is
+
+	signal tmp_res : signed(40 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(29 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_198.vhd b/testsuite/gna/issue50/idct.d/mul_198.vhd
new file mode 100644
index 000000000..48fe0c79d
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_198.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_198 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_198;
+
+architecture augh of mul_198 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_199.vhd b/testsuite/gna/issue50/idct.d/mul_199.vhd
new file mode 100644
index 000000000..d229385aa
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_199.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_199 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(13 downto 0)
+	);
+end mul_199;
+
+architecture augh of mul_199 is
+
+	signal tmp_res : signed(44 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_215.vhd b/testsuite/gna/issue50/idct.d/mul_215.vhd
new file mode 100644
index 000000000..4acb0b531
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_215.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_215 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end mul_215;
+
+architecture augh of mul_215 is
+
+	signal tmp_res : signed(47 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_216.vhd b/testsuite/gna/issue50/idct.d/mul_216.vhd
new file mode 100644
index 000000000..bb2e15bd4
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_216.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_216 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_216;
+
+architecture augh of mul_216 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_218.vhd b/testsuite/gna/issue50/idct.d/mul_218.vhd
new file mode 100644
index 000000000..f97ceb137
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_218.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_218 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_218;
+
+architecture augh of mul_218 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_219.vhd b/testsuite/gna/issue50/idct.d/mul_219.vhd
new file mode 100644
index 000000000..813e12749
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_219.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_219 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end mul_219;
+
+architecture augh of mul_219 is
+
+	signal tmp_res : signed(47 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_223.vhd b/testsuite/gna/issue50/idct.d/mul_223.vhd
new file mode 100644
index 000000000..3f28903b7
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_223.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_223 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_223;
+
+architecture augh of mul_223 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_230.vhd b/testsuite/gna/issue50/idct.d/mul_230.vhd
new file mode 100644
index 000000000..189ff3e87
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_230.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_230 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_230;
+
+architecture augh of mul_230 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_328.vhd b/testsuite/gna/issue50/idct.d/mul_328.vhd
new file mode 100644
index 000000000..374f73bef
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_328.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_328 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_328;
+
+architecture augh of mul_328 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_331.vhd b/testsuite/gna/issue50/idct.d/mul_331.vhd
new file mode 100644
index 000000000..b5b4522d7
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_331.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_331 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end mul_331;
+
+architecture augh of mul_331 is
+
+	signal tmp_res : signed(47 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_341.vhd b/testsuite/gna/issue50/idct.d/mul_341.vhd
new file mode 100644
index 000000000..49681535f
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_341.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_341 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end mul_341;
+
+architecture augh of mul_341 is
+
+	signal tmp_res : signed(47 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_344.vhd b/testsuite/gna/issue50/idct.d/mul_344.vhd
new file mode 100644
index 000000000..2bec140d1
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_344.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_344 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_344;
+
+architecture augh of mul_344 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_353.vhd b/testsuite/gna/issue50/idct.d/mul_353.vhd
new file mode 100644
index 000000000..cbb449a85
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_353.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_353 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_353;
+
+architecture augh of mul_353 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_357.vhd b/testsuite/gna/issue50/idct.d/mul_357.vhd
new file mode 100644
index 000000000..b40f2dc92
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_357.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_357 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_357;
+
+architecture augh of mul_357 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_365.vhd b/testsuite/gna/issue50/idct.d/mul_365.vhd
new file mode 100644
index 000000000..5a80b8482
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_365.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_365 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_365;
+
+architecture augh of mul_365 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_368.vhd b/testsuite/gna/issue50/idct.d/mul_368.vhd
new file mode 100644
index 000000000..52c56106d
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_368.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_368 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end mul_368;
+
+architecture augh of mul_368 is
+
+	signal tmp_res : signed(47 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_373.vhd b/testsuite/gna/issue50/idct.d/mul_373.vhd
new file mode 100644
index 000000000..78aabd06d
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_373.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_373 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end mul_373;
+
+architecture augh of mul_373 is
+
+	signal tmp_res : signed(47 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_376.vhd b/testsuite/gna/issue50/idct.d/mul_376.vhd
new file mode 100644
index 000000000..95ebdcd08
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_376.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_376 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_376;
+
+architecture augh of mul_376 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_383.vhd b/testsuite/gna/issue50/idct.d/mul_383.vhd
new file mode 100644
index 000000000..159659041
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_383.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_383 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_383;
+
+architecture augh of mul_383 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_416.vhd b/testsuite/gna/issue50/idct.d/mul_416.vhd
new file mode 100644
index 000000000..cf835ddec
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_416.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_416 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_416;
+
+architecture augh of mul_416 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_442.vhd b/testsuite/gna/issue50/idct.d/mul_442.vhd
new file mode 100644
index 000000000..e4ece2c8a
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_442.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_442 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end mul_442;
+
+architecture augh of mul_442 is
+
+	signal tmp_res : signed(47 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_445.vhd b/testsuite/gna/issue50/idct.d/mul_445.vhd
new file mode 100644
index 000000000..b47b71fc0
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_445.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_445 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_445;
+
+architecture augh of mul_445 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_447.vhd b/testsuite/gna/issue50/idct.d/mul_447.vhd
new file mode 100644
index 000000000..151f84d7d
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_447.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_447 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_447;
+
+architecture augh of mul_447 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_448.vhd b/testsuite/gna/issue50/idct.d/mul_448.vhd
new file mode 100644
index 000000000..754f77303
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_448.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_448 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end mul_448;
+
+architecture augh of mul_448 is
+
+	signal tmp_res : signed(47 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_456.vhd b/testsuite/gna/issue50/idct.d/mul_456.vhd
new file mode 100644
index 000000000..d012689f1
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_456.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_456 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_456;
+
+architecture augh of mul_456 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_457.vhd b/testsuite/gna/issue50/idct.d/mul_457.vhd
new file mode 100644
index 000000000..db623824f
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_457.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_457 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end mul_457;
+
+architecture augh of mul_457 is
+
+	signal tmp_res : signed(47 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_460.vhd b/testsuite/gna/issue50/idct.d/mul_460.vhd
new file mode 100644
index 000000000..f81f31d4c
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_460.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_460 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_460;
+
+architecture augh of mul_460 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_469.vhd b/testsuite/gna/issue50/idct.d/mul_469.vhd
new file mode 100644
index 000000000..0f9604bf7
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_469.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_469 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_469;
+
+architecture augh of mul_469 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_477.vhd b/testsuite/gna/issue50/idct.d/mul_477.vhd
new file mode 100644
index 000000000..7cc4bd860
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_477.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_477 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_477;
+
+architecture augh of mul_477 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_492.vhd b/testsuite/gna/issue50/idct.d/mul_492.vhd
new file mode 100644
index 000000000..7af8f6555
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_492.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_492 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_492;
+
+architecture augh of mul_492 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_495.vhd b/testsuite/gna/issue50/idct.d/mul_495.vhd
new file mode 100644
index 000000000..b60c4c49f
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_495.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_495 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end mul_495;
+
+architecture augh of mul_495 is
+
+	signal tmp_res : signed(47 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_499.vhd b/testsuite/gna/issue50/idct.d/mul_499.vhd
new file mode 100644
index 000000000..520b5aaa3
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_499.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_499 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end mul_499;
+
+architecture augh of mul_499 is
+
+	signal tmp_res : signed(47 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_502.vhd b/testsuite/gna/issue50/idct.d/mul_502.vhd
new file mode 100644
index 000000000..83cb843dc
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_502.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_502 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_502;
+
+architecture augh of mul_502 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_511.vhd b/testsuite/gna/issue50/idct.d/mul_511.vhd
new file mode 100644
index 000000000..a8213e358
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_511.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_511 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_511;
+
+architecture augh of mul_511 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_520.vhd b/testsuite/gna/issue50/idct.d/mul_520.vhd
new file mode 100644
index 000000000..e6703c255
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_520.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_520 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_520;
+
+architecture augh of mul_520 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_524.vhd b/testsuite/gna/issue50/idct.d/mul_524.vhd
new file mode 100644
index 000000000..f938743d6
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_524.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_524 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_524;
+
+architecture augh of mul_524 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_527.vhd b/testsuite/gna/issue50/idct.d/mul_527.vhd
new file mode 100644
index 000000000..3f636e975
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_527.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_527 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end mul_527;
+
+architecture augh of mul_527 is
+
+	signal tmp_res : signed(47 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_531.vhd b/testsuite/gna/issue50/idct.d/mul_531.vhd
new file mode 100644
index 000000000..f214ecb26
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_531.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_531 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_531;
+
+architecture augh of mul_531 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_534.vhd b/testsuite/gna/issue50/idct.d/mul_534.vhd
new file mode 100644
index 000000000..672f9820e
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_534.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_534 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_534;
+
+architecture augh of mul_534 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_540.vhd b/testsuite/gna/issue50/idct.d/mul_540.vhd
new file mode 100644
index 000000000..ed0311d61
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_540.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_540 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end mul_540;
+
+architecture augh of mul_540 is
+
+	signal tmp_res : signed(47 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_543.vhd b/testsuite/gna/issue50/idct.d/mul_543.vhd
new file mode 100644
index 000000000..782a26084
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_543.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_543 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_543;
+
+architecture augh of mul_543 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_547.vhd b/testsuite/gna/issue50/idct.d/mul_547.vhd
new file mode 100644
index 000000000..ede6a5376
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_547.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_547 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_547;
+
+architecture augh of mul_547 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_556.vhd b/testsuite/gna/issue50/idct.d/mul_556.vhd
new file mode 100644
index 000000000..2caa3f3b9
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_556.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_556 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_556;
+
+architecture augh of mul_556 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_559.vhd b/testsuite/gna/issue50/idct.d/mul_559.vhd
new file mode 100644
index 000000000..2ddad5af2
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_559.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_559 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_559;
+
+architecture augh of mul_559 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_560.vhd b/testsuite/gna/issue50/idct.d/mul_560.vhd
new file mode 100644
index 000000000..51d358c61
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_560.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_560 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_560;
+
+architecture augh of mul_560 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_561.vhd b/testsuite/gna/issue50/idct.d/mul_561.vhd
new file mode 100644
index 000000000..325c7e3ca
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_561.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_561 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end mul_561;
+
+architecture augh of mul_561 is
+
+	signal tmp_res : signed(47 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_565.vhd b/testsuite/gna/issue50/idct.d/mul_565.vhd
new file mode 100644
index 000000000..1651f8050
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_565.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_565 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end mul_565;
+
+architecture augh of mul_565 is
+
+	signal tmp_res : signed(47 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_566.vhd b/testsuite/gna/issue50/idct.d/mul_566.vhd
new file mode 100644
index 000000000..11ce8c301
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_566.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_566 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_566;
+
+architecture augh of mul_566 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_573.vhd b/testsuite/gna/issue50/idct.d/mul_573.vhd
new file mode 100644
index 000000000..9a419fe46
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_573.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_573 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_573;
+
+architecture augh of mul_573 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_577.vhd b/testsuite/gna/issue50/idct.d/mul_577.vhd
new file mode 100644
index 000000000..b8e3f024b
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_577.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_577 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_577;
+
+architecture augh of mul_577 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_578.vhd b/testsuite/gna/issue50/idct.d/mul_578.vhd
new file mode 100644
index 000000000..511b8af35
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_578.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_578 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_578;
+
+architecture augh of mul_578 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_579.vhd b/testsuite/gna/issue50/idct.d/mul_579.vhd
new file mode 100644
index 000000000..8eec1bacf
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_579.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_579 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end mul_579;
+
+architecture augh of mul_579 is
+
+	signal tmp_res : signed(47 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_589.vhd b/testsuite/gna/issue50/idct.d/mul_589.vhd
new file mode 100644
index 000000000..adbf23bb5
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_589.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_589 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end mul_589;
+
+architecture augh of mul_589 is
+
+	signal tmp_res : signed(47 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_592.vhd b/testsuite/gna/issue50/idct.d/mul_592.vhd
new file mode 100644
index 000000000..7edf63ecd
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_592.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_592 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_592;
+
+architecture augh of mul_592 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_594.vhd b/testsuite/gna/issue50/idct.d/mul_594.vhd
new file mode 100644
index 000000000..28161e278
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_594.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_594 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_594;
+
+architecture augh of mul_594 is
+
+	signal tmp_res : signed(46 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_595.vhd b/testsuite/gna/issue50/idct.d/mul_595.vhd
new file mode 100644
index 000000000..26e00ce84
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_595.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_595 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end mul_595;
+
+architecture augh of mul_595 is
+
+	signal tmp_res : signed(47 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(31 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/mul_605.vhd b/testsuite/gna/issue50/idct.d/mul_605.vhd
new file mode 100644
index 000000000..46a8124b9
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/mul_605.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity mul_605 is
+	port (
+		result : out std_logic_vector(30 downto 0);
+		in_a : in  std_logic_vector(30 downto 0);
+		in_b : in  std_logic_vector(14 downto 0)
+	);
+end mul_605;
+
+architecture augh of mul_605 is
+
+	signal tmp_res : signed(45 downto 0);
+
+begin
+
+	-- The actual multiplication
+	tmp_res <= signed(in_a) * signed(in_b);
+
+	-- Set the output
+	result <= std_logic_vector(tmp_res(30 downto 0));
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/muxb_162.vhd b/testsuite/gna/issue50/idct.d/muxb_162.vhd
new file mode 100644
index 000000000..638efae6a
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/muxb_162.vhd
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity muxb_162 is
+	port (
+		in_sel : in  std_logic;
+		out_data : out std_logic;
+		in_data0 : in  std_logic;
+		in_data1 : in  std_logic
+	);
+end muxb_162;
+
+architecture augh of muxb_162 is
+begin
+
+	out_data <= in_data0 when in_sel = '0' else in_data1;
+
+end architecture;
+
diff --git a/testsuite/gna/issue50/idct.d/muxb_201.vhd b/testsuite/gna/issue50/idct.d/muxb_201.vhd
new file mode 100644
index 000000000..106183a41
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/muxb_201.vhd
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity muxb_201 is
+	port (
+		in_sel : in  std_logic;
+		out_data : out std_logic;
+		in_data0 : in  std_logic;
+		in_data1 : in  std_logic
+	);
+end muxb_201;
+
+architecture augh of muxb_201 is
+begin
+
+	out_data <= in_data0 when in_sel = '0' else in_data1;
+
+end architecture;
+
diff --git a/testsuite/gna/issue50/idct.d/muxb_263.vhd b/testsuite/gna/issue50/idct.d/muxb_263.vhd
new file mode 100644
index 000000000..b5e735e12
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/muxb_263.vhd
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity muxb_263 is
+	port (
+		in_sel : in  std_logic;
+		out_data : out std_logic;
+		in_data0 : in  std_logic;
+		in_data1 : in  std_logic
+	);
+end muxb_263;
+
+architecture augh of muxb_263 is
+begin
+
+	out_data <= in_data0 when in_sel = '0' else in_data1;
+
+end architecture;
+
diff --git a/testsuite/gna/issue50/idct.d/muxb_265.vhd b/testsuite/gna/issue50/idct.d/muxb_265.vhd
new file mode 100644
index 000000000..17db58201
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/muxb_265.vhd
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity muxb_265 is
+	port (
+		in_sel : in  std_logic;
+		out_data : out std_logic;
+		in_data0 : in  std_logic;
+		in_data1 : in  std_logic
+	);
+end muxb_265;
+
+architecture augh of muxb_265 is
+begin
+
+	out_data <= in_data0 when in_sel = '0' else in_data1;
+
+end architecture;
+
diff --git a/testsuite/gna/issue50/idct.d/muxb_322.vhd b/testsuite/gna/issue50/idct.d/muxb_322.vhd
new file mode 100644
index 000000000..e54c9ffde
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/muxb_322.vhd
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity muxb_322 is
+	port (
+		in_sel : in  std_logic;
+		out_data : out std_logic;
+		in_data0 : in  std_logic;
+		in_data1 : in  std_logic
+	);
+end muxb_322;
+
+architecture augh of muxb_322 is
+begin
+
+	out_data <= in_data0 when in_sel = '0' else in_data1;
+
+end architecture;
+
diff --git a/testsuite/gna/issue50/idct.d/output_split0.vhd b/testsuite/gna/issue50/idct.d/output_split0.vhd
new file mode 100644
index 000000000..dc3627dcb
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/output_split0.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity output_split0 is
+	port (
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic_vector(2 downto 0);
+		ra0_data : out std_logic_vector(7 downto 0);
+		ra0_addr : in  std_logic_vector(2 downto 0);
+		wa0_en : in  std_logic;
+		clk : in  std_logic
+	);
+end output_split0;
+architecture augh of output_split0 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (others => (others => '0'));
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/output_split1.vhd b/testsuite/gna/issue50/idct.d/output_split1.vhd
new file mode 100644
index 000000000..65980992f
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/output_split1.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity output_split1 is
+	port (
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic_vector(2 downto 0);
+		ra0_data : out std_logic_vector(7 downto 0);
+		ra0_addr : in  std_logic_vector(2 downto 0);
+		wa0_en : in  std_logic;
+		clk : in  std_logic
+	);
+end output_split1;
+architecture augh of output_split1 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (others => (others => '0'));
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/output_split2.vhd b/testsuite/gna/issue50/idct.d/output_split2.vhd
new file mode 100644
index 000000000..89e8a1587
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/output_split2.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity output_split2 is
+	port (
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic_vector(2 downto 0);
+		ra0_data : out std_logic_vector(7 downto 0);
+		ra0_addr : in  std_logic_vector(2 downto 0);
+		wa0_en : in  std_logic;
+		clk : in  std_logic
+	);
+end output_split2;
+architecture augh of output_split2 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (others => (others => '0'));
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/output_split3.vhd b/testsuite/gna/issue50/idct.d/output_split3.vhd
new file mode 100644
index 000000000..301380934
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/output_split3.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity output_split3 is
+	port (
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic_vector(2 downto 0);
+		ra0_data : out std_logic_vector(7 downto 0);
+		ra0_addr : in  std_logic_vector(2 downto 0);
+		wa0_en : in  std_logic;
+		clk : in  std_logic
+	);
+end output_split3;
+architecture augh of output_split3 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (others => (others => '0'));
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/output_split4.vhd b/testsuite/gna/issue50/idct.d/output_split4.vhd
new file mode 100644
index 000000000..2e998cef6
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/output_split4.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity output_split4 is
+	port (
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic_vector(2 downto 0);
+		ra0_data : out std_logic_vector(7 downto 0);
+		ra0_addr : in  std_logic_vector(2 downto 0);
+		wa0_en : in  std_logic;
+		clk : in  std_logic
+	);
+end output_split4;
+architecture augh of output_split4 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (others => (others => '0'));
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/output_split5.vhd b/testsuite/gna/issue50/idct.d/output_split5.vhd
new file mode 100644
index 000000000..0a9cfabda
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/output_split5.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity output_split5 is
+	port (
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic_vector(2 downto 0);
+		ra0_data : out std_logic_vector(7 downto 0);
+		ra0_addr : in  std_logic_vector(2 downto 0);
+		wa0_en : in  std_logic;
+		clk : in  std_logic
+	);
+end output_split5;
+architecture augh of output_split5 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (others => (others => '0'));
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/output_split6.vhd b/testsuite/gna/issue50/idct.d/output_split6.vhd
new file mode 100644
index 000000000..888ea9cd2
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/output_split6.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity output_split6 is
+	port (
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic_vector(2 downto 0);
+		ra0_data : out std_logic_vector(7 downto 0);
+		ra0_addr : in  std_logic_vector(2 downto 0);
+		wa0_en : in  std_logic;
+		clk : in  std_logic
+	);
+end output_split6;
+architecture augh of output_split6 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (others => (others => '0'));
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/output_split7.vhd b/testsuite/gna/issue50/idct.d/output_split7.vhd
new file mode 100644
index 000000000..c70550219
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/output_split7.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity output_split7 is
+	port (
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic_vector(2 downto 0);
+		ra0_data : out std_logic_vector(7 downto 0);
+		ra0_addr : in  std_logic_vector(2 downto 0);
+		wa0_en : in  std_logic;
+		clk : in  std_logic
+	);
+end output_split7;
+architecture augh of output_split7 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (others => (others => '0'));
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/pkg_tb.vhd b/testsuite/gna/issue50/idct.d/pkg_tb.vhd
new file mode 100644
index 000000000..b770071a4
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/pkg_tb.vhd
@@ -0,0 +1,60 @@
+--test bench written by alban bourge @ tima
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package pkg_tb is
+
+	--fsm state types
+	type state_t is (Rst,Sig_start,Ack_data,Running,Waitfor,Cp_search,Cp_save,Idle,Rst_uut,Rest_ini0,Rest_ini1,Rest,Stop);
+	--context descriptor
+	subtype context_t is std_logic_vector(1 downto 0);
+	--argument width and type of fsm instruction
+	constant ARG_WIDTH : integer := 8;
+	subtype argument_t is unsigned(ARG_WIDTH - 1 downto 0);
+
+	type instruction is 
+		record
+			state       : state_t;
+			context_uut : context_t;
+			arg         : argument_t;
+		end record;
+
+	--reset instruction
+	constant instr_rst : instruction := (state => Rst, context_uut => (others =>'0'), arg => (others =>'0'));
+
+	--ram instruction
+	type ram_instruction is
+		record
+			sel     : std_logic;
+			we      : std_logic;
+			addr_up : std_logic;
+			addr_z  : std_logic;
+		end record;
+
+	constant ram_instr_z : ram_instruction := (sel => '0', we => '0', addr_up => '0', addr_z => '0');
+
+	--assert unit instruction
+	type assert_instruction is
+		record
+			en_feed  : std_logic;
+			en_check : std_logic;
+		end record;
+
+	constant assert_instr_z : assert_instruction := (en_feed => '0', en_check => '0');
+	
+	--size of instruction table defined by PC_SIZE i.e. width of program counter
+	constant PC_SIZE : integer := 5;
+	type table_behavior is array (0 to 2**PC_SIZE - 1) of instruction;
+
+	--constraint fixed by unit under test (augh dependant)
+	--##CONSTRAINTS_START##--
+	subtype stdin_vector is std_logic_vector(31 downto 0);
+	subtype stdout_vector is std_logic_vector(7 downto 0);
+	subtype cp_vector is std_logic_vector(63 downto 0);
+	--##CONSTRAINTS_END##--
+
+	--assert_uut vector number counter size
+	constant VEC_NO_SIZE : integer := 20;
+
+end pkg_tb;
diff --git a/testsuite/gna/issue50/idct.d/prog.vhd b/testsuite/gna/issue50/idct.d/prog.vhd
new file mode 100644
index 000000000..0bba1578d
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/prog.vhd
@@ -0,0 +1,70 @@
+--test bench written by Alban Bourge @ TIMA
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.pkg_tb.all;
+
+entity prog is
+	port(
+				clock      : in std_logic;
+				reset      : in std_logic;
+				step       : in std_logic;
+				instr_next : out instruction
+			);
+end prog;
+
+architecture rtl of prog is
+
+	signal instr_n : instruction := instr_rst;
+
+	--Table describing fsm behavior
+	constant fsm_behavior : table_behavior := (
+		--##PROGRAM_GOES_DOWN_HERE##--
+		0 => (state => Rst, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
+		1 => (state => Rst, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
+		2 => (state => Sig_start, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
+		3 => (state => Ack_data, context_uut => "01", arg => to_unsigned(64,ARG_WIDTH)),
+		4 => (state => Cp_search, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
+		5 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
+		6 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
+		7 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
+		8 => (state => Sig_start, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
+		9 => (state => Ack_data, context_uut => "10", arg => to_unsigned(64,ARG_WIDTH)),
+		10 => (state => Running, context_uut => "10", arg => to_unsigned(20,ARG_WIDTH)),
+		11 => (state => Cp_search, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
+		12 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
+		13 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
+		14 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
+		15 => (state => Rest_ini0, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
+		16 => (state => Waitfor, context_uut => "01", arg => to_unsigned(64,ARG_WIDTH)),
+		17 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
+		18 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
+		19 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
+		20 => (state => Rest_ini0, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
+		21 => (state => Waitfor, context_uut => "10", arg => to_unsigned(64,ARG_WIDTH)),
+		22 => (state => Stop, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
+		--##PROGRAM_GOES_OVER_HERE##--
+		others => instr_rst);
+
+	signal pc : unsigned(PC_SIZE - 1 downto 0) := (others => '0');
+
+begin
+
+	drive_state : process (reset,clock) is
+	begin
+		if reset = '1' then
+			instr_n <= instr_rst;
+			pc      <= (others => '0');
+		elsif rising_edge(clock) then
+			if (step = '1') then
+				pc <= pc + 1;
+			end if;
+			instr_n <= fsm_behavior(to_integer(pc));
+		end if;
+	end process drive_state;
+
+	--instr_next <= instr_n;
+	instr_next <= fsm_behavior(to_integer(pc));
+
+end rtl;
diff --git a/testsuite/gna/issue50/idct.d/sub_157.vhd b/testsuite/gna/issue50/idct.d/sub_157.vhd
new file mode 100644
index 000000000..60aa5474e
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_157.vhd
@@ -0,0 +1,64 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_157 is
+	port (
+		ge : out std_logic;
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0);
+		sign : in  std_logic
+	);
+end sub_157;
+
+architecture augh of sub_157 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+	-- Signals to generate the comparison outputs
+	signal msb_abr  : std_logic_vector(2 downto 0);
+	signal tmp_sign : std_logic;
+	signal tmp_eq   : std_logic;
+	signal tmp_le   : std_logic;
+	signal tmp_ge   : std_logic;
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+	-- Other comparison outputs
+
+	-- Temporary signals
+	msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32);
+	tmp_sign <= sign;
+	tmp_eq  <= '1' when in_a = in_b else '0';
+
+	tmp_le <=
+		tmp_eq when msb_abr = "000" or msb_abr = "110" else
+		'1' when msb_abr = "001" or msb_abr = "111" else
+		'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
+		'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
+		'0';
+
+	tmp_ge <=
+		'1' when msb_abr = "000" or msb_abr = "110" else
+		'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
+		'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
+		'0';
+
+	ge <= tmp_ge;
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_159.vhd b/testsuite/gna/issue50/idct.d/sub_159.vhd
new file mode 100644
index 000000000..fb69c2984
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_159.vhd
@@ -0,0 +1,64 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_159 is
+	port (
+		gt : out std_logic;
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0);
+		sign : in  std_logic
+	);
+end sub_159;
+
+architecture augh of sub_159 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+	-- Signals to generate the comparison outputs
+	signal msb_abr  : std_logic_vector(2 downto 0);
+	signal tmp_sign : std_logic;
+	signal tmp_eq   : std_logic;
+	signal tmp_le   : std_logic;
+	signal tmp_ge   : std_logic;
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+	-- Other comparison outputs
+
+	-- Temporary signals
+	msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32);
+	tmp_sign <= sign;
+	tmp_eq  <= '1' when in_a = in_b else '0';
+
+	tmp_le <=
+		tmp_eq when msb_abr = "000" or msb_abr = "110" else
+		'1' when msb_abr = "001" or msb_abr = "111" else
+		'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
+		'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
+		'0';
+
+	tmp_ge <=
+		'1' when msb_abr = "000" or msb_abr = "110" else
+		'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
+		'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
+		'0';
+
+	gt <= not(tmp_le);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_160.vhd b/testsuite/gna/issue50/idct.d/sub_160.vhd
new file mode 100644
index 000000000..33dfaecd3
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_160.vhd
@@ -0,0 +1,64 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_160 is
+	port (
+		le : out std_logic;
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0);
+		sign : in  std_logic
+	);
+end sub_160;
+
+architecture augh of sub_160 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+	-- Signals to generate the comparison outputs
+	signal msb_abr  : std_logic_vector(2 downto 0);
+	signal tmp_sign : std_logic;
+	signal tmp_eq   : std_logic;
+	signal tmp_le   : std_logic;
+	signal tmp_ge   : std_logic;
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+	-- Other comparison outputs
+
+	-- Temporary signals
+	msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32);
+	tmp_sign <= sign;
+	tmp_eq  <= '1' when in_a = in_b else '0';
+
+	tmp_le <=
+		tmp_eq when msb_abr = "000" or msb_abr = "110" else
+		'1' when msb_abr = "001" or msb_abr = "111" else
+		'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
+		'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
+		'0';
+
+	tmp_ge <=
+		'1' when msb_abr = "000" or msb_abr = "110" else
+		'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
+		'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
+		'0';
+
+	le <= tmp_le;
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_185.vhd b/testsuite/gna/issue50/idct.d/sub_185.vhd
new file mode 100644
index 000000000..f6f78be21
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_185.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_185 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_185;
+
+architecture augh of sub_185 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_186.vhd b/testsuite/gna/issue50/idct.d/sub_186.vhd
new file mode 100644
index 000000000..5178357fa
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_186.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_186 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_186;
+
+architecture augh of sub_186 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_187.vhd b/testsuite/gna/issue50/idct.d/sub_187.vhd
new file mode 100644
index 000000000..f38c25ec0
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_187.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_187 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_187;
+
+architecture augh of sub_187 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_188.vhd b/testsuite/gna/issue50/idct.d/sub_188.vhd
new file mode 100644
index 000000000..b72ee5f90
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_188.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_188 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_188;
+
+architecture augh of sub_188 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_197.vhd b/testsuite/gna/issue50/idct.d/sub_197.vhd
new file mode 100644
index 000000000..934ef4546
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_197.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_197 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_197;
+
+architecture augh of sub_197 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_200.vhd b/testsuite/gna/issue50/idct.d/sub_200.vhd
new file mode 100644
index 000000000..58eeaf53d
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_200.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_200 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_200;
+
+architecture augh of sub_200 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_207.vhd b/testsuite/gna/issue50/idct.d/sub_207.vhd
new file mode 100644
index 000000000..0bbb27861
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_207.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_207 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_207;
+
+architecture augh of sub_207 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_208.vhd b/testsuite/gna/issue50/idct.d/sub_208.vhd
new file mode 100644
index 000000000..04955c989
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_208.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_208 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_208;
+
+architecture augh of sub_208 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_209.vhd b/testsuite/gna/issue50/idct.d/sub_209.vhd
new file mode 100644
index 000000000..7506a9107
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_209.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_209 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_209;
+
+architecture augh of sub_209 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_213.vhd b/testsuite/gna/issue50/idct.d/sub_213.vhd
new file mode 100644
index 000000000..667b143b7
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_213.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_213 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_213;
+
+architecture augh of sub_213 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_214.vhd b/testsuite/gna/issue50/idct.d/sub_214.vhd
new file mode 100644
index 000000000..a0cc10e2e
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_214.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_214 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_214;
+
+architecture augh of sub_214 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_217.vhd b/testsuite/gna/issue50/idct.d/sub_217.vhd
new file mode 100644
index 000000000..46c08114f
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_217.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_217 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_217;
+
+architecture augh of sub_217 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_220.vhd b/testsuite/gna/issue50/idct.d/sub_220.vhd
new file mode 100644
index 000000000..59afe89d9
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_220.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_220 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_220;
+
+architecture augh of sub_220 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_227.vhd b/testsuite/gna/issue50/idct.d/sub_227.vhd
new file mode 100644
index 000000000..68eb64627
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_227.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_227 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_227;
+
+architecture augh of sub_227 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_243.vhd b/testsuite/gna/issue50/idct.d/sub_243.vhd
new file mode 100644
index 000000000..0082e0974
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_243.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_243 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_243;
+
+architecture augh of sub_243 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_262.vhd b/testsuite/gna/issue50/idct.d/sub_262.vhd
new file mode 100644
index 000000000..607edaf9a
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_262.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_262 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_262;
+
+architecture augh of sub_262 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_284.vhd b/testsuite/gna/issue50/idct.d/sub_284.vhd
new file mode 100644
index 000000000..5a438f2fa
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_284.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_284 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_284;
+
+architecture augh of sub_284 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_303.vhd b/testsuite/gna/issue50/idct.d/sub_303.vhd
new file mode 100644
index 000000000..493d36185
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_303.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_303 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_303;
+
+architecture augh of sub_303 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_332.vhd b/testsuite/gna/issue50/idct.d/sub_332.vhd
new file mode 100644
index 000000000..4b4f033c6
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_332.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_332 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_332;
+
+architecture augh of sub_332 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_337.vhd b/testsuite/gna/issue50/idct.d/sub_337.vhd
new file mode 100644
index 000000000..1e4d7d35e
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_337.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_337 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_337;
+
+architecture augh of sub_337 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_345.vhd b/testsuite/gna/issue50/idct.d/sub_345.vhd
new file mode 100644
index 000000000..9fe7ef2d0
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_345.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_345 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_345;
+
+architecture augh of sub_345 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_354.vhd b/testsuite/gna/issue50/idct.d/sub_354.vhd
new file mode 100644
index 000000000..afc78d181
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_354.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_354 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_354;
+
+architecture augh of sub_354 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_362.vhd b/testsuite/gna/issue50/idct.d/sub_362.vhd
new file mode 100644
index 000000000..cd1502ed5
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_362.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_362 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_362;
+
+architecture augh of sub_362 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_369.vhd b/testsuite/gna/issue50/idct.d/sub_369.vhd
new file mode 100644
index 000000000..43bb66168
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_369.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_369 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_369;
+
+architecture augh of sub_369 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_370.vhd b/testsuite/gna/issue50/idct.d/sub_370.vhd
new file mode 100644
index 000000000..fcebc0f43
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_370.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_370 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_370;
+
+architecture augh of sub_370 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_377.vhd b/testsuite/gna/issue50/idct.d/sub_377.vhd
new file mode 100644
index 000000000..8acb011b0
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_377.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_377 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_377;
+
+architecture augh of sub_377 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_391.vhd b/testsuite/gna/issue50/idct.d/sub_391.vhd
new file mode 100644
index 000000000..b2b1d18e8
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_391.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_391 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_391;
+
+architecture augh of sub_391 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_429.vhd b/testsuite/gna/issue50/idct.d/sub_429.vhd
new file mode 100644
index 000000000..edbf7c17c
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_429.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_429 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_429;
+
+architecture augh of sub_429 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_437.vhd b/testsuite/gna/issue50/idct.d/sub_437.vhd
new file mode 100644
index 000000000..3c549f2b0
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_437.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_437 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_437;
+
+architecture augh of sub_437 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_446.vhd b/testsuite/gna/issue50/idct.d/sub_446.vhd
new file mode 100644
index 000000000..4b34a5e1e
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_446.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_446 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_446;
+
+architecture augh of sub_446 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_449.vhd b/testsuite/gna/issue50/idct.d/sub_449.vhd
new file mode 100644
index 000000000..73bdc38e7
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_449.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_449 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_449;
+
+architecture augh of sub_449 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_461.vhd b/testsuite/gna/issue50/idct.d/sub_461.vhd
new file mode 100644
index 000000000..bce5accb7
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_461.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_461 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_461;
+
+architecture augh of sub_461 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_478.vhd b/testsuite/gna/issue50/idct.d/sub_478.vhd
new file mode 100644
index 000000000..6099d883e
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_478.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_478 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_478;
+
+architecture augh of sub_478 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_484.vhd b/testsuite/gna/issue50/idct.d/sub_484.vhd
new file mode 100644
index 000000000..a7578a19e
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_484.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_484 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_484;
+
+architecture augh of sub_484 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_488.vhd b/testsuite/gna/issue50/idct.d/sub_488.vhd
new file mode 100644
index 000000000..1f0abf831
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_488.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_488 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_488;
+
+architecture augh of sub_488 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_489.vhd b/testsuite/gna/issue50/idct.d/sub_489.vhd
new file mode 100644
index 000000000..bc1133c19
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_489.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_489 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_489;
+
+architecture augh of sub_489 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_496.vhd b/testsuite/gna/issue50/idct.d/sub_496.vhd
new file mode 100644
index 000000000..6cb195e9c
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_496.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_496 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_496;
+
+architecture augh of sub_496 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_503.vhd b/testsuite/gna/issue50/idct.d/sub_503.vhd
new file mode 100644
index 000000000..cd89e59ca
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_503.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_503 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_503;
+
+architecture augh of sub_503 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_517.vhd b/testsuite/gna/issue50/idct.d/sub_517.vhd
new file mode 100644
index 000000000..1f1714668
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_517.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_517 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_517;
+
+architecture augh of sub_517 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_521.vhd b/testsuite/gna/issue50/idct.d/sub_521.vhd
new file mode 100644
index 000000000..92603bd27
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_521.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_521 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_521;
+
+architecture augh of sub_521 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_528.vhd b/testsuite/gna/issue50/idct.d/sub_528.vhd
new file mode 100644
index 000000000..0f7fbafca
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_528.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_528 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_528;
+
+architecture augh of sub_528 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_544.vhd b/testsuite/gna/issue50/idct.d/sub_544.vhd
new file mode 100644
index 000000000..3583c6ce4
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_544.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_544 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_544;
+
+architecture augh of sub_544 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_553.vhd b/testsuite/gna/issue50/idct.d/sub_553.vhd
new file mode 100644
index 000000000..42c77a6fe
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_553.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_553 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_553;
+
+architecture augh of sub_553 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_562.vhd b/testsuite/gna/issue50/idct.d/sub_562.vhd
new file mode 100644
index 000000000..2ad25bba8
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_562.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_562 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_562;
+
+architecture augh of sub_562 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_563.vhd b/testsuite/gna/issue50/idct.d/sub_563.vhd
new file mode 100644
index 000000000..0a544649b
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_563.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_563 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_563;
+
+architecture augh of sub_563 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_567.vhd b/testsuite/gna/issue50/idct.d/sub_567.vhd
new file mode 100644
index 000000000..42d6ca9e0
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_567.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_567 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_567;
+
+architecture augh of sub_567 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_574.vhd b/testsuite/gna/issue50/idct.d/sub_574.vhd
new file mode 100644
index 000000000..52e0a08e8
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_574.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_574 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_574;
+
+architecture augh of sub_574 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_580.vhd b/testsuite/gna/issue50/idct.d/sub_580.vhd
new file mode 100644
index 000000000..ae77bbd23
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_580.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_580 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_580;
+
+architecture augh of sub_580 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_585.vhd b/testsuite/gna/issue50/idct.d/sub_585.vhd
new file mode 100644
index 000000000..6d809d9e8
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_585.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_585 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_585;
+
+architecture augh of sub_585 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_586.vhd b/testsuite/gna/issue50/idct.d/sub_586.vhd
new file mode 100644
index 000000000..245486a80
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_586.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_586 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_586;
+
+architecture augh of sub_586 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_593.vhd b/testsuite/gna/issue50/idct.d/sub_593.vhd
new file mode 100644
index 000000000..13d9b8296
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_593.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_593 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_593;
+
+architecture augh of sub_593 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_596.vhd b/testsuite/gna/issue50/idct.d/sub_596.vhd
new file mode 100644
index 000000000..5881cf2af
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_596.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_596 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_596;
+
+architecture augh of sub_596 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sub_599.vhd b/testsuite/gna/issue50/idct.d/sub_599.vhd
new file mode 100644
index 000000000..692205a61
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sub_599.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_599 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_599;
+
+architecture augh of sub_599 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/idct.d/sync_ram.vhd b/testsuite/gna/issue50/idct.d/sync_ram.vhd
new file mode 100644
index 000000000..83aecf543
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/sync_ram.vhd
@@ -0,0 +1,42 @@
+-- Simple generic RAM Model
+--
+-- +-----------------------------+
+-- |    Copyright 2008 DOULOS    |
+-- |   designer :  JK            |
+-- +-----------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity sync_ram is
+  port (
+    clock   : in  std_logic;
+    we      : in  std_logic;
+    address : in  std_logic_vector;
+    datain  : in  std_logic_vector;
+    dataout : out std_logic_vector
+  );
+end entity sync_ram;
+
+architecture rtl of sync_ram is
+
+   type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(datain'range);
+   signal ram : ram_type;
+   signal read_address : std_logic_vector(address'range);
+
+begin
+
+  ramproc: process(clock) is
+  begin
+    if rising_edge(clock) then
+      if we = '1' then
+        ram(to_integer(unsigned(address))) <= datain;
+      end if;
+      read_address <= address;
+    end if;
+  end process ramproc;
+
+  dataout <= ram(to_integer(unsigned(read_address)));
+
+end architecture rtl;
diff --git a/testsuite/gna/issue50/idct.d/tb.vhd b/testsuite/gna/issue50/idct.d/tb.vhd
new file mode 100644
index 000000000..94a534963
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/tb.vhd
@@ -0,0 +1,44 @@
+--test bench written by Alban Bourge @ TIMA
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.pkg_tb.all;
+
+entity tb is
+end tb;
+
+architecture behavior of tb is
+
+	signal clock      : std_logic  := '0';
+	signal clock_next : std_logic  := '0';
+	signal reset      : std_logic  := '0';
+	--TOP signals
+	signal n_error    : std_logic;
+	signal stopped    : std_logic;
+
+begin
+
+	test : entity work.cp3_test(rtl)
+	port map(
+						clock   => clock,
+						reset   => reset,
+						n_error => n_error,
+						stopped => stopped
+					);
+
+	--clock generator
+	clock <= clock_next after 10 ns;
+	clock_next <= not clock when stopped = '0' else '0';
+
+	reset_proc : process
+	begin
+		reset <= '1';
+		for i in 1 to 5 loop
+			wait until rising_edge(clock);
+		end loop;
+		reset <= '0';
+		wait;
+	end process reset_proc;
+
+end behavior;
diff --git a/testsuite/gna/issue50/idct.d/top.vhd b/testsuite/gna/issue50/idct.d/top.vhd
new file mode 100644
index 000000000..570e9eb7d
--- /dev/null
+++ b/testsuite/gna/issue50/idct.d/top.vhd
@@ -0,0 +1,6740 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity top is
+	port (
+		clock : in  std_logic;
+		reset : in  std_logic;
+		start : in  std_logic;
+		cp_ok : out std_logic;
+		cp_en : in  std_logic;
+		cp_rest : in  std_logic;
+		cp_din : in  std_logic_vector(63 downto 0);
+		cp_dout : out std_logic_vector(63 downto 0);
+		stdout_data : out std_logic_vector(7 downto 0);
+		stdout_rdy : out std_logic;
+		stdout_ack : in  std_logic;
+		stdin_data : in  std_logic_vector(31 downto 0);
+		stdin_rdy : out std_logic;
+		stdin_ack : in  std_logic
+	);
+end top;
+
+architecture augh of top is
+
+	-- Declaration of components
+
+	component output_split2 is
+		port (
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic_vector(2 downto 0);
+			ra0_data : out std_logic_vector(7 downto 0);
+			ra0_addr : in  std_logic_vector(2 downto 0);
+			wa0_en : in  std_logic;
+			clk : in  std_logic
+		);
+	end component;
+
+	component output_split3 is
+		port (
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic_vector(2 downto 0);
+			ra0_data : out std_logic_vector(7 downto 0);
+			ra0_addr : in  std_logic_vector(2 downto 0);
+			wa0_en : in  std_logic;
+			clk : in  std_logic
+		);
+	end component;
+
+	component sub_159 is
+		port (
+			gt : out std_logic;
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0);
+			sign : in  std_logic
+		);
+	end component;
+
+	component add_165 is
+		port (
+			result : out std_logic_vector(26 downto 0);
+			in_a : in  std_logic_vector(26 downto 0);
+			in_b : in  std_logic_vector(26 downto 0)
+		);
+	end component;
+
+	component output_split1 is
+		port (
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic_vector(2 downto 0);
+			ra0_data : out std_logic_vector(7 downto 0);
+			ra0_addr : in  std_logic_vector(2 downto 0);
+			wa0_en : in  std_logic;
+			clk : in  std_logic
+		);
+	end component;
+
+	component output_split0 is
+		port (
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic_vector(2 downto 0);
+			ra0_data : out std_logic_vector(7 downto 0);
+			ra0_addr : in  std_logic_vector(2 downto 0);
+			wa0_en : in  std_logic;
+			clk : in  std_logic
+		);
+	end component;
+
+	component add_172 is
+		port (
+			result : out std_logic_vector(19 downto 0);
+			in_a : in  std_logic_vector(19 downto 0);
+			in_b : in  std_logic_vector(19 downto 0)
+		);
+	end component;
+
+	component add_176 is
+		port (
+			result : out std_logic_vector(19 downto 0);
+			in_a : in  std_logic_vector(19 downto 0);
+			in_b : in  std_logic_vector(19 downto 0)
+		);
+	end component;
+
+	component add_181 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_187 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_189 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(13 downto 0)
+		);
+	end component;
+
+	component add_191 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(30 downto 0)
+		);
+	end component;
+
+	component mul_192 is
+		port (
+			result : out std_logic_vector(29 downto 0);
+			in_a : in  std_logic_vector(29 downto 0);
+			in_b : in  std_logic_vector(10 downto 0)
+		);
+	end component;
+
+	component mul_193 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_198 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_199 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(13 downto 0)
+		);
+	end component;
+
+	component sub_209 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_212 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_213 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_214 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_215 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component mul_216 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component sub_217 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_218 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_219 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component sub_220 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_223 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component sub_227 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_157 is
+		port (
+			ge : out std_logic;
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0);
+			sign : in  std_logic
+		);
+	end component;
+
+	component add_163 is
+		port (
+			result : out std_logic_vector(15 downto 0);
+			in_a : in  std_logic_vector(15 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component cmp_164 is
+		port (
+			ne : out std_logic;
+			in0 : in  std_logic_vector(15 downto 0);
+			in1 : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component add_170 is
+		port (
+			result : out std_logic_vector(19 downto 0);
+			in_a : in  std_logic_vector(19 downto 0);
+			in_b : in  std_logic_vector(19 downto 0)
+		);
+	end component;
+
+	component add_174 is
+		port (
+			result : out std_logic_vector(19 downto 0);
+			in_a : in  std_logic_vector(19 downto 0);
+			in_b : in  std_logic_vector(19 downto 0)
+		);
+	end component;
+
+	component add_180 is
+		port (
+			result : out std_logic_vector(19 downto 0);
+			in_a : in  std_logic_vector(19 downto 0);
+			in_b : in  std_logic_vector(19 downto 0)
+		);
+	end component;
+
+	component sub_186 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_190 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_196 is
+		port (
+			result : out std_logic_vector(29 downto 0);
+			in_a : in  std_logic_vector(29 downto 0);
+			in_b : in  std_logic_vector(10 downto 0)
+		);
+	end component;
+
+	component sub_200 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_206 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_210 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_171 is
+		port (
+			result : out std_logic_vector(26 downto 0);
+			in_a : in  std_logic_vector(26 downto 0);
+			in_b : in  std_logic_vector(26 downto 0)
+		);
+	end component;
+
+	component add_177 is
+		port (
+			result : out std_logic_vector(26 downto 0);
+			in_a : in  std_logic_vector(26 downto 0);
+			in_b : in  std_logic_vector(26 downto 0)
+		);
+	end component;
+
+	component add_179 is
+		port (
+			result : out std_logic_vector(26 downto 0);
+			in_a : in  std_logic_vector(26 downto 0);
+			in_b : in  std_logic_vector(26 downto 0)
+		);
+	end component;
+
+	component mul_195 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component sub_197 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_207 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_230 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component sub_185 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_211 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_226 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_235 is
+		port (
+			result : out std_logic_vector(26 downto 0);
+			in_a : in  std_logic_vector(26 downto 0);
+			in_b : in  std_logic_vector(26 downto 0)
+		);
+	end component;
+
+	component add_314 is
+		port (
+			result : out std_logic_vector(26 downto 0);
+			in_a : in  std_logic_vector(26 downto 0);
+			in_b : in  std_logic_vector(26 downto 0)
+		);
+	end component;
+
+	component sub_160 is
+		port (
+			le : out std_logic;
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0);
+			sign : in  std_logic
+		);
+	end component;
+
+	component add_173 is
+		port (
+			result : out std_logic_vector(26 downto 0);
+			in_a : in  std_logic_vector(26 downto 0);
+			in_b : in  std_logic_vector(26 downto 0)
+		);
+	end component;
+
+	component add_182 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_188 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_243 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_262 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component output_split4 is
+		port (
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic_vector(2 downto 0);
+			ra0_data : out std_logic_vector(7 downto 0);
+			ra0_addr : in  std_logic_vector(2 downto 0);
+			wa0_en : in  std_logic;
+			clk : in  std_logic
+		);
+	end component;
+
+	component output_split5 is
+		port (
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic_vector(2 downto 0);
+			ra0_data : out std_logic_vector(7 downto 0);
+			ra0_addr : in  std_logic_vector(2 downto 0);
+			wa0_en : in  std_logic;
+			clk : in  std_logic
+		);
+	end component;
+
+	component output_split6 is
+		port (
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic_vector(2 downto 0);
+			ra0_data : out std_logic_vector(7 downto 0);
+			ra0_addr : in  std_logic_vector(2 downto 0);
+			wa0_en : in  std_logic;
+			clk : in  std_logic
+		);
+	end component;
+
+	component output_split7 is
+		port (
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic_vector(2 downto 0);
+			ra0_data : out std_logic_vector(7 downto 0);
+			ra0_addr : in  std_logic_vector(2 downto 0);
+			wa0_en : in  std_logic;
+			clk : in  std_logic
+		);
+	end component;
+
+	component input_split0 is
+		port (
+			ra0_data : out std_logic_vector(31 downto 0);
+			ra0_addr : in  std_logic_vector(4 downto 0);
+			ra1_data : out std_logic_vector(31 downto 0);
+			ra1_addr : in  std_logic_vector(4 downto 0);
+			ra2_data : out std_logic_vector(31 downto 0);
+			ra2_addr : in  std_logic_vector(4 downto 0);
+			ra3_data : out std_logic_vector(31 downto 0);
+			ra3_addr : in  std_logic_vector(4 downto 0);
+			clk : in  std_logic;
+			wa2_data : in  std_logic_vector(31 downto 0);
+			wa2_addr : in  std_logic_vector(4 downto 0);
+			wa2_en : in  std_logic
+		);
+	end component;
+
+	component add_194 is
+		port (
+			result : out std_logic_vector(29 downto 0);
+			in_a : in  std_logic_vector(29 downto 0);
+			in_b : in  std_logic_vector(29 downto 0)
+		);
+	end component;
+
+	component add_205 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_254 is
+		port (
+			result : out std_logic_vector(26 downto 0);
+			in_a : in  std_logic_vector(26 downto 0);
+			in_b : in  std_logic_vector(26 downto 0)
+		);
+	end component;
+
+	component add_276 is
+		port (
+			result : out std_logic_vector(26 downto 0);
+			in_a : in  std_logic_vector(26 downto 0);
+			in_b : in  std_logic_vector(26 downto 0)
+		);
+	end component;
+
+	component sub_284 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component input_split1 is
+		port (
+			wa0_data : in  std_logic_vector(31 downto 0);
+			wa0_addr : in  std_logic_vector(4 downto 0);
+			ra0_data : out std_logic_vector(31 downto 0);
+			ra0_addr : in  std_logic_vector(4 downto 0);
+			wa0_en : in  std_logic;
+			ra1_data : out std_logic_vector(31 downto 0);
+			ra1_addr : in  std_logic_vector(4 downto 0);
+			ra2_data : out std_logic_vector(31 downto 0);
+			ra2_addr : in  std_logic_vector(4 downto 0);
+			ra3_data : out std_logic_vector(31 downto 0);
+			ra3_addr : in  std_logic_vector(4 downto 0);
+			clk : in  std_logic
+		);
+	end component;
+
+	component add_166 is
+		port (
+			result : out std_logic_vector(19 downto 0);
+			in_a : in  std_logic_vector(19 downto 0);
+			in_b : in  std_logic_vector(19 downto 0)
+		);
+	end component;
+
+	component add_168 is
+		port (
+			result : out std_logic_vector(19 downto 0);
+			in_a : in  std_logic_vector(19 downto 0);
+			in_b : in  std_logic_vector(19 downto 0)
+		);
+	end component;
+
+	component add_178 is
+		port (
+			result : out std_logic_vector(19 downto 0);
+			in_a : in  std_logic_vector(19 downto 0);
+			in_b : in  std_logic_vector(19 downto 0)
+		);
+	end component;
+
+	component add_183 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_332 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_341 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component mul_357 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_365 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_368 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component sub_369 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_370 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_377 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component cmp_398 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_400 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_404 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_406 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_408 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_410 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_412 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic;
+			in1 : in  std_logic
+		);
+	end component;
+
+	component sub_429 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_466 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_496 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_521 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_528 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component fsm_23 is
+		port (
+			clock : in  std_logic;
+			reset : in  std_logic;
+			in0 : in  std_logic;
+			out181 : out std_logic;
+			out182 : out std_logic;
+			out183 : out std_logic;
+			out184 : out std_logic;
+			out185 : out std_logic;
+			out8 : out std_logic;
+			out13 : out std_logic;
+			out14 : out std_logic;
+			out16 : out std_logic;
+			out18 : out std_logic;
+			out19 : out std_logic;
+			out20 : out std_logic;
+			out21 : out std_logic;
+			out22 : out std_logic;
+			in2 : in  std_logic;
+			out23 : out std_logic;
+			out24 : out std_logic;
+			out25 : out std_logic;
+			out26 : out std_logic;
+			out27 : out std_logic;
+			out28 : out std_logic;
+			out29 : out std_logic;
+			out30 : out std_logic;
+			out31 : out std_logic;
+			out33 : out std_logic;
+			out35 : out std_logic;
+			out36 : out std_logic;
+			out38 : out std_logic;
+			out40 : out std_logic;
+			out42 : out std_logic;
+			in3 : in  std_logic;
+			out44 : out std_logic;
+			out46 : out std_logic;
+			out48 : out std_logic;
+			out49 : out std_logic;
+			out50 : out std_logic;
+			out52 : out std_logic;
+			out54 : out std_logic;
+			out56 : out std_logic;
+			out57 : out std_logic;
+			out58 : out std_logic;
+			in4 : in  std_logic;
+			out60 : out std_logic;
+			in5 : in  std_logic;
+			out164 : out std_logic;
+			out165 : out std_logic;
+			out167 : out std_logic;
+			out168 : out std_logic;
+			out170 : out std_logic;
+			out171 : out std_logic;
+			out173 : out std_logic;
+			out174 : out std_logic;
+			out176 : out std_logic;
+			out178 : out std_logic;
+			out0 : out std_logic;
+			out1 : out std_logic;
+			out2 : out std_logic;
+			in1 : in  std_logic;
+			out4 : out std_logic;
+			out90 : out std_logic;
+			out91 : out std_logic;
+			out97 : out std_logic;
+			out99 : out std_logic;
+			out101 : out std_logic;
+			in6 : in  std_logic;
+			out103 : out std_logic;
+			out105 : out std_logic;
+			out106 : out std_logic;
+			out107 : out std_logic;
+			out108 : out std_logic;
+			out135 : out std_logic;
+			out136 : out std_logic;
+			out137 : out std_logic;
+			out138 : out std_logic;
+			in11 : in  std_logic;
+			out140 : out std_logic;
+			out141 : out std_logic;
+			out142 : out std_logic;
+			out143 : out std_logic;
+			out145 : out std_logic;
+			out146 : out std_logic;
+			out148 : out std_logic;
+			out150 : out std_logic;
+			out153 : out std_logic;
+			out154 : out std_logic;
+			out155 : out std_logic;
+			out156 : out std_logic;
+			out157 : out std_logic;
+			out158 : out std_logic;
+			out159 : out std_logic;
+			out160 : out std_logic;
+			out161 : out std_logic;
+			out162 : out std_logic;
+			out111 : out std_logic;
+			out112 : out std_logic;
+			out114 : out std_logic;
+			out116 : out std_logic;
+			out118 : out std_logic;
+			out120 : out std_logic;
+			out121 : out std_logic;
+			out122 : out std_logic;
+			out123 : out std_logic;
+			out124 : out std_logic;
+			out125 : out std_logic;
+			out126 : out std_logic;
+			in7 : in  std_logic;
+			out129 : out std_logic;
+			out130 : out std_logic;
+			in8 : in  std_logic;
+			out131 : out std_logic;
+			in9 : in  std_logic;
+			out132 : out std_logic;
+			out133 : out std_logic;
+			out134 : out std_logic;
+			in10 : in  std_logic;
+			out186 : out std_logic;
+			out187 : out std_logic;
+			out190 : out std_logic;
+			out195 : out std_logic;
+			out197 : out std_logic;
+			out198 : out std_logic;
+			out199 : out std_logic;
+			out200 : out std_logic;
+			out201 : out std_logic;
+			out203 : out std_logic;
+			out204 : out std_logic;
+			out206 : out std_logic;
+			out207 : out std_logic;
+			out209 : out std_logic;
+			out210 : out std_logic;
+			out212 : out std_logic;
+			out213 : out std_logic;
+			out215 : out std_logic;
+			out217 : out std_logic;
+			out220 : out std_logic;
+			out221 : out std_logic;
+			out222 : out std_logic;
+			out223 : out std_logic;
+			out224 : out std_logic;
+			out225 : out std_logic;
+			out226 : out std_logic;
+			out227 : out std_logic;
+			out228 : out std_logic;
+			out229 : out std_logic;
+			out231 : out std_logic;
+			out232 : out std_logic;
+			out234 : out std_logic;
+			out235 : out std_logic;
+			out237 : out std_logic;
+			out238 : out std_logic;
+			out240 : out std_logic;
+			out241 : out std_logic;
+			out243 : out std_logic;
+			out245 : out std_logic;
+			out248 : out std_logic;
+			out249 : out std_logic;
+			out250 : out std_logic;
+			out251 : out std_logic;
+			out252 : out std_logic;
+			out253 : out std_logic;
+			out254 : out std_logic;
+			out255 : out std_logic;
+			out256 : out std_logic;
+			out257 : out std_logic;
+			out259 : out std_logic;
+			out260 : out std_logic;
+			out262 : out std_logic;
+			out263 : out std_logic;
+			out265 : out std_logic;
+			out266 : out std_logic;
+			out268 : out std_logic;
+			out269 : out std_logic;
+			out271 : out std_logic;
+			out273 : out std_logic;
+			out276 : out std_logic;
+			out277 : out std_logic;
+			out278 : out std_logic;
+			out279 : out std_logic;
+			out280 : out std_logic;
+			out281 : out std_logic;
+			out282 : out std_logic;
+			out283 : out std_logic;
+			out284 : out std_logic;
+			out285 : out std_logic;
+			out286 : out std_logic;
+			out287 : out std_logic;
+			out288 : out std_logic;
+			out289 : out std_logic;
+			out290 : out std_logic;
+			out291 : out std_logic;
+			out292 : out std_logic;
+			out293 : out std_logic;
+			out294 : out std_logic;
+			out295 : out std_logic;
+			out296 : out std_logic;
+			out297 : out std_logic;
+			out298 : out std_logic;
+			out311 : out std_logic;
+			out312 : out std_logic;
+			out313 : out std_logic;
+			out314 : out std_logic;
+			out315 : out std_logic;
+			out316 : out std_logic;
+			out318 : out std_logic;
+			out321 : out std_logic;
+			out322 : out std_logic;
+			out323 : out std_logic;
+			out324 : out std_logic;
+			out325 : out std_logic;
+			out326 : out std_logic;
+			out327 : out std_logic;
+			out328 : out std_logic;
+			out329 : out std_logic;
+			out333 : out std_logic;
+			out341 : out std_logic;
+			out342 : out std_logic;
+			out343 : out std_logic;
+			out344 : out std_logic;
+			out345 : out std_logic;
+			out346 : out std_logic;
+			out349 : out std_logic;
+			out350 : out std_logic;
+			out351 : out std_logic;
+			out352 : out std_logic;
+			out353 : out std_logic;
+			out354 : out std_logic;
+			out355 : out std_logic;
+			out357 : out std_logic;
+			out361 : out std_logic;
+			out362 : out std_logic;
+			out363 : out std_logic;
+			out364 : out std_logic;
+			out366 : out std_logic;
+			out367 : out std_logic;
+			out371 : out std_logic;
+			out372 : out std_logic;
+			out373 : out std_logic;
+			out382 : out std_logic;
+			out383 : out std_logic;
+			out385 : out std_logic;
+			out393 : out std_logic;
+			out394 : out std_logic;
+			out395 : out std_logic;
+			out396 : out std_logic;
+			out398 : out std_logic;
+			out400 : out std_logic;
+			out401 : out std_logic;
+			out402 : out std_logic;
+			out404 : out std_logic;
+			out406 : out std_logic;
+			out407 : out std_logic;
+			out408 : out std_logic;
+			out409 : out std_logic;
+			out410 : out std_logic;
+			out411 : out std_logic;
+			out412 : out std_logic;
+			out413 : out std_logic;
+			out414 : out std_logic;
+			out416 : out std_logic;
+			out417 : out std_logic;
+			out418 : out std_logic;
+			out419 : out std_logic;
+			out422 : out std_logic;
+			out423 : out std_logic;
+			out425 : out std_logic;
+			out426 : out std_logic;
+			out428 : out std_logic;
+			out429 : out std_logic;
+			out430 : out std_logic;
+			out431 : out std_logic;
+			out433 : out std_logic;
+			out434 : out std_logic;
+			out435 : out std_logic;
+			out436 : out std_logic;
+			out437 : out std_logic;
+			out438 : out std_logic;
+			out440 : out std_logic;
+			out441 : out std_logic;
+			out443 : out std_logic;
+			out444 : out std_logic;
+			out445 : out std_logic;
+			out446 : out std_logic;
+			out447 : out std_logic;
+			out450 : out std_logic;
+			out451 : out std_logic;
+			out454 : out std_logic;
+			out455 : out std_logic;
+			out457 : out std_logic;
+			out458 : out std_logic;
+			out459 : out std_logic;
+			out460 : out std_logic;
+			out461 : out std_logic;
+			out462 : out std_logic;
+			out463 : out std_logic;
+			out464 : out std_logic;
+			out465 : out std_logic;
+			out466 : out std_logic;
+			out467 : out std_logic;
+			out468 : out std_logic;
+			out469 : out std_logic;
+			out472 : out std_logic;
+			out475 : out std_logic;
+			out481 : out std_logic;
+			out482 : out std_logic;
+			out483 : out std_logic;
+			out484 : out std_logic;
+			out487 : out std_logic;
+			out488 : out std_logic;
+			out491 : out std_logic;
+			out495 : out std_logic;
+			out496 : out std_logic;
+			out497 : out std_logic;
+			out498 : out std_logic;
+			out499 : out std_logic;
+			out500 : out std_logic;
+			out501 : out std_logic;
+			out512 : out std_logic;
+			out513 : out std_logic;
+			out517 : out std_logic;
+			out518 : out std_logic;
+			out519 : out std_logic;
+			out521 : out std_logic;
+			out522 : out std_logic;
+			out524 : out std_logic;
+			out525 : out std_logic;
+			out526 : out std_logic;
+			out527 : out std_logic;
+			out528 : out std_logic;
+			out531 : out std_logic;
+			out540 : out std_logic;
+			out542 : out std_logic;
+			out544 : out std_logic;
+			out545 : out std_logic;
+			out554 : out std_logic;
+			out555 : out std_logic;
+			out559 : out std_logic;
+			out560 : out std_logic;
+			out561 : out std_logic;
+			out562 : out std_logic;
+			out563 : out std_logic;
+			out566 : out std_logic;
+			out567 : out std_logic;
+			out570 : out std_logic;
+			out572 : out std_logic;
+			out575 : out std_logic;
+			out577 : out std_logic;
+			out578 : out std_logic;
+			out580 : out std_logic;
+			out581 : out std_logic
+		);
+	end component;
+
+	component add_167 is
+		port (
+			result : out std_logic_vector(26 downto 0);
+			in_a : in  std_logic_vector(26 downto 0);
+			in_b : in  std_logic_vector(26 downto 0)
+		);
+	end component;
+
+	component add_169 is
+		port (
+			result : out std_logic_vector(26 downto 0);
+			in_a : in  std_logic_vector(26 downto 0);
+			in_b : in  std_logic_vector(26 downto 0)
+		);
+	end component;
+
+	component add_175 is
+		port (
+			result : out std_logic_vector(26 downto 0);
+			in_a : in  std_logic_vector(26 downto 0);
+			in_b : in  std_logic_vector(26 downto 0)
+		);
+	end component;
+
+	component add_255 is
+		port (
+			result : out std_logic_vector(19 downto 0);
+			in_a : in  std_logic_vector(19 downto 0);
+			in_b : in  std_logic_vector(19 downto 0)
+		);
+	end component;
+
+	component sub_362 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_376 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component add_420 is
+		port (
+			result : out std_logic_vector(19 downto 0);
+			in_a : in  std_logic_vector(19 downto 0);
+			in_b : in  std_logic_vector(19 downto 0)
+		);
+	end component;
+
+	component sub_446 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_456 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_457 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component sub_461 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_517 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_560 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_565 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component mul_578 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component muxb_162 is
+		port (
+			in_sel : in  std_logic;
+			out_data : out std_logic;
+			in_data0 : in  std_logic;
+			in_data1 : in  std_logic
+		);
+	end component;
+
+	component add_184 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component muxb_201 is
+		port (
+			in_sel : in  std_logic;
+			out_data : out std_logic;
+			in_data0 : in  std_logic;
+			in_data1 : in  std_logic
+		);
+	end component;
+
+	component cmp_202 is
+		port (
+			ne : out std_logic;
+			in0 : in  std_logic_vector(15 downto 0);
+			in1 : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component cmp_203 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic;
+			in1 : in  std_logic
+		);
+	end component;
+
+	component cmp_204 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic;
+			in1 : in  std_logic
+		);
+	end component;
+
+	component sub_208 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_236 is
+		port (
+			result : out std_logic_vector(19 downto 0);
+			in_a : in  std_logic_vector(19 downto 0);
+			in_b : in  std_logic_vector(19 downto 0)
+		);
+	end component;
+
+	component muxb_263 is
+		port (
+			in_sel : in  std_logic;
+			out_data : out std_logic;
+			in_data0 : in  std_logic;
+			in_data1 : in  std_logic
+		);
+	end component;
+
+	component muxb_265 is
+		port (
+			in_sel : in  std_logic;
+			out_data : out std_logic;
+			in_data0 : in  std_logic;
+			in_data1 : in  std_logic
+		);
+	end component;
+
+	component add_277 is
+		port (
+			result : out std_logic_vector(19 downto 0);
+			in_a : in  std_logic_vector(19 downto 0);
+			in_b : in  std_logic_vector(19 downto 0)
+		);
+	end component;
+
+	component add_295 is
+		port (
+			result : out std_logic_vector(26 downto 0);
+			in_a : in  std_logic_vector(26 downto 0);
+			in_b : in  std_logic_vector(26 downto 0)
+		);
+	end component;
+
+	component add_296 is
+		port (
+			result : out std_logic_vector(19 downto 0);
+			in_a : in  std_logic_vector(19 downto 0);
+			in_b : in  std_logic_vector(19 downto 0)
+		);
+	end component;
+
+	component sub_303 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_315 is
+		port (
+			result : out std_logic_vector(19 downto 0);
+			in_a : in  std_logic_vector(19 downto 0);
+			in_b : in  std_logic_vector(19 downto 0)
+		);
+	end component;
+
+	component muxb_322 is
+		port (
+			in_sel : in  std_logic;
+			out_data : out std_logic;
+			in_data0 : in  std_logic;
+			in_data1 : in  std_logic
+		);
+	end component;
+
+	component add_323 is
+		port (
+			result : out std_logic_vector(15 downto 0);
+			in_a : in  std_logic_vector(15 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component cmp_324 is
+		port (
+			ne : out std_logic;
+			in0 : in  std_logic_vector(15 downto 0);
+			in1 : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component cmp_325 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic;
+			in1 : in  std_logic
+		);
+	end component;
+
+	component mul_328 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_331 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component sub_337 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_338 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_344 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component sub_345 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_350 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_353 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component sub_354 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_373 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component add_382 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_383 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component add_390 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_391 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component cmp_392 is
+		port (
+			ne : out std_logic;
+			in0 : in  std_logic_vector(31 downto 0);
+			in1 : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_393 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component cmp_396 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_402 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_411 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic;
+			in1 : in  std_logic
+		);
+	end component;
+
+	component cmp_413 is
+		port (
+			ne : out std_logic;
+			in0 : in  std_logic_vector(31 downto 0);
+			in1 : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_416 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component add_419 is
+		port (
+			result : out std_logic_vector(26 downto 0);
+			in_a : in  std_logic_vector(26 downto 0);
+			in_b : in  std_logic_vector(26 downto 0)
+		);
+	end component;
+
+	component add_430 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_437 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_442 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component mul_445 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_447 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_448 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component sub_449 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_460 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_469 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component add_474 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_477 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component sub_478 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_483 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_484 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_487 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_488 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_489 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_492 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_495 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component mul_499 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component mul_502 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component sub_503 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_508 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_511 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component add_516 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_520 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_524 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_527 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component mul_531 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_534 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component add_537 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_540 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component mul_543 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component sub_544 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_547 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component add_552 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_553 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_556 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_559 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_561 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component sub_562 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_563 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_564 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_566 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component sub_567 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_570 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_573 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component sub_574 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_577 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_579 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component sub_580 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_585 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_586 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_589 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component mul_592 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component sub_593 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component mul_594 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	component mul_595 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component sub_596 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_599 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_600 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component add_601 is
+		port (
+			result : out std_logic_vector(26 downto 0);
+			in_a : in  std_logic_vector(26 downto 0);
+			in_b : in  std_logic_vector(26 downto 0)
+		);
+	end component;
+
+	component add_602 is
+		port (
+			result : out std_logic_vector(19 downto 0);
+			in_a : in  std_logic_vector(19 downto 0);
+			in_b : in  std_logic_vector(19 downto 0)
+		);
+	end component;
+
+	component mul_605 is
+		port (
+			result : out std_logic_vector(30 downto 0);
+			in_a : in  std_logic_vector(30 downto 0);
+			in_b : in  std_logic_vector(14 downto 0)
+		);
+	end component;
+
+	-- Declaration of signals
+
+	signal sig_clock : std_logic;
+	signal sig_reset : std_logic;
+	signal augh_test_9 : std_logic;
+	signal augh_test_11 : std_logic;
+	signal sig_start : std_logic;
+	signal test_cp_0_16 : std_logic;
+	signal test_cp_1_17 : std_logic;
+	signal memextrct_loop_sig_21 : std_logic;
+	signal psc_loop_sig_20 : std_logic;
+	signal memextrct_loop_sig_22 : std_logic;
+	signal sig_606 : std_logic_vector(30 downto 0);
+	signal sig_607 : std_logic_vector(19 downto 0);
+	signal sig_608 : std_logic_vector(26 downto 0);
+	signal sig_609 : std_logic_vector(31 downto 0);
+	signal sig_610 : std_logic_vector(31 downto 0);
+	signal sig_611 : std_logic_vector(31 downto 0);
+	signal sig_612 : std_logic_vector(31 downto 0);
+	signal sig_613 : std_logic_vector(31 downto 0);
+	signal sig_614 : std_logic_vector(31 downto 0);
+	signal sig_615 : std_logic_vector(31 downto 0);
+	signal sig_616 : std_logic_vector(31 downto 0);
+	signal sig_617 : std_logic_vector(31 downto 0);
+	signal sig_618 : std_logic_vector(31 downto 0);
+	signal sig_619 : std_logic_vector(31 downto 0);
+	signal sig_620 : std_logic_vector(31 downto 0);
+	signal sig_621 : std_logic_vector(30 downto 0);
+	signal sig_622 : std_logic_vector(31 downto 0);
+	signal sig_623 : std_logic_vector(30 downto 0);
+	signal sig_624 : std_logic_vector(31 downto 0);
+	signal sig_625 : std_logic_vector(31 downto 0);
+	signal sig_626 : std_logic_vector(31 downto 0);
+	signal sig_627 : std_logic_vector(31 downto 0);
+	signal sig_628 : std_logic_vector(31 downto 0);
+	signal sig_629 : std_logic_vector(31 downto 0);
+	signal sig_630 : std_logic_vector(31 downto 0);
+	signal sig_631 : std_logic_vector(30 downto 0);
+	signal sig_632 : std_logic_vector(30 downto 0);
+	signal sig_633 : std_logic_vector(31 downto 0);
+	signal sig_634 : std_logic_vector(31 downto 0);
+	signal sig_635 : std_logic_vector(30 downto 0);
+	signal sig_636 : std_logic_vector(31 downto 0);
+	signal sig_637 : std_logic_vector(31 downto 0);
+	signal sig_638 : std_logic_vector(31 downto 0);
+	signal sig_639 : std_logic_vector(31 downto 0);
+	signal sig_640 : std_logic_vector(30 downto 0);
+	signal sig_641 : std_logic_vector(30 downto 0);
+	signal sig_642 : std_logic_vector(31 downto 0);
+	signal sig_643 : std_logic_vector(31 downto 0);
+	signal sig_644 : std_logic_vector(30 downto 0);
+	signal sig_645 : std_logic_vector(31 downto 0);
+	signal sig_646 : std_logic_vector(30 downto 0);
+	signal sig_647 : std_logic_vector(31 downto 0);
+	signal sig_648 : std_logic_vector(31 downto 0);
+	signal sig_649 : std_logic_vector(31 downto 0);
+	signal sig_650 : std_logic_vector(31 downto 0);
+	signal sig_651 : std_logic_vector(31 downto 0);
+	signal sig_652 : std_logic_vector(31 downto 0);
+	signal sig_653 : std_logic_vector(31 downto 0);
+	signal sig_654 : std_logic_vector(31 downto 0);
+	signal sig_655 : std_logic_vector(31 downto 0);
+	signal sig_656 : std_logic_vector(31 downto 0);
+	signal sig_657 : std_logic_vector(31 downto 0);
+	signal sig_658 : std_logic_vector(31 downto 0);
+	signal sig_659 : std_logic_vector(30 downto 0);
+	signal sig_660 : std_logic_vector(31 downto 0);
+	signal sig_661 : std_logic_vector(30 downto 0);
+	signal sig_662 : std_logic_vector(31 downto 0);
+	signal sig_663 : std_logic_vector(31 downto 0);
+	signal sig_664 : std_logic_vector(31 downto 0);
+	signal sig_665 : std_logic_vector(31 downto 0);
+	signal sig_666 : std_logic_vector(31 downto 0);
+	signal sig_667 : std_logic_vector(31 downto 0);
+	signal sig_668 : std_logic_vector(31 downto 0);
+	signal sig_669 : std_logic_vector(31 downto 0);
+	signal sig_670 : std_logic_vector(26 downto 0);
+	signal sig_671 : std_logic_vector(30 downto 0);
+	signal sig_672 : std_logic;
+	signal sig_673 : std_logic;
+	signal sig_674 : std_logic;
+	signal sig_675 : std_logic_vector(31 downto 0);
+	signal sig_676 : std_logic_vector(31 downto 0);
+	signal sig_677 : std_logic_vector(31 downto 0);
+	signal sig_678 : std_logic_vector(30 downto 0);
+	signal sig_679 : std_logic_vector(31 downto 0);
+	signal sig_680 : std_logic_vector(31 downto 0);
+	signal sig_681 : std_logic_vector(31 downto 0);
+	signal sig_682 : std_logic_vector(30 downto 0);
+	signal sig_683 : std_logic_vector(31 downto 0);
+	signal sig_684 : std_logic_vector(31 downto 0);
+	signal sig_685 : std_logic_vector(31 downto 0);
+	signal sig_686 : std_logic_vector(31 downto 0);
+	signal sig_687 : std_logic_vector(31 downto 0);
+	signal sig_688 : std_logic_vector(31 downto 0);
+	signal sig_689 : std_logic_vector(31 downto 0);
+	signal sig_690 : std_logic;
+	signal sig_691 : std_logic_vector(15 downto 0);
+	signal sig_692 : std_logic;
+	signal sig_693 : std_logic_vector(19 downto 0);
+	signal sig_694 : std_logic_vector(31 downto 0);
+	signal sig_695 : std_logic_vector(19 downto 0);
+	signal sig_696 : std_logic_vector(26 downto 0);
+	signal sig_697 : std_logic_vector(19 downto 0);
+	signal sig_698 : std_logic;
+	signal sig_699 : std_logic;
+	signal sig_700 : std_logic_vector(19 downto 0);
+	signal sig_701 : std_logic_vector(31 downto 0);
+	signal sig_702 : std_logic;
+	signal sig_703 : std_logic;
+	signal sig_704 : std_logic_vector(31 downto 0);
+	signal sig_705 : std_logic;
+	signal sig_706 : std_logic_vector(31 downto 0);
+	signal sig_707 : std_logic_vector(31 downto 0);
+	signal sig_708 : std_logic_vector(31 downto 0);
+	signal sig_709 : std_logic_vector(31 downto 0);
+	signal sig_710 : std_logic_vector(31 downto 0);
+	signal sig_711 : std_logic_vector(31 downto 0);
+	signal sig_712 : std_logic_vector(30 downto 0);
+	signal sig_713 : std_logic_vector(31 downto 0);
+	signal sig_714 : std_logic_vector(19 downto 0);
+	signal sig_715 : std_logic_vector(31 downto 0);
+	signal sig_716 : std_logic_vector(31 downto 0);
+	signal sig_717 : std_logic_vector(19 downto 0);
+	signal sig_718 : std_logic_vector(26 downto 0);
+	signal sig_719 : std_logic_vector(26 downto 0);
+	signal sig_720 : std_logic_vector(26 downto 0);
+	signal sig_721 : std_logic;
+	signal sig_722 : std_logic;
+	signal sig_723 : std_logic;
+	signal sig_724 : std_logic;
+	signal sig_725 : std_logic;
+	signal sig_726 : std_logic;
+	signal sig_727 : std_logic;
+	signal sig_728 : std_logic;
+	signal sig_729 : std_logic;
+	signal sig_730 : std_logic;
+	signal sig_731 : std_logic;
+	signal sig_732 : std_logic;
+	signal sig_733 : std_logic;
+	signal sig_734 : std_logic;
+	signal sig_735 : std_logic;
+	signal sig_736 : std_logic;
+	signal sig_737 : std_logic;
+	signal sig_738 : std_logic;
+	signal sig_739 : std_logic;
+	signal sig_740 : std_logic;
+	signal sig_741 : std_logic;
+	signal sig_742 : std_logic;
+	signal sig_743 : std_logic;
+	signal sig_744 : std_logic;
+	signal sig_745 : std_logic;
+	signal sig_746 : std_logic;
+	signal sig_747 : std_logic;
+	signal sig_748 : std_logic;
+	signal sig_749 : std_logic;
+	signal sig_750 : std_logic;
+	signal sig_751 : std_logic;
+	signal sig_752 : std_logic;
+	signal sig_753 : std_logic;
+	signal sig_754 : std_logic;
+	signal sig_755 : std_logic;
+	signal sig_756 : std_logic;
+	signal sig_757 : std_logic;
+	signal sig_758 : std_logic;
+	signal sig_759 : std_logic;
+	signal sig_760 : std_logic;
+	signal sig_761 : std_logic;
+	signal sig_762 : std_logic;
+	signal sig_763 : std_logic;
+	signal sig_764 : std_logic;
+	signal sig_765 : std_logic;
+	signal sig_766 : std_logic;
+	signal sig_767 : std_logic;
+	signal sig_768 : std_logic;
+	signal sig_769 : std_logic;
+	signal sig_770 : std_logic;
+	signal sig_771 : std_logic;
+	signal sig_772 : std_logic;
+	signal sig_773 : std_logic;
+	signal sig_774 : std_logic;
+	signal sig_775 : std_logic;
+	signal sig_776 : std_logic;
+	signal sig_777 : std_logic;
+	signal sig_778 : std_logic;
+	signal sig_779 : std_logic;
+	signal sig_780 : std_logic;
+	signal sig_781 : std_logic;
+	signal sig_782 : std_logic;
+	signal sig_783 : std_logic;
+	signal sig_784 : std_logic;
+	signal sig_785 : std_logic;
+	signal sig_786 : std_logic;
+	signal sig_787 : std_logic;
+	signal sig_788 : std_logic;
+	signal sig_789 : std_logic;
+	signal sig_790 : std_logic;
+	signal sig_791 : std_logic;
+	signal sig_792 : std_logic;
+	signal sig_793 : std_logic;
+	signal sig_794 : std_logic;
+	signal sig_795 : std_logic;
+	signal sig_796 : std_logic;
+	signal sig_797 : std_logic;
+	signal sig_798 : std_logic;
+	signal sig_799 : std_logic;
+	signal sig_800 : std_logic;
+	signal sig_801 : std_logic;
+	signal sig_802 : std_logic;
+	signal sig_803 : std_logic;
+	signal sig_804 : std_logic;
+	signal sig_805 : std_logic;
+	signal sig_806 : std_logic;
+	signal sig_807 : std_logic;
+	signal sig_808 : std_logic;
+	signal sig_809 : std_logic;
+	signal sig_810 : std_logic;
+	signal sig_811 : std_logic;
+	signal sig_812 : std_logic;
+	signal sig_813 : std_logic;
+	signal sig_814 : std_logic;
+	signal sig_815 : std_logic;
+	signal sig_816 : std_logic;
+	signal sig_817 : std_logic;
+	signal sig_818 : std_logic;
+	signal sig_819 : std_logic;
+	signal sig_820 : std_logic;
+	signal sig_821 : std_logic;
+	signal sig_822 : std_logic;
+	signal sig_823 : std_logic;
+	signal sig_824 : std_logic;
+	signal sig_825 : std_logic;
+	signal sig_826 : std_logic;
+	signal sig_827 : std_logic;
+	signal sig_828 : std_logic;
+	signal sig_829 : std_logic;
+	signal sig_830 : std_logic;
+	signal sig_831 : std_logic;
+	signal sig_832 : std_logic;
+	signal sig_833 : std_logic;
+	signal sig_834 : std_logic;
+	signal sig_835 : std_logic;
+	signal sig_836 : std_logic;
+	signal sig_837 : std_logic;
+	signal sig_838 : std_logic;
+	signal sig_839 : std_logic;
+	signal sig_840 : std_logic;
+	signal sig_841 : std_logic;
+	signal sig_842 : std_logic;
+	signal sig_843 : std_logic;
+	signal sig_844 : std_logic;
+	signal sig_845 : std_logic;
+	signal sig_846 : std_logic;
+	signal sig_847 : std_logic;
+	signal sig_848 : std_logic;
+	signal sig_849 : std_logic;
+	signal sig_850 : std_logic;
+	signal sig_851 : std_logic;
+	signal sig_852 : std_logic;
+	signal sig_853 : std_logic;
+	signal sig_854 : std_logic;
+	signal sig_855 : std_logic;
+	signal sig_856 : std_logic;
+	signal sig_857 : std_logic;
+	signal sig_858 : std_logic;
+	signal sig_859 : std_logic;
+	signal sig_860 : std_logic;
+	signal sig_861 : std_logic;
+	signal sig_862 : std_logic;
+	signal sig_863 : std_logic;
+	signal sig_864 : std_logic;
+	signal sig_865 : std_logic;
+	signal sig_866 : std_logic;
+	signal sig_867 : std_logic;
+	signal sig_868 : std_logic;
+	signal sig_869 : std_logic;
+	signal sig_870 : std_logic;
+	signal sig_871 : std_logic;
+	signal sig_872 : std_logic;
+	signal sig_873 : std_logic;
+	signal sig_874 : std_logic;
+	signal sig_875 : std_logic;
+	signal sig_876 : std_logic;
+	signal sig_877 : std_logic;
+	signal sig_878 : std_logic;
+	signal sig_879 : std_logic;
+	signal sig_880 : std_logic;
+	signal sig_881 : std_logic;
+	signal sig_882 : std_logic;
+	signal sig_883 : std_logic;
+	signal sig_884 : std_logic;
+	signal sig_885 : std_logic;
+	signal sig_886 : std_logic;
+	signal sig_887 : std_logic;
+	signal sig_888 : std_logic;
+	signal sig_889 : std_logic;
+	signal sig_890 : std_logic;
+	signal sig_891 : std_logic;
+	signal sig_892 : std_logic;
+	signal sig_893 : std_logic;
+	signal sig_894 : std_logic;
+	signal sig_895 : std_logic;
+	signal sig_896 : std_logic;
+	signal sig_897 : std_logic;
+	signal sig_898 : std_logic;
+	signal sig_899 : std_logic;
+	signal sig_900 : std_logic;
+	signal sig_901 : std_logic;
+	signal sig_902 : std_logic;
+	signal sig_903 : std_logic;
+	signal sig_904 : std_logic;
+	signal sig_905 : std_logic;
+	signal sig_906 : std_logic;
+	signal sig_907 : std_logic;
+	signal sig_908 : std_logic;
+	signal sig_909 : std_logic;
+	signal sig_910 : std_logic;
+	signal sig_911 : std_logic;
+	signal sig_912 : std_logic;
+	signal sig_913 : std_logic;
+	signal sig_914 : std_logic;
+	signal sig_915 : std_logic;
+	signal sig_916 : std_logic;
+	signal sig_917 : std_logic;
+	signal sig_918 : std_logic;
+	signal sig_919 : std_logic;
+	signal sig_920 : std_logic;
+	signal sig_921 : std_logic;
+	signal sig_922 : std_logic;
+	signal sig_923 : std_logic;
+	signal sig_924 : std_logic;
+	signal sig_925 : std_logic;
+	signal sig_926 : std_logic;
+	signal sig_927 : std_logic;
+	signal sig_928 : std_logic;
+	signal sig_929 : std_logic;
+	signal sig_930 : std_logic;
+	signal sig_931 : std_logic;
+	signal sig_932 : std_logic;
+	signal sig_933 : std_logic;
+	signal sig_934 : std_logic;
+	signal sig_935 : std_logic;
+	signal sig_936 : std_logic;
+	signal sig_937 : std_logic;
+	signal sig_938 : std_logic;
+	signal sig_939 : std_logic;
+	signal sig_940 : std_logic;
+	signal sig_941 : std_logic;
+	signal sig_942 : std_logic;
+	signal sig_943 : std_logic;
+	signal sig_944 : std_logic;
+	signal sig_945 : std_logic;
+	signal sig_946 : std_logic;
+	signal sig_947 : std_logic;
+	signal sig_948 : std_logic;
+	signal sig_949 : std_logic;
+	signal sig_950 : std_logic;
+	signal sig_951 : std_logic;
+	signal sig_952 : std_logic;
+	signal sig_953 : std_logic;
+	signal sig_954 : std_logic;
+	signal sig_955 : std_logic;
+	signal sig_956 : std_logic;
+	signal sig_957 : std_logic;
+	signal sig_958 : std_logic;
+	signal sig_959 : std_logic;
+	signal sig_960 : std_logic;
+	signal sig_961 : std_logic;
+	signal sig_962 : std_logic;
+	signal sig_963 : std_logic;
+	signal sig_964 : std_logic;
+	signal sig_965 : std_logic;
+	signal sig_966 : std_logic;
+	signal sig_967 : std_logic;
+	signal sig_968 : std_logic;
+	signal sig_969 : std_logic;
+	signal sig_970 : std_logic;
+	signal sig_971 : std_logic;
+	signal sig_972 : std_logic;
+	signal sig_973 : std_logic;
+	signal sig_974 : std_logic;
+	signal sig_975 : std_logic;
+	signal sig_976 : std_logic;
+	signal sig_977 : std_logic;
+	signal sig_978 : std_logic;
+	signal sig_979 : std_logic;
+	signal sig_980 : std_logic;
+	signal sig_981 : std_logic;
+	signal sig_982 : std_logic;
+	signal sig_983 : std_logic;
+	signal sig_984 : std_logic;
+	signal sig_985 : std_logic;
+	signal sig_986 : std_logic;
+	signal sig_987 : std_logic;
+	signal sig_988 : std_logic;
+	signal sig_989 : std_logic;
+	signal sig_990 : std_logic;
+	signal sig_991 : std_logic;
+	signal sig_992 : std_logic;
+	signal sig_993 : std_logic;
+	signal sig_994 : std_logic;
+	signal sig_995 : std_logic;
+	signal sig_996 : std_logic;
+	signal sig_997 : std_logic;
+	signal sig_998 : std_logic;
+	signal sig_999 : std_logic;
+	signal sig_1000 : std_logic;
+	signal sig_1001 : std_logic;
+	signal sig_1002 : std_logic;
+	signal sig_1003 : std_logic;
+	signal sig_1004 : std_logic;
+	signal sig_1005 : std_logic;
+	signal sig_1006 : std_logic;
+	signal sig_1007 : std_logic;
+	signal sig_1008 : std_logic;
+	signal sig_1009 : std_logic;
+	signal sig_1010 : std_logic;
+	signal sig_1011 : std_logic;
+	signal sig_1012 : std_logic;
+	signal sig_1013 : std_logic;
+	signal sig_1014 : std_logic;
+	signal sig_1015 : std_logic;
+	signal sig_1016 : std_logic;
+	signal sig_1017 : std_logic;
+	signal sig_1018 : std_logic;
+	signal sig_1019 : std_logic;
+	signal sig_1020 : std_logic;
+	signal sig_1021 : std_logic;
+	signal sig_1022 : std_logic;
+	signal sig_1023 : std_logic;
+	signal sig_1024 : std_logic;
+	signal sig_1025 : std_logic;
+	signal sig_1026 : std_logic;
+	signal sig_1027 : std_logic;
+	signal sig_1028 : std_logic;
+	signal sig_1029 : std_logic;
+	signal sig_1030 : std_logic;
+	signal sig_1031 : std_logic;
+	signal sig_1032 : std_logic;
+	signal sig_1033 : std_logic;
+	signal sig_1034 : std_logic;
+	signal sig_1035 : std_logic;
+	signal sig_1036 : std_logic;
+	signal sig_1037 : std_logic;
+	signal sig_1038 : std_logic;
+	signal sig_1039 : std_logic;
+	signal sig_1040 : std_logic;
+	signal sig_1041 : std_logic;
+	signal sig_1042 : std_logic;
+	signal sig_1043 : std_logic;
+	signal sig_1044 : std_logic;
+	signal sig_1045 : std_logic;
+	signal sig_1046 : std_logic;
+	signal sig_1047 : std_logic;
+	signal sig_1048 : std_logic;
+	signal sig_1049 : std_logic;
+	signal sig_1050 : std_logic;
+	signal sig_1051 : std_logic;
+	signal sig_1052 : std_logic;
+	signal sig_1053 : std_logic;
+	signal sig_1054 : std_logic;
+	signal sig_1055 : std_logic;
+	signal sig_1056 : std_logic;
+	signal sig_1057 : std_logic;
+	signal sig_1058 : std_logic;
+	signal sig_1059 : std_logic_vector(31 downto 0);
+	signal sig_1060 : std_logic_vector(31 downto 0);
+	signal sig_1061 : std_logic_vector(31 downto 0);
+	signal sig_1062 : std_logic_vector(31 downto 0);
+	signal sig_1063 : std_logic_vector(31 downto 0);
+	signal sig_1064 : std_logic;
+	signal sig_1065 : std_logic;
+	signal sig_1066 : std_logic;
+	signal sig_1067 : std_logic;
+	signal sig_1068 : std_logic;
+	signal sig_1069 : std_logic;
+	signal sig_1070 : std_logic;
+	signal sig_1071 : std_logic_vector(31 downto 0);
+	signal sig_1072 : std_logic_vector(31 downto 0);
+	signal sig_1073 : std_logic_vector(31 downto 0);
+	signal sig_1074 : std_logic_vector(31 downto 0);
+	signal sig_1075 : std_logic_vector(31 downto 0);
+	signal sig_1076 : std_logic_vector(30 downto 0);
+	signal sig_1077 : std_logic_vector(31 downto 0);
+	signal sig_1078 : std_logic_vector(31 downto 0);
+	signal sig_1079 : std_logic_vector(31 downto 0);
+	signal sig_1080 : std_logic_vector(19 downto 0);
+	signal sig_1081 : std_logic_vector(19 downto 0);
+	signal sig_1082 : std_logic_vector(19 downto 0);
+	signal sig_1083 : std_logic_vector(31 downto 0);
+	signal sig_1084 : std_logic_vector(31 downto 0);
+	signal sig_1085 : std_logic_vector(31 downto 0);
+	signal sig_1086 : std_logic_vector(31 downto 0);
+	signal sig_1087 : std_logic_vector(31 downto 0);
+	signal sig_1088 : std_logic_vector(26 downto 0);
+	signal sig_1089 : std_logic_vector(26 downto 0);
+	signal sig_1090 : std_logic_vector(31 downto 0);
+	signal sig_1091 : std_logic_vector(29 downto 0);
+	signal sig_1092 : std_logic_vector(31 downto 0);
+	signal sig_1093 : std_logic_vector(31 downto 0);
+	signal sig_1094 : std_logic_vector(31 downto 0);
+	signal sig_1095 : std_logic_vector(31 downto 0);
+	signal sig_1096 : std_logic_vector(7 downto 0);
+	signal sig_1097 : std_logic_vector(7 downto 0);
+	signal sig_1098 : std_logic_vector(7 downto 0);
+	signal sig_1099 : std_logic_vector(7 downto 0);
+	signal sig_1100 : std_logic_vector(31 downto 0);
+	signal sig_1101 : std_logic_vector(31 downto 0);
+	signal sig_1102 : std_logic_vector(31 downto 0);
+	signal sig_1103 : std_logic_vector(31 downto 0);
+	signal sig_1104 : std_logic_vector(26 downto 0);
+	signal sig_1105 : std_logic_vector(31 downto 0);
+	signal sig_1106 : std_logic;
+	signal sig_1107 : std_logic_vector(26 downto 0);
+	signal sig_1108 : std_logic_vector(26 downto 0);
+	signal sig_1109 : std_logic_vector(31 downto 0);
+	signal sig_1110 : std_logic_vector(31 downto 0);
+	signal sig_1111 : std_logic_vector(31 downto 0);
+	signal sig_1112 : std_logic_vector(30 downto 0);
+	signal sig_1113 : std_logic_vector(31 downto 0);
+	signal sig_1114 : std_logic_vector(31 downto 0);
+	signal sig_1115 : std_logic_vector(31 downto 0);
+	signal sig_1116 : std_logic_vector(26 downto 0);
+	signal sig_1117 : std_logic_vector(26 downto 0);
+	signal sig_1118 : std_logic_vector(26 downto 0);
+	signal sig_1119 : std_logic_vector(31 downto 0);
+	signal sig_1120 : std_logic_vector(31 downto 0);
+	signal sig_1121 : std_logic_vector(31 downto 0);
+	signal sig_1122 : std_logic_vector(29 downto 0);
+	signal sig_1123 : std_logic_vector(31 downto 0);
+	signal sig_1124 : std_logic_vector(31 downto 0);
+	signal sig_1125 : std_logic_vector(19 downto 0);
+	signal sig_1126 : std_logic_vector(19 downto 0);
+	signal sig_1127 : std_logic_vector(19 downto 0);
+	signal sig_1128 : std_logic_vector(15 downto 0);
+	signal sig_1129 : std_logic_vector(31 downto 0);
+	signal sig_1130 : std_logic;
+	signal sig_1131 : std_logic_vector(31 downto 0);
+	signal sig_1132 : std_logic_vector(30 downto 0);
+	signal sig_1133 : std_logic_vector(31 downto 0);
+	signal sig_1134 : std_logic_vector(31 downto 0);
+	signal sig_1135 : std_logic_vector(31 downto 0);
+	signal sig_1136 : std_logic_vector(31 downto 0);
+	signal sig_1137 : std_logic_vector(31 downto 0);
+	signal sig_1138 : std_logic_vector(31 downto 0);
+	signal sig_1139 : std_logic_vector(31 downto 0);
+	signal sig_1140 : std_logic_vector(31 downto 0);
+	signal sig_1141 : std_logic_vector(31 downto 0);
+	signal sig_1142 : std_logic_vector(31 downto 0);
+	signal sig_1143 : std_logic_vector(30 downto 0);
+	signal sig_1144 : std_logic_vector(31 downto 0);
+	signal sig_1145 : std_logic_vector(31 downto 0);
+	signal sig_1146 : std_logic_vector(29 downto 0);
+	signal sig_1147 : std_logic_vector(30 downto 0);
+	signal sig_1148 : std_logic_vector(30 downto 0);
+	signal sig_1149 : std_logic_vector(31 downto 0);
+	signal sig_1150 : std_logic_vector(31 downto 0);
+	signal sig_1151 : std_logic_vector(19 downto 0);
+	signal sig_1152 : std_logic_vector(19 downto 0);
+	signal sig_1153 : std_logic_vector(7 downto 0);
+	signal sig_1154 : std_logic_vector(7 downto 0);
+	signal sig_1155 : std_logic_vector(26 downto 0);
+	signal sig_1156 : std_logic_vector(31 downto 0);
+	signal sig_1157 : std_logic;
+	signal sig_1158 : std_logic_vector(7 downto 0);
+	signal sig_1159 : std_logic_vector(7 downto 0);
+	signal sig_1160 : std_logic_vector(19 downto 0);
+	signal sig_1161 : std_logic_vector(31 downto 0);
+	signal sig_1162 : std_logic_vector(31 downto 0);
+	signal sig_1163 : std_logic_vector(19 downto 0);
+	signal sig_1164 : std_logic_vector(31 downto 0);
+	signal sig_1165 : std_logic_vector(19 downto 0);
+	signal sig_1166 : std_logic_vector(19 downto 0);
+	signal sig_1167 : std_logic_vector(19 downto 0);
+	signal sig_1168 : std_logic_vector(19 downto 0);
+	signal sig_1169 : std_logic_vector(19 downto 0);
+	signal sig_1170 : std_logic_vector(31 downto 0);
+	signal sig_1171 : std_logic_vector(19 downto 0);
+	signal sig_1172 : std_logic_vector(19 downto 0);
+	signal sig_1173 : std_logic_vector(19 downto 0);
+	signal sig_1174 : std_logic_vector(31 downto 0);
+	signal sig_1175 : std_logic_vector(31 downto 0);
+	signal sig_1176 : std_logic_vector(31 downto 0);
+	signal sig_1177 : std_logic_vector(31 downto 0);
+	signal sig_1178 : std_logic_vector(31 downto 0);
+	signal sig_1179 : std_logic_vector(19 downto 0);
+	signal sig_1180 : std_logic_vector(19 downto 0);
+	signal sig_1181 : std_logic_vector(19 downto 0);
+	signal sig_1182 : std_logic_vector(19 downto 0);
+	signal sig_1183 : std_logic_vector(19 downto 0);
+
+	-- Other inlined components
+
+	signal mux_66 : std_logic_vector(2 downto 0);
+	signal mux_30 : std_logic;
+	signal mux_32 : std_logic;
+	signal mux_33 : std_logic;
+	signal mux_34 : std_logic;
+	signal augh_main_k : std_logic_vector(31 downto 0) := (others => '0');
+	signal read32_ret0_10 : std_logic_vector(31 downto 0) := (others => '0');
+	signal mux_58 : std_logic_vector(2 downto 0);
+	signal mux_59 : std_logic_vector(2 downto 0);
+	signal mux_60 : std_logic;
+	signal mux_61 : std_logic_vector(7 downto 0);
+	signal mux_62 : std_logic_vector(2 downto 0);
+	signal mux_63 : std_logic_vector(2 downto 0);
+	signal mux_64 : std_logic;
+	signal mux_65 : std_logic_vector(7 downto 0);
+	signal mux_35 : std_logic;
+	signal mux_36 : std_logic;
+	signal mux_37 : std_logic_vector(15 downto 0);
+	signal mux_38 : std_logic;
+	signal mux_39 : std_logic_vector(31 downto 0);
+	signal idct_2d_r : std_logic_vector(31 downto 0) := (others => '0');
+	signal mux_45 : std_logic_vector(4 downto 0);
+	signal mux_46 : std_logic_vector(4 downto 0);
+	signal mux_47 : std_logic_vector(4 downto 0);
+	signal mux_48 : std_logic_vector(4 downto 0);
+	signal mux_49 : std_logic_vector(4 downto 0);
+	signal mux_40 : std_logic_vector(4 downto 0);
+	signal mux_41 : std_logic_vector(4 downto 0);
+	signal mux_42 : std_logic;
+	signal mux_43 : std_logic_vector(4 downto 0);
+	signal mux_44 : std_logic_vector(4 downto 0);
+	signal write8_u8 : std_logic_vector(7 downto 0) := (others => '0');
+	signal mux_50 : std_logic_vector(31 downto 0);
+	signal mux_51 : std_logic_vector(4 downto 0);
+	signal mux_52 : std_logic;
+	signal mux_53 : std_logic_vector(7 downto 0);
+	signal mux_54 : std_logic_vector(2 downto 0);
+	signal mux_55 : std_logic_vector(2 downto 0);
+	signal mux_56 : std_logic;
+	signal mux_57 : std_logic_vector(7 downto 0);
+	signal idct_z3_reg4 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_z3_reg5 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_z3_reg6 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_z3_reg7 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_z1_reg0 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_z1_reg1 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_z1_reg2 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_z1_reg3 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_z1_reg4 : std_logic_vector(31 downto 0) := (others => '0');
+	signal mux_88 : std_logic;
+	signal mux_67 : std_logic_vector(2 downto 0);
+	signal mux_68 : std_logic;
+	signal mux_69 : std_logic_vector(31 downto 0);
+	signal mux_71 : std_logic_vector(31 downto 0);
+	signal mux_73 : std_logic_vector(31 downto 0);
+	signal mux_75 : std_logic_vector(31 downto 0);
+	signal mux_77 : std_logic_vector(31 downto 0);
+	signal mux_79 : std_logic_vector(31 downto 0);
+	signal mux_81 : std_logic_vector(31 downto 0);
+	signal mux_83 : std_logic_vector(31 downto 0);
+	signal mux_85 : std_logic_vector(7 downto 0);
+	signal mux_86 : std_logic_vector(2 downto 0);
+	signal mux_87 : std_logic_vector(2 downto 0);
+	signal mux_28 : std_logic;
+	signal idct_z1_reg5 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_z1_reg6 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_z1_reg7 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_z2_reg0 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_z2_reg1 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_z2_reg2 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_z2_reg3 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_z2_reg4 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_z2_reg5 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_z2_reg6 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_z2_reg7 : std_logic_vector(31 downto 0) := (others => '0');
+	signal mux_109 : std_logic_vector(31 downto 0);
+	signal mux_154 : std_logic;
+	signal mux_156 : std_logic_vector(7 downto 0);
+	signal idct_2d_yc_reg0 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_2d_yc_reg1 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_2d_yc_reg2 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_2d_yc_reg3 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_2d_yc_reg4 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_2d_yc_reg5 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_2d_yc_reg6 : std_logic_vector(31 downto 0) := (others => '0');
+	signal idct_2d_yc_reg7 : std_logic_vector(31 downto 0) := (others => '0');
+	signal mux_89 : std_logic_vector(7 downto 0);
+	signal mux_90 : std_logic_vector(2 downto 0);
+	signal mux_134 : std_logic;
+	signal mux_91 : std_logic_vector(2 downto 0);
+	signal mux_92 : std_logic;
+	signal mux_158 : std_logic_vector(7 downto 0);
+	signal mux_111 : std_logic_vector(31 downto 0);
+	signal mux_113 : std_logic_vector(31 downto 0);
+	signal mux_115 : std_logic_vector(31 downto 0);
+	signal mux_117 : std_logic_vector(31 downto 0);
+	signal mux_119 : std_logic_vector(31 downto 0);
+	signal mux_121 : std_logic_vector(31 downto 0);
+	signal mux_123 : std_logic_vector(31 downto 0);
+	signal or_224 : std_logic_vector(31 downto 0);
+	signal and_225 : std_logic_vector(31 downto 0);
+	signal or_231 : std_logic_vector(31 downto 0);
+	signal and_232 : std_logic_vector(31 downto 0);
+	signal or_250 : std_logic_vector(31 downto 0);
+	signal and_251 : std_logic_vector(31 downto 0);
+	signal or_260 : std_logic_vector(31 downto 0);
+	signal and_261 : std_logic_vector(31 downto 0);
+	signal or_282 : std_logic_vector(31 downto 0);
+	signal and_283 : std_logic_vector(31 downto 0);
+	signal or_285 : std_logic_vector(31 downto 0);
+	signal and_286 : std_logic_vector(31 downto 0);
+	signal or_289 : std_logic_vector(31 downto 0);
+	signal and_290 : std_logic_vector(31 downto 0);
+	signal or_291 : std_logic_vector(31 downto 0);
+	signal and_292 : std_logic_vector(31 downto 0);
+	signal or_297 : std_logic_vector(31 downto 0);
+	signal and_298 : std_logic_vector(31 downto 0);
+	signal or_299 : std_logic_vector(31 downto 0);
+	signal and_300 : std_logic_vector(31 downto 0);
+	signal or_320 : std_logic_vector(31 downto 0);
+	signal and_321 : std_logic_vector(31 downto 0);
+	signal or_326 : std_logic_vector(31 downto 0);
+	signal and_327 : std_logic_vector(31 downto 0);
+	signal or_333 : std_logic_vector(31 downto 0);
+	signal and_334 : std_logic_vector(31 downto 0);
+	signal or_363 : std_logic_vector(31 downto 0);
+	signal and_364 : std_logic_vector(31 downto 0);
+	signal and_403 : std_logic_vector(7 downto 0);
+	signal and_405 : std_logic_vector(7 downto 0);
+	signal and_407 : std_logic_vector(7 downto 0);
+	signal and_409 : std_logic_vector(7 downto 0);
+	signal and_415 : std_logic_vector(30 downto 0);
+	signal or_464 : std_logic_vector(31 downto 0);
+	signal and_465 : std_logic_vector(31 downto 0);
+	signal or_470 : std_logic_vector(31 downto 0);
+	signal and_471 : std_logic_vector(31 downto 0);
+	signal or_472 : std_logic_vector(31 downto 0);
+	signal and_473 : std_logic_vector(31 downto 0);
+	signal or_500 : std_logic_vector(31 downto 0);
+	signal and_501 : std_logic_vector(31 downto 0);
+	signal or_504 : std_logic_vector(31 downto 0);
+	signal and_505 : std_logic_vector(31 downto 0);
+	signal or_506 : std_logic_vector(31 downto 0);
+	signal and_507 : std_logic_vector(31 downto 0);
+	signal or_514 : std_logic_vector(31 downto 0);
+	signal and_515 : std_logic_vector(31 downto 0);
+	signal or_522 : std_logic_vector(31 downto 0);
+	signal and_523 : std_logic_vector(31 downto 0);
+	signal psc_loop_reg_13 : std_logic_vector(15 downto 0) := (others => '0');
+	signal cp_id_reg_14 : std_logic := '0';
+	signal cp_id_reg_stable_15 : std_logic := '0';
+	signal psc_stuff_reg_18 : std_logic_vector(23 downto 0) := (others => '0');
+	signal psc_stuff_reg_19 : std_logic_vector(62 downto 0) := "000000000000000000000000000000000000000000000000000000000000000";
+	signal mux_129 : std_logic_vector(31 downto 0);
+	signal mux_133 : std_logic_vector(7 downto 0);
+	signal mux_135 : std_logic_vector(31 downto 0);
+	signal mux_137 : std_logic_vector(7 downto 0);
+	signal mux_138 : std_logic_vector(2 downto 0);
+	signal mux_139 : std_logic_vector(2 downto 0);
+	signal mux_140 : std_logic;
+	signal mux_141 : std_logic_vector(7 downto 0);
+	signal mux_142 : std_logic_vector(2 downto 0);
+	signal mux_143 : std_logic_vector(2 downto 0);
+	signal mux_144 : std_logic;
+	signal mux_147 : std_logic;
+	signal mux_149 : std_logic_vector(31 downto 0);
+	signal mux_150 : std_logic;
+	signal mux_151 : std_logic;
+	signal mux_152 : std_logic_vector(63 downto 0);
+	signal mux_155 : std_logic;
+	signal or_221 : std_logic_vector(31 downto 0);
+	signal and_222 : std_logic_vector(31 downto 0);
+	signal or_233 : std_logic_vector(31 downto 0);
+	signal and_234 : std_logic_vector(31 downto 0);
+	signal or_237 : std_logic_vector(31 downto 0);
+	signal and_238 : std_logic_vector(31 downto 0);
+	signal or_252 : std_logic_vector(31 downto 0);
+	signal and_253 : std_logic_vector(31 downto 0);
+	signal or_256 : std_logic_vector(31 downto 0);
+	signal and_257 : std_logic_vector(31 downto 0);
+	signal or_268 : std_logic_vector(31 downto 0);
+	signal and_269 : std_logic_vector(31 downto 0);
+	signal or_270 : std_logic_vector(31 downto 0);
+	signal and_271 : std_logic_vector(31 downto 0);
+	signal or_274 : std_logic_vector(31 downto 0);
+	signal and_275 : std_logic_vector(31 downto 0);
+	signal or_278 : std_logic_vector(31 downto 0);
+	signal and_279 : std_logic_vector(31 downto 0);
+	signal or_310 : std_logic_vector(31 downto 0);
+	signal and_311 : std_logic_vector(31 downto 0);
+	signal or_316 : std_logic_vector(31 downto 0);
+	signal and_317 : std_logic_vector(31 downto 0);
+	signal or_358 : std_logic_vector(31 downto 0);
+	signal and_359 : std_logic_vector(31 downto 0);
+	signal or_366 : std_logic_vector(31 downto 0);
+	signal and_367 : std_logic_vector(31 downto 0);
+	signal or_374 : std_logic_vector(31 downto 0);
+	signal and_375 : std_logic_vector(31 downto 0);
+	signal or_417 : std_logic_vector(31 downto 0);
+	signal and_418 : std_logic_vector(31 downto 0);
+	signal or_421 : std_logic_vector(31 downto 0);
+	signal and_422 : std_logic_vector(31 downto 0);
+	signal or_435 : std_logic_vector(31 downto 0);
+	signal and_436 : std_logic_vector(31 downto 0);
+	signal or_452 : std_logic_vector(31 downto 0);
+	signal and_453 : std_logic_vector(31 downto 0);
+	signal and_494 : std_logic_vector(31 downto 0);
+	signal and_498 : std_logic_vector(31 downto 0);
+	signal or_509 : std_logic_vector(30 downto 0);
+	signal and_510 : std_logic_vector(30 downto 0);
+	signal or_550 : std_logic_vector(31 downto 0);
+	signal and_551 : std_logic_vector(31 downto 0);
+	signal or_581 : std_logic_vector(31 downto 0);
+	signal and_582 : std_logic_vector(31 downto 0);
+	signal or_583 : std_logic_vector(31 downto 0);
+	signal and_584 : std_logic_vector(31 downto 0);
+	signal or_587 : std_logic_vector(31 downto 0);
+	signal and_588 : std_logic_vector(31 downto 0);
+	signal and_161 : std_logic;
+	signal or_228 : std_logic_vector(31 downto 0);
+	signal and_229 : std_logic_vector(31 downto 0);
+	signal or_239 : std_logic_vector(31 downto 0);
+	signal and_240 : std_logic_vector(31 downto 0);
+	signal or_241 : std_logic_vector(31 downto 0);
+	signal and_242 : std_logic_vector(31 downto 0);
+	signal or_244 : std_logic_vector(31 downto 0);
+	signal and_245 : std_logic_vector(31 downto 0);
+	signal or_246 : std_logic_vector(31 downto 0);
+	signal and_247 : std_logic_vector(31 downto 0);
+	signal or_248 : std_logic_vector(31 downto 0);
+	signal and_249 : std_logic_vector(31 downto 0);
+	signal or_258 : std_logic_vector(31 downto 0);
+	signal and_259 : std_logic_vector(31 downto 0);
+	signal not_264 : std_logic;
+	signal or_266 : std_logic_vector(31 downto 0);
+	signal and_267 : std_logic_vector(31 downto 0);
+	signal or_272 : std_logic_vector(31 downto 0);
+	signal and_273 : std_logic_vector(31 downto 0);
+	signal or_280 : std_logic_vector(31 downto 0);
+	signal and_281 : std_logic_vector(31 downto 0);
+	signal or_287 : std_logic_vector(31 downto 0);
+	signal and_288 : std_logic_vector(31 downto 0);
+	signal or_293 : std_logic_vector(31 downto 0);
+	signal and_294 : std_logic_vector(31 downto 0);
+	signal or_301 : std_logic_vector(31 downto 0);
+	signal and_302 : std_logic_vector(31 downto 0);
+	signal or_304 : std_logic_vector(31 downto 0);
+	signal and_305 : std_logic_vector(31 downto 0);
+	signal or_306 : std_logic_vector(31 downto 0);
+	signal and_307 : std_logic_vector(31 downto 0);
+	signal or_308 : std_logic_vector(31 downto 0);
+	signal and_309 : std_logic_vector(31 downto 0);
+	signal or_312 : std_logic_vector(31 downto 0);
+	signal and_313 : std_logic_vector(31 downto 0);
+	signal or_318 : std_logic_vector(31 downto 0);
+	signal and_319 : std_logic_vector(31 downto 0);
+	signal or_329 : std_logic_vector(31 downto 0);
+	signal and_330 : std_logic_vector(31 downto 0);
+	signal or_335 : std_logic_vector(31 downto 0);
+	signal and_336 : std_logic_vector(31 downto 0);
+	signal or_339 : std_logic_vector(31 downto 0);
+	signal and_340 : std_logic_vector(31 downto 0);
+	signal or_342 : std_logic_vector(31 downto 0);
+	signal and_343 : std_logic_vector(31 downto 0);
+	signal or_346 : std_logic_vector(31 downto 0);
+	signal and_347 : std_logic_vector(31 downto 0);
+	signal or_348 : std_logic_vector(31 downto 0);
+	signal and_349 : std_logic_vector(31 downto 0);
+	signal or_351 : std_logic_vector(30 downto 0);
+	signal and_352 : std_logic_vector(30 downto 0);
+	signal or_355 : std_logic_vector(30 downto 0);
+	signal and_356 : std_logic_vector(30 downto 0);
+	signal or_360 : std_logic_vector(31 downto 0);
+	signal and_361 : std_logic_vector(31 downto 0);
+	signal or_371 : std_logic_vector(31 downto 0);
+	signal and_372 : std_logic_vector(31 downto 0);
+	signal or_378 : std_logic_vector(31 downto 0);
+	signal and_379 : std_logic_vector(31 downto 0);
+	signal or_380 : std_logic_vector(31 downto 0);
+	signal and_381 : std_logic_vector(31 downto 0);
+	signal or_384 : std_logic_vector(31 downto 0);
+	signal and_385 : std_logic_vector(31 downto 0);
+	signal or_386 : std_logic_vector(31 downto 0);
+	signal and_387 : std_logic_vector(31 downto 0);
+	signal or_388 : std_logic_vector(31 downto 0);
+	signal and_389 : std_logic_vector(31 downto 0);
+	signal or_394 : std_logic_vector(7 downto 0);
+	signal and_395 : std_logic_vector(7 downto 0);
+	signal and_397 : std_logic_vector(7 downto 0);
+	signal and_399 : std_logic_vector(7 downto 0);
+	signal and_401 : std_logic_vector(7 downto 0);
+	signal or_414 : std_logic_vector(30 downto 0);
+	signal or_423 : std_logic_vector(31 downto 0);
+	signal and_424 : std_logic_vector(31 downto 0);
+	signal or_425 : std_logic_vector(31 downto 0);
+	signal and_426 : std_logic_vector(31 downto 0);
+	signal or_427 : std_logic_vector(31 downto 0);
+	signal and_428 : std_logic_vector(31 downto 0);
+	signal or_431 : std_logic_vector(31 downto 0);
+	signal and_432 : std_logic_vector(31 downto 0);
+	signal or_433 : std_logic_vector(31 downto 0);
+	signal and_434 : std_logic_vector(31 downto 0);
+	signal or_438 : std_logic_vector(31 downto 0);
+	signal and_439 : std_logic_vector(31 downto 0);
+	signal or_440 : std_logic_vector(31 downto 0);
+	signal and_441 : std_logic_vector(31 downto 0);
+	signal or_443 : std_logic_vector(31 downto 0);
+	signal and_444 : std_logic_vector(31 downto 0);
+	signal or_450 : std_logic_vector(31 downto 0);
+	signal and_451 : std_logic_vector(31 downto 0);
+	signal or_454 : std_logic_vector(30 downto 0);
+	signal and_455 : std_logic_vector(30 downto 0);
+	signal or_458 : std_logic_vector(31 downto 0);
+	signal and_459 : std_logic_vector(31 downto 0);
+	signal or_462 : std_logic_vector(31 downto 0);
+	signal and_463 : std_logic_vector(31 downto 0);
+	signal or_467 : std_logic_vector(30 downto 0);
+	signal and_468 : std_logic_vector(30 downto 0);
+	signal or_475 : std_logic_vector(30 downto 0);
+	signal and_476 : std_logic_vector(30 downto 0);
+	signal or_479 : std_logic_vector(31 downto 0);
+	signal and_480 : std_logic_vector(31 downto 0);
+	signal or_481 : std_logic_vector(31 downto 0);
+	signal and_482 : std_logic_vector(31 downto 0);
+	signal or_485 : std_logic_vector(31 downto 0);
+	signal and_486 : std_logic_vector(31 downto 0);
+	signal or_490 : std_logic_vector(31 downto 0);
+	signal and_491 : std_logic_vector(31 downto 0);
+	signal or_493 : std_logic_vector(31 downto 0);
+	signal or_497 : std_logic_vector(31 downto 0);
+	signal or_512 : std_logic_vector(31 downto 0);
+	signal and_513 : std_logic_vector(31 downto 0);
+	signal or_518 : std_logic_vector(30 downto 0);
+	signal and_519 : std_logic_vector(30 downto 0);
+	signal or_525 : std_logic_vector(31 downto 0);
+	signal and_526 : std_logic_vector(31 downto 0);
+	signal or_529 : std_logic_vector(30 downto 0);
+	signal and_530 : std_logic_vector(30 downto 0);
+	signal or_532 : std_logic_vector(30 downto 0);
+	signal and_533 : std_logic_vector(30 downto 0);
+	signal or_535 : std_logic_vector(31 downto 0);
+	signal and_536 : std_logic_vector(31 downto 0);
+	signal or_538 : std_logic_vector(31 downto 0);
+	signal and_539 : std_logic_vector(31 downto 0);
+	signal or_541 : std_logic_vector(31 downto 0);
+	signal and_542 : std_logic_vector(31 downto 0);
+	signal or_545 : std_logic_vector(30 downto 0);
+	signal and_546 : std_logic_vector(30 downto 0);
+	signal or_548 : std_logic_vector(31 downto 0);
+	signal and_549 : std_logic_vector(31 downto 0);
+	signal or_554 : std_logic_vector(30 downto 0);
+	signal and_555 : std_logic_vector(30 downto 0);
+	signal or_557 : std_logic_vector(30 downto 0);
+	signal and_558 : std_logic_vector(30 downto 0);
+	signal or_568 : std_logic_vector(31 downto 0);
+	signal and_569 : std_logic_vector(31 downto 0);
+	signal or_571 : std_logic_vector(30 downto 0);
+	signal and_572 : std_logic_vector(30 downto 0);
+	signal or_575 : std_logic_vector(30 downto 0);
+	signal and_576 : std_logic_vector(30 downto 0);
+	signal or_590 : std_logic_vector(31 downto 0);
+	signal and_591 : std_logic_vector(31 downto 0);
+	signal or_597 : std_logic_vector(31 downto 0);
+	signal and_598 : std_logic_vector(31 downto 0);
+	signal or_603 : std_logic_vector(30 downto 0);
+	signal and_604 : std_logic_vector(30 downto 0);
+
+	-- This utility function is used for to generate concatenations of std_logic
+
+	-- Little utility function to ease concatenation of an std_logic
+	-- and explicitely return an std_logic_vector
+	function repeat(N: natural; B: std_logic) return std_logic_vector is
+		variable result: std_logic_vector(N-1 downto 0);
+	begin
+		result := (others => B);
+		return result;
+	end;
+
+begin
+
+	-- Instantiation of components
+
+	output_split2_i : output_split2 port map (
+		wa0_data => mux_141,
+		wa0_addr => mux_142,
+		ra0_data => sig_1159,
+		ra0_addr => mux_143,
+		wa0_en => mux_144,
+		clk => sig_clock
+	);
+
+	output_split3_i : output_split3 port map (
+		wa0_data => mux_137,
+		wa0_addr => mux_138,
+		ra0_data => sig_1158,
+		ra0_addr => mux_139,
+		wa0_en => mux_140,
+		clk => sig_clock
+	);
+
+	sub_159_i : sub_159 port map (
+		gt => sig_1157,
+		result => sig_1156,
+		in_a => idct_2d_r,
+		in_b => "00000000000000000000000011111111",
+		sign => '1'
+	);
+
+	add_165_i : add_165 port map (
+		result => sig_1155,
+		in_a => idct_2d_yc_reg7(31 downto 5),
+		in_b => "000000000000000000000000001"
+	);
+
+	output_split1_i : output_split1 port map (
+		wa0_data => mux_89,
+		wa0_addr => mux_90,
+		ra0_data => sig_1154,
+		ra0_addr => mux_91,
+		wa0_en => mux_92,
+		clk => sig_clock
+	);
+
+	output_split0_i : output_split0 port map (
+		wa0_data => mux_85,
+		wa0_addr => mux_86,
+		ra0_data => sig_1153,
+		ra0_addr => mux_87,
+		wa0_en => mux_88,
+		clk => sig_clock
+	);
+
+	add_172_i : add_172 port map (
+		result => sig_1152,
+		in_a => sig_1183,
+		in_b => "00000000000000000001"
+	);
+
+	add_176_i : add_176 port map (
+		result => sig_1151,
+		in_a => sig_1182,
+		in_b => "00000000000000000001"
+	);
+
+	add_181_i : add_181 port map (
+		result => sig_1150,
+		in_a => idct_z2_reg0,
+		in_b => idct_z3_reg7
+	);
+
+	sub_187_i : sub_187 port map (
+		result => sig_1149,
+		in_a => idct_z2_reg1,
+		in_b => idct_z3_reg6
+	);
+
+	mul_189_i : mul_189 port map (
+		result => sig_1148,
+		in_a => idct_z2_reg4(30 downto 0),
+		in_b => "01000111000111"
+	);
+
+	add_191_i : add_191 port map (
+		result => sig_1147,
+		in_a => sig_1148,
+		in_b => sig_1123(31 downto 1)
+	);
+
+	mul_192_i : mul_192 port map (
+		result => sig_1146,
+		in_a => idct_z2_reg5(29 downto 0),
+		in_b => "01100011111"
+	);
+
+	mul_193_i : mul_193 port map (
+		result => sig_1145,
+		in_a => idct_z2_reg6,
+		in_b => "011111011000101"
+	);
+
+	mul_198_i : mul_198 port map (
+		result => sig_1144,
+		in_a => idct_z2_reg4,
+		in_b => "011010100110111"
+	);
+
+	mul_199_i : mul_199 port map (
+		result => sig_1143,
+		in_a => idct_z2_reg7(30 downto 0),
+		in_b => "01000111000111"
+	);
+
+	sub_209_i : sub_209 port map (
+		result => sig_1142,
+		in_a => idct_2d_yc_reg1,
+		in_b => idct_2d_yc_reg7
+	);
+
+	add_212_i : add_212 port map (
+		result => sig_1141,
+		in_a => idct_z1_reg1,
+		in_b => idct_z1_reg2
+	);
+
+	sub_213_i : sub_213 port map (
+		result => sig_1140,
+		in_a => idct_z1_reg1,
+		in_b => idct_z1_reg2
+	);
+
+	sub_214_i : sub_214 port map (
+		result => sig_1139,
+		in_a => idct_z1_reg0,
+		in_b => idct_z1_reg3
+	);
+
+	mul_215_i : mul_215 port map (
+		result => sig_1138,
+		in_a => idct_2d_yc_reg2,
+		in_b => "0101001110011111"
+	);
+
+	mul_216_i : mul_216 port map (
+		result => sig_1137,
+		in_a => idct_2d_yc_reg6,
+		in_b => "010001010100011"
+	);
+
+	sub_217_i : sub_217 port map (
+		result => sig_1136,
+		in_a => sig_1138,
+		in_b => sig_1137
+	);
+
+	mul_218_i : mul_218 port map (
+		result => sig_1135,
+		in_a => idct_2d_yc_reg2,
+		in_b => "010001010100011"
+	);
+
+	mul_219_i : mul_219 port map (
+		result => sig_1134,
+		in_a => idct_2d_yc_reg6,
+		in_b => "0101001110011111"
+	);
+
+	sub_220_i : sub_220 port map (
+		result => sig_1133,
+		in_a => sig_1135,
+		in_b => sig_1134
+	);
+
+	mul_223_i : mul_223 port map (
+		result => sig_1132,
+		in_a => idct_2d_yc_reg5(30 downto 0),
+		in_b => "010110101000001"
+	);
+
+	sub_227_i : sub_227 port map (
+		result => sig_1131,
+		in_a => idct_2d_yc_reg0,
+		in_b => idct_2d_yc_reg4
+	);
+
+	sub_157_i : sub_157 port map (
+		ge => sig_1130,
+		result => sig_1129,
+		in_a => idct_2d_r,
+		in_b => "00000000000000000000000000000000",
+		sign => '1'
+	);
+
+	add_163_i : add_163 port map (
+		result => sig_1128,
+		in_a => psc_loop_reg_13,
+		in_b => "0000000000000001"
+	);
+
+	cmp_164_i : cmp_164 port map (
+		ne => memextrct_loop_sig_21,
+		in0 => "0000000000011111",
+		in1 => psc_loop_reg_13
+	);
+
+	add_170_i : add_170 port map (
+		result => sig_1127,
+		in_a => sig_1181,
+		in_b => "00000000000000000001"
+	);
+
+	add_174_i : add_174 port map (
+		result => sig_1126,
+		in_a => sig_1180,
+		in_b => "00000000000000000001"
+	);
+
+	add_180_i : add_180 port map (
+		result => sig_1125,
+		in_a => sig_1179,
+		in_b => "00000000000000000001"
+	);
+
+	sub_186_i : sub_186 port map (
+		result => sig_1124,
+		in_a => idct_z2_reg2,
+		in_b => idct_z3_reg5
+	);
+
+	mul_190_i : mul_190 port map (
+		result => sig_1123,
+		in_a => idct_z2_reg7,
+		in_b => "011010100110111"
+	);
+
+	mul_196_i : mul_196 port map (
+		result => sig_1122,
+		in_a => idct_z2_reg6(29 downto 0),
+		in_b => "01100011111"
+	);
+
+	sub_200_i : sub_200 port map (
+		result => sig_1121,
+		in_a => sig_1144,
+		in_b => sig_1178
+	);
+
+	add_206_i : add_206 port map (
+		result => sig_1120,
+		in_a => idct_z1_reg4,
+		in_b => idct_z1_reg6
+	);
+
+	add_210_i : add_210 port map (
+		result => sig_1119,
+		in_a => idct_2d_yc_reg1,
+		in_b => idct_2d_yc_reg7
+	);
+
+	add_171_i : add_171 port map (
+		result => sig_1118,
+		in_a => idct_2d_yc_reg4(31 downto 5),
+		in_b => "000000000000000000000000001"
+	);
+
+	add_177_i : add_177 port map (
+		result => sig_1117,
+		in_a => idct_2d_yc_reg1(31 downto 5),
+		in_b => "000000000000000000000000001"
+	);
+
+	add_179_i : add_179 port map (
+		result => sig_1116,
+		in_a => idct_2d_yc_reg0(31 downto 5),
+		in_b => "000000000000000000000000001"
+	);
+
+	mul_195_i : mul_195 port map (
+		result => sig_1115,
+		in_a => idct_z2_reg5,
+		in_b => "011111011000101"
+	);
+
+	sub_197_i : sub_197 port map (
+		result => sig_1114,
+		in_a => sig_1115,
+		in_b => sig_1177
+	);
+
+	sub_207_i : sub_207 port map (
+		result => sig_1113,
+		in_a => idct_z1_reg7,
+		in_b => idct_z1_reg5
+	);
+
+	mul_230_i : mul_230 port map (
+		result => sig_1112,
+		in_a => idct_2d_yc_reg3(30 downto 0),
+		in_b => "010110101000001"
+	);
+
+	sub_185_i : sub_185 port map (
+		result => sig_1111,
+		in_a => idct_z2_reg3,
+		in_b => idct_z3_reg4
+	);
+
+	add_211_i : add_211 port map (
+		result => sig_1110,
+		in_a => idct_z1_reg0,
+		in_b => idct_z1_reg3
+	);
+
+	add_226_i : add_226 port map (
+		result => sig_1109,
+		in_a => idct_2d_yc_reg0,
+		in_b => idct_2d_yc_reg4
+	);
+
+	add_235_i : add_235 port map (
+		result => sig_1108,
+		in_a => idct_2d_yc_reg2(31 downto 5),
+		in_b => "000000000000000000000000001"
+	);
+
+	add_314_i : add_314 port map (
+		result => sig_1107,
+		in_a => idct_2d_yc_reg2(31 downto 5),
+		in_b => "000000000000000000000000001"
+	);
+
+	sub_160_i : sub_160 port map (
+		le => sig_1106,
+		result => sig_1105,
+		in_a => idct_2d_r,
+		in_b => "00000000000000000000000011111111",
+		sign => '1'
+	);
+
+	add_173_i : add_173 port map (
+		result => sig_1104,
+		in_a => idct_2d_yc_reg3(31 downto 5),
+		in_b => "000000000000000000000000001"
+	);
+
+	add_182_i : add_182 port map (
+		result => sig_1103,
+		in_a => idct_z2_reg1,
+		in_b => idct_z3_reg6
+	);
+
+	sub_188_i : sub_188 port map (
+		result => sig_1102,
+		in_a => idct_z2_reg0,
+		in_b => idct_z3_reg7
+	);
+
+	sub_243_i : sub_243 port map (
+		result => sig_1101,
+		in_a => sig_1115,
+		in_b => sig_1176
+	);
+
+	sub_262_i : sub_262 port map (
+		result => sig_1100,
+		in_a => sig_1115,
+		in_b => sig_1175
+	);
+
+	output_split4_i : output_split4 port map (
+		wa0_data => mux_65,
+		wa0_addr => mux_66,
+		ra0_data => sig_1099,
+		ra0_addr => mux_67,
+		wa0_en => mux_68,
+		clk => sig_clock
+	);
+
+	output_split5_i : output_split5 port map (
+		wa0_data => mux_61,
+		wa0_addr => mux_62,
+		ra0_data => sig_1098,
+		ra0_addr => mux_63,
+		wa0_en => mux_64,
+		clk => sig_clock
+	);
+
+	output_split6_i : output_split6 port map (
+		wa0_data => mux_57,
+		wa0_addr => mux_58,
+		ra0_data => sig_1097,
+		ra0_addr => mux_59,
+		wa0_en => mux_60,
+		clk => sig_clock
+	);
+
+	output_split7_i : output_split7 port map (
+		wa0_data => mux_53,
+		wa0_addr => mux_54,
+		ra0_data => sig_1096,
+		ra0_addr => mux_55,
+		wa0_en => mux_56,
+		clk => sig_clock
+	);
+
+	input_split0_i : input_split0 port map (
+		ra0_data => sig_1095,
+		ra0_addr => mux_46,
+		ra1_data => sig_1094,
+		ra1_addr => mux_47,
+		ra2_data => sig_1093,
+		ra2_addr => mux_48,
+		ra3_data => sig_1092,
+		ra3_addr => mux_49,
+		clk => sig_clock,
+		wa2_data => mux_50,
+		wa2_addr => mux_51,
+		wa2_en => mux_52
+	);
+
+	add_194_i : add_194 port map (
+		result => sig_1091,
+		in_a => sig_1146,
+		in_b => sig_1145(31 downto 2)
+	);
+
+	add_205_i : add_205 port map (
+		result => sig_1090,
+		in_a => idct_z1_reg7,
+		in_b => idct_z1_reg5
+	);
+
+	add_254_i : add_254 port map (
+		result => sig_1089,
+		in_a => idct_2d_yc_reg2(31 downto 5),
+		in_b => "000000000000000000000000001"
+	);
+
+	add_276_i : add_276 port map (
+		result => sig_1088,
+		in_a => idct_2d_yc_reg2(31 downto 5),
+		in_b => "000000000000000000000000001"
+	);
+
+	sub_284_i : sub_284 port map (
+		result => sig_1087,
+		in_a => sig_1115,
+		in_b => sig_1174
+	);
+
+	input_split1_i : input_split1 port map (
+		wa0_data => mux_39,
+		wa0_addr => mux_40,
+		ra0_data => sig_1086,
+		ra0_addr => mux_41,
+		wa0_en => mux_42,
+		ra1_data => sig_1085,
+		ra1_addr => mux_43,
+		ra2_data => sig_1084,
+		ra2_addr => mux_44,
+		ra3_data => sig_1083,
+		ra3_addr => mux_45,
+		clk => sig_clock
+	);
+
+	add_166_i : add_166 port map (
+		result => sig_1082,
+		in_a => sig_1173,
+		in_b => "00000000000000000001"
+	);
+
+	add_168_i : add_168 port map (
+		result => sig_1081,
+		in_a => sig_1172,
+		in_b => "00000000000000000001"
+	);
+
+	add_178_i : add_178 port map (
+		result => sig_1080,
+		in_a => sig_1171,
+		in_b => "00000000000000000001"
+	);
+
+	add_183_i : add_183 port map (
+		result => sig_1079,
+		in_a => idct_z2_reg2,
+		in_b => idct_z3_reg5
+	);
+
+	sub_332_i : sub_332 port map (
+		result => sig_1078,
+		in_a => sig_689,
+		in_b => sig_688
+	);
+
+	mul_341_i : mul_341 port map (
+		result => sig_1077,
+		in_a => or_339,
+		in_b => "0101001110011111"
+	);
+
+	mul_357_i : mul_357 port map (
+		result => sig_1076,
+		in_a => or_355,
+		in_b => "010110101000001"
+	);
+
+	mul_365_i : mul_365 port map (
+		result => sig_1075,
+		in_a => or_363,
+		in_b => "010001010100011"
+	);
+
+	mul_368_i : mul_368 port map (
+		result => sig_1074,
+		in_a => or_366,
+		in_b => "0101001110011111"
+	);
+
+	sub_369_i : sub_369 port map (
+		result => sig_1073,
+		in_a => sig_1075,
+		in_b => sig_1074
+	);
+
+	sub_370_i : sub_370 port map (
+		result => sig_1072,
+		in_a => sig_1115,
+		in_b => sig_1170
+	);
+
+	sub_377_i : sub_377 port map (
+		result => sig_1071,
+		in_a => sig_680,
+		in_b => sig_715
+	);
+
+	cmp_398_i : cmp_398 port map (
+		eq => sig_1070,
+		in0 => "110",
+		in1 => augh_main_k(2 downto 0)
+	);
+
+	cmp_400_i : cmp_400 port map (
+		eq => sig_1069,
+		in0 => "101",
+		in1 => augh_main_k(2 downto 0)
+	);
+
+	cmp_404_i : cmp_404 port map (
+		eq => sig_1068,
+		in0 => "011",
+		in1 => augh_main_k(2 downto 0)
+	);
+
+	cmp_406_i : cmp_406 port map (
+		eq => sig_1067,
+		in0 => "010",
+		in1 => augh_main_k(2 downto 0)
+	);
+
+	cmp_408_i : cmp_408 port map (
+		eq => sig_1066,
+		in0 => "001",
+		in1 => augh_main_k(2 downto 0)
+	);
+
+	cmp_410_i : cmp_410 port map (
+		eq => sig_1065,
+		in0 => "000",
+		in1 => augh_main_k(2 downto 0)
+	);
+
+	cmp_412_i : cmp_412 port map (
+		eq => sig_1064,
+		in0 => '0',
+		in1 => augh_main_k(0)
+	);
+
+	sub_429_i : sub_429 port map (
+		result => sig_1063,
+		in_a => or_421,
+		in_b => or_427
+	);
+
+	add_466_i : add_466 port map (
+		result => sig_1062,
+		in_a => or_462,
+		in_b => or_464
+	);
+
+	sub_496_i : sub_496 port map (
+		result => sig_1061,
+		in_a => sig_652,
+		in_b => sig_651
+	);
+
+	sub_521_i : sub_521 port map (
+		result => sig_1060,
+		in_a => or_438,
+		in_b => or_464
+	);
+
+	sub_528_i : sub_528 port map (
+		result => sig_1059,
+		in_a => sig_643,
+		in_b => sig_642
+	);
+
+	fsm_23_i : fsm_23 port map (
+		clock => sig_clock,
+		reset => sig_reset,
+		in0 => memextrct_loop_sig_21,
+		out181 => sig_1058,
+		out182 => sig_1057,
+		out183 => sig_1056,
+		out184 => sig_1055,
+		out185 => sig_1054,
+		out8 => sig_1053,
+		out13 => sig_1052,
+		out14 => sig_1051,
+		out16 => sig_1050,
+		out18 => sig_1049,
+		out19 => sig_1048,
+		out20 => sig_1047,
+		out21 => sig_1046,
+		out22 => sig_1045,
+		in2 => sig_start,
+		out23 => sig_1044,
+		out24 => sig_1043,
+		out25 => sig_1042,
+		out26 => sig_1041,
+		out27 => sig_1040,
+		out28 => sig_1039,
+		out29 => sig_1038,
+		out30 => sig_1037,
+		out31 => sig_1036,
+		out33 => sig_1035,
+		out35 => sig_1034,
+		out36 => sig_1033,
+		out38 => sig_1032,
+		out40 => sig_1031,
+		out42 => sig_1030,
+		in3 => memextrct_loop_sig_22,
+		out44 => sig_1029,
+		out46 => sig_1028,
+		out48 => sig_1027,
+		out49 => sig_1026,
+		out50 => sig_1025,
+		out52 => sig_1024,
+		out54 => sig_1023,
+		out56 => sig_1022,
+		out57 => sig_1021,
+		out58 => sig_1020,
+		in4 => test_cp_0_16,
+		out60 => sig_1019,
+		in5 => test_cp_1_17,
+		out164 => sig_1018,
+		out165 => sig_1017,
+		out167 => sig_1016,
+		out168 => sig_1015,
+		out170 => sig_1014,
+		out171 => sig_1013,
+		out173 => sig_1012,
+		out174 => sig_1011,
+		out176 => sig_1010,
+		out178 => sig_1009,
+		out0 => sig_1008,
+		out1 => sig_1007,
+		out2 => sig_1006,
+		in1 => cp_rest,
+		out4 => sig_1005,
+		out90 => sig_1004,
+		out91 => sig_1003,
+		out97 => sig_1002,
+		out99 => sig_1001,
+		out101 => sig_1000,
+		in6 => stdout_ack,
+		out103 => sig_999,
+		out105 => sig_998,
+		out106 => sig_997,
+		out107 => sig_996,
+		out108 => sig_995,
+		out135 => sig_994,
+		out136 => sig_993,
+		out137 => sig_992,
+		out138 => sig_991,
+		in11 => augh_test_9,
+		out140 => sig_990,
+		out141 => sig_989,
+		out142 => sig_988,
+		out143 => sig_987,
+		out145 => sig_986,
+		out146 => sig_985,
+		out148 => sig_984,
+		out150 => sig_983,
+		out153 => sig_982,
+		out154 => sig_981,
+		out155 => sig_980,
+		out156 => sig_979,
+		out157 => sig_978,
+		out158 => sig_977,
+		out159 => sig_976,
+		out160 => sig_975,
+		out161 => sig_974,
+		out162 => sig_973,
+		out111 => sig_972,
+		out112 => sig_971,
+		out114 => sig_970,
+		out116 => sig_969,
+		out118 => sig_968,
+		out120 => sig_967,
+		out121 => sig_966,
+		out122 => sig_965,
+		out123 => sig_964,
+		out124 => sig_963,
+		out125 => sig_962,
+		out126 => sig_961,
+		in7 => cp_en,
+		out129 => sig_960,
+		out130 => sig_959,
+		in8 => stdin_ack,
+		out131 => sig_958,
+		in9 => psc_loop_sig_20,
+		out132 => sig_957,
+		out133 => sig_956,
+		out134 => sig_955,
+		in10 => augh_test_11,
+		out186 => sig_954,
+		out187 => sig_953,
+		out190 => sig_952,
+		out195 => sig_951,
+		out197 => sig_950,
+		out198 => sig_949,
+		out199 => sig_948,
+		out200 => sig_947,
+		out201 => sig_946,
+		out203 => sig_945,
+		out204 => sig_944,
+		out206 => sig_943,
+		out207 => sig_942,
+		out209 => sig_941,
+		out210 => sig_940,
+		out212 => sig_939,
+		out213 => sig_938,
+		out215 => sig_937,
+		out217 => sig_936,
+		out220 => sig_935,
+		out221 => sig_934,
+		out222 => sig_933,
+		out223 => sig_932,
+		out224 => sig_931,
+		out225 => sig_930,
+		out226 => sig_929,
+		out227 => sig_928,
+		out228 => sig_927,
+		out229 => sig_926,
+		out231 => sig_925,
+		out232 => sig_924,
+		out234 => sig_923,
+		out235 => sig_922,
+		out237 => sig_921,
+		out238 => sig_920,
+		out240 => sig_919,
+		out241 => sig_918,
+		out243 => sig_917,
+		out245 => sig_916,
+		out248 => sig_915,
+		out249 => sig_914,
+		out250 => sig_913,
+		out251 => sig_912,
+		out252 => sig_911,
+		out253 => sig_910,
+		out254 => sig_909,
+		out255 => sig_908,
+		out256 => sig_907,
+		out257 => sig_906,
+		out259 => sig_905,
+		out260 => sig_904,
+		out262 => sig_903,
+		out263 => sig_902,
+		out265 => sig_901,
+		out266 => sig_900,
+		out268 => sig_899,
+		out269 => sig_898,
+		out271 => sig_897,
+		out273 => sig_896,
+		out276 => sig_895,
+		out277 => sig_894,
+		out278 => sig_893,
+		out279 => sig_892,
+		out280 => sig_891,
+		out281 => sig_890,
+		out282 => sig_889,
+		out283 => sig_888,
+		out284 => sig_887,
+		out285 => sig_886,
+		out286 => sig_885,
+		out287 => sig_884,
+		out288 => sig_883,
+		out289 => sig_882,
+		out290 => sig_881,
+		out291 => sig_880,
+		out292 => sig_879,
+		out293 => sig_878,
+		out294 => sig_877,
+		out295 => sig_876,
+		out296 => sig_875,
+		out297 => sig_874,
+		out298 => sig_873,
+		out311 => sig_872,
+		out312 => sig_871,
+		out313 => sig_870,
+		out314 => sig_869,
+		out315 => sig_868,
+		out316 => sig_867,
+		out318 => sig_866,
+		out321 => sig_865,
+		out322 => sig_864,
+		out323 => sig_863,
+		out324 => sig_862,
+		out325 => sig_861,
+		out326 => sig_860,
+		out327 => sig_859,
+		out328 => sig_858,
+		out329 => sig_857,
+		out333 => sig_856,
+		out341 => sig_855,
+		out342 => sig_854,
+		out343 => sig_853,
+		out344 => sig_852,
+		out345 => sig_851,
+		out346 => sig_850,
+		out349 => sig_849,
+		out350 => sig_848,
+		out351 => sig_847,
+		out352 => sig_846,
+		out353 => sig_845,
+		out354 => sig_844,
+		out355 => sig_843,
+		out357 => sig_842,
+		out361 => sig_841,
+		out362 => sig_840,
+		out363 => sig_839,
+		out364 => sig_838,
+		out366 => sig_837,
+		out367 => sig_836,
+		out371 => sig_835,
+		out372 => sig_834,
+		out373 => sig_833,
+		out382 => sig_832,
+		out383 => sig_831,
+		out385 => sig_830,
+		out393 => sig_829,
+		out394 => sig_828,
+		out395 => sig_827,
+		out396 => sig_826,
+		out398 => sig_825,
+		out400 => sig_824,
+		out401 => sig_823,
+		out402 => sig_822,
+		out404 => sig_821,
+		out406 => sig_820,
+		out407 => sig_819,
+		out408 => sig_818,
+		out409 => sig_817,
+		out410 => sig_816,
+		out411 => sig_815,
+		out412 => sig_814,
+		out413 => sig_813,
+		out414 => sig_812,
+		out416 => sig_811,
+		out417 => sig_810,
+		out418 => sig_809,
+		out419 => sig_808,
+		out422 => sig_807,
+		out423 => sig_806,
+		out425 => sig_805,
+		out426 => sig_804,
+		out428 => sig_803,
+		out429 => sig_802,
+		out430 => sig_801,
+		out431 => sig_800,
+		out433 => sig_799,
+		out434 => sig_798,
+		out435 => sig_797,
+		out436 => sig_796,
+		out437 => sig_795,
+		out438 => sig_794,
+		out440 => sig_793,
+		out441 => sig_792,
+		out443 => sig_791,
+		out444 => sig_790,
+		out445 => sig_789,
+		out446 => sig_788,
+		out447 => sig_787,
+		out450 => sig_786,
+		out451 => sig_785,
+		out454 => sig_784,
+		out455 => sig_783,
+		out457 => sig_782,
+		out458 => sig_781,
+		out459 => sig_780,
+		out460 => sig_779,
+		out461 => sig_778,
+		out462 => sig_777,
+		out463 => sig_776,
+		out464 => sig_775,
+		out465 => sig_774,
+		out466 => sig_773,
+		out467 => sig_772,
+		out468 => sig_771,
+		out469 => sig_770,
+		out472 => sig_769,
+		out475 => sig_768,
+		out481 => sig_767,
+		out482 => sig_766,
+		out483 => sig_765,
+		out484 => sig_764,
+		out487 => sig_763,
+		out488 => sig_762,
+		out491 => sig_761,
+		out495 => sig_760,
+		out496 => sig_759,
+		out497 => sig_758,
+		out498 => sig_757,
+		out499 => sig_756,
+		out500 => sig_755,
+		out501 => sig_754,
+		out512 => sig_753,
+		out513 => sig_752,
+		out517 => sig_751,
+		out518 => sig_750,
+		out519 => sig_749,
+		out521 => sig_748,
+		out522 => sig_747,
+		out524 => sig_746,
+		out525 => sig_745,
+		out526 => sig_744,
+		out527 => sig_743,
+		out528 => sig_742,
+		out531 => sig_741,
+		out540 => sig_740,
+		out542 => sig_739,
+		out544 => sig_738,
+		out545 => sig_737,
+		out554 => sig_736,
+		out555 => sig_735,
+		out559 => sig_734,
+		out560 => sig_733,
+		out561 => sig_732,
+		out562 => sig_731,
+		out563 => sig_730,
+		out566 => sig_729,
+		out567 => sig_728,
+		out570 => sig_727,
+		out572 => sig_726,
+		out575 => sig_725,
+		out577 => sig_724,
+		out578 => sig_723,
+		out580 => sig_722,
+		out581 => sig_721
+	);
+
+	add_167_i : add_167 port map (
+		result => sig_720,
+		in_a => idct_2d_yc_reg6(31 downto 5),
+		in_b => "000000000000000000000000001"
+	);
+
+	add_169_i : add_169 port map (
+		result => sig_719,
+		in_a => idct_2d_yc_reg5(31 downto 5),
+		in_b => "000000000000000000000000001"
+	);
+
+	add_175_i : add_175 port map (
+		result => sig_718,
+		in_a => idct_2d_yc_reg2(31 downto 5),
+		in_b => "000000000000000000000000001"
+	);
+
+	add_255_i : add_255 port map (
+		result => sig_717,
+		in_a => sig_1169,
+		in_b => "00000000000000000001"
+	);
+
+	sub_362_i : sub_362 port map (
+		result => sig_716,
+		in_a => or_358,
+		in_b => or_360
+	);
+
+	mul_376_i : mul_376 port map (
+		result => sig_715,
+		in_a => or_374,
+		in_b => "010001010100011"
+	);
+
+	add_420_i : add_420 port map (
+		result => sig_714,
+		in_a => sig_1168,
+		in_b => "00000000000000000001"
+	);
+
+	sub_446_i : sub_446 port map (
+		result => sig_713,
+		in_a => sig_667,
+		in_b => sig_666
+	);
+
+	mul_456_i : mul_456 port map (
+		result => sig_712,
+		in_a => or_454,
+		in_b => "010110101000001"
+	);
+
+	mul_457_i : mul_457 port map (
+		result => sig_711,
+		in_a => or_450,
+		in_b => "0101001110011111"
+	);
+
+	sub_461_i : sub_461 port map (
+		result => sig_710,
+		in_a => sig_711,
+		in_b => sig_662
+	);
+
+	sub_517_i : sub_517 port map (
+		result => sig_709,
+		in_a => or_512,
+		in_b => or_514
+	);
+
+	mul_560_i : mul_560 port map (
+		result => sig_708,
+		in_a => or_435,
+		in_b => "010001010100011"
+	);
+
+	mul_565_i : mul_565 port map (
+		result => sig_707,
+		in_a => or_363,
+		in_b => "0101001110011111"
+	);
+
+	mul_578_i : mul_578 port map (
+		result => sig_706,
+		in_a => or_431,
+		in_b => "010001010100011"
+	);
+
+	muxb_162_i : muxb_162 port map (
+		in_sel => cp_en,
+		out_data => sig_705,
+		in_data0 => '0',
+		in_data1 => '1'
+	);
+
+	add_184_i : add_184 port map (
+		result => sig_704,
+		in_a => idct_z2_reg3,
+		in_b => idct_z3_reg4
+	);
+
+	muxb_201_i : muxb_201 port map (
+		in_sel => cp_en,
+		out_data => sig_703,
+		in_data0 => '0',
+		in_data1 => '1'
+	);
+
+	cmp_202_i : cmp_202 port map (
+		ne => memextrct_loop_sig_22,
+		in0 => "0000000000000111",
+		in1 => psc_loop_reg_13
+	);
+
+	cmp_203_i : cmp_203 port map (
+		eq => test_cp_1_17,
+		in0 => '1',
+		in1 => cp_id_reg_stable_15
+	);
+
+	cmp_204_i : cmp_204 port map (
+		eq => sig_702,
+		in0 => '0',
+		in1 => cp_id_reg_stable_15
+	);
+
+	sub_208_i : sub_208 port map (
+		result => sig_701,
+		in_a => idct_z1_reg4,
+		in_b => idct_z1_reg6
+	);
+
+	add_236_i : add_236 port map (
+		result => sig_700,
+		in_a => sig_1167,
+		in_b => "00000000000000000001"
+	);
+
+	muxb_263_i : muxb_263 port map (
+		in_sel => not_264,
+		out_data => sig_699,
+		in_data0 => '0',
+		in_data1 => '1'
+	);
+
+	muxb_265_i : muxb_265 port map (
+		in_sel => not_264,
+		out_data => sig_698,
+		in_data0 => '0',
+		in_data1 => '1'
+	);
+
+	add_277_i : add_277 port map (
+		result => sig_697,
+		in_a => sig_1166,
+		in_b => "00000000000000000001"
+	);
+
+	add_295_i : add_295 port map (
+		result => sig_696,
+		in_a => idct_2d_yc_reg2(31 downto 5),
+		in_b => "000000000000000000000000001"
+	);
+
+	add_296_i : add_296 port map (
+		result => sig_695,
+		in_a => sig_1165,
+		in_b => "00000000000000000001"
+	);
+
+	sub_303_i : sub_303 port map (
+		result => sig_694,
+		in_a => sig_1115,
+		in_b => sig_1164
+	);
+
+	add_315_i : add_315 port map (
+		result => sig_693,
+		in_a => sig_1163,
+		in_b => "00000000000000000001"
+	);
+
+	muxb_322_i : muxb_322 port map (
+		in_sel => cp_en,
+		out_data => sig_692,
+		in_data0 => '0',
+		in_data1 => '1'
+	);
+
+	add_323_i : add_323 port map (
+		result => sig_691,
+		in_a => psc_loop_reg_13,
+		in_b => "0000000000000001"
+	);
+
+	cmp_324_i : cmp_324 port map (
+		ne => psc_loop_sig_20,
+		in0 => "0000000000000001",
+		in1 => psc_loop_reg_13
+	);
+
+	cmp_325_i : cmp_325 port map (
+		eq => sig_690,
+		in0 => '0',
+		in1 => cp_id_reg_stable_15
+	);
+
+	mul_328_i : mul_328 port map (
+		result => sig_689,
+		in_a => or_326,
+		in_b => "010001010100011"
+	);
+
+	mul_331_i : mul_331 port map (
+		result => sig_688,
+		in_a => or_329,
+		in_b => "0101001110011111"
+	);
+
+	sub_337_i : sub_337 port map (
+		result => sig_687,
+		in_a => or_333,
+		in_b => or_335
+	);
+
+	add_338_i : add_338 port map (
+		result => sig_686,
+		in_a => or_333,
+		in_b => or_297
+	);
+
+	mul_344_i : mul_344 port map (
+		result => sig_685,
+		in_a => or_342,
+		in_b => "010001010100011"
+	);
+
+	sub_345_i : sub_345 port map (
+		result => sig_684,
+		in_a => sig_1077,
+		in_b => sig_685
+	);
+
+	add_350_i : add_350 port map (
+		result => sig_683,
+		in_a => or_346,
+		in_b => or_348
+	);
+
+	mul_353_i : mul_353 port map (
+		result => sig_682,
+		in_a => or_351,
+		in_b => "010110101000001"
+	);
+
+	sub_354_i : sub_354 port map (
+		result => sig_681,
+		in_a => or_346,
+		in_b => or_348
+	);
+
+	mul_373_i : mul_373 port map (
+		result => sig_680,
+		in_a => or_371,
+		in_b => "0101001110011111"
+	);
+
+	add_382_i : add_382 port map (
+		result => sig_679,
+		in_a => or_378,
+		in_b => or_380
+	);
+
+	mul_383_i : mul_383 port map (
+		result => sig_678,
+		in_a => idct_2d_yc_reg3(30 downto 0),
+		in_b => "010110101000001"
+	);
+
+	add_390_i : add_390 port map (
+		result => sig_677,
+		in_a => or_386,
+		in_b => or_388
+	);
+
+	sub_391_i : sub_391 port map (
+		result => sig_676,
+		in_a => or_386,
+		in_b => or_388
+	);
+
+	cmp_392_i : cmp_392 port map (
+		ne => augh_test_11,
+		in0 => "00000000000000000000000000111111",
+		in1 => augh_main_k
+	);
+
+	add_393_i : add_393 port map (
+		result => sig_675,
+		in_a => augh_main_k,
+		in_b => "00000000000000000000000000000001"
+	);
+
+	cmp_396_i : cmp_396 port map (
+		eq => sig_674,
+		in0 => "111",
+		in1 => augh_main_k(2 downto 0)
+	);
+
+	cmp_402_i : cmp_402 port map (
+		eq => sig_673,
+		in0 => "100",
+		in1 => augh_main_k(2 downto 0)
+	);
+
+	cmp_411_i : cmp_411 port map (
+		eq => sig_672,
+		in0 => '1',
+		in1 => augh_main_k(0)
+	);
+
+	cmp_413_i : cmp_413 port map (
+		ne => augh_test_9,
+		in0 => "00000000000000000000000000111111",
+		in1 => augh_main_k
+	);
+
+	mul_416_i : mul_416 port map (
+		result => sig_671,
+		in_a => or_414,
+		in_b => "010110101000001"
+	);
+
+	add_419_i : add_419 port map (
+		result => sig_670,
+		in_a => idct_2d_yc_reg2(31 downto 5),
+		in_b => "000000000000000000000000001"
+	);
+
+	add_430_i : add_430 port map (
+		result => sig_669,
+		in_a => or_421,
+		in_b => or_427
+	);
+
+	sub_437_i : sub_437 port map (
+		result => sig_668,
+		in_a => sig_1115,
+		in_b => sig_1162
+	);
+
+	mul_442_i : mul_442 port map (
+		result => sig_667,
+		in_a => or_440,
+		in_b => "0101001110011111"
+	);
+
+	mul_445_i : mul_445 port map (
+		result => sig_666,
+		in_a => or_443,
+		in_b => "010001010100011"
+	);
+
+	mul_447_i : mul_447 port map (
+		result => sig_665,
+		in_a => or_440,
+		in_b => "010001010100011"
+	);
+
+	mul_448_i : mul_448 port map (
+		result => sig_664,
+		in_a => or_443,
+		in_b => "0101001110011111"
+	);
+
+	sub_449_i : sub_449 port map (
+		result => sig_663,
+		in_a => sig_665,
+		in_b => sig_664
+	);
+
+	mul_460_i : mul_460 port map (
+		result => sig_662,
+		in_a => or_458,
+		in_b => "010001010100011"
+	);
+
+	mul_469_i : mul_469 port map (
+		result => sig_661,
+		in_a => or_467,
+		in_b => "010110101000001"
+	);
+
+	add_474_i : add_474 port map (
+		result => sig_660,
+		in_a => or_470,
+		in_b => or_472
+	);
+
+	mul_477_i : mul_477 port map (
+		result => sig_659,
+		in_a => or_475,
+		in_b => "010110101000001"
+	);
+
+	sub_478_i : sub_478 port map (
+		result => sig_658,
+		in_a => or_470,
+		in_b => or_472
+	);
+
+	add_483_i : add_483 port map (
+		result => sig_657,
+		in_a => or_479,
+		in_b => or_481
+	);
+
+	sub_484_i : sub_484 port map (
+		result => sig_656,
+		in_a => or_479,
+		in_b => or_481
+	);
+
+	add_487_i : add_487 port map (
+		result => sig_655,
+		in_a => or_425,
+		in_b => or_485
+	);
+
+	sub_488_i : sub_488 port map (
+		result => sig_654,
+		in_a => or_425,
+		in_b => or_485
+	);
+
+	sub_489_i : sub_489 port map (
+		result => sig_653,
+		in_a => or_378,
+		in_b => or_285
+	);
+
+	mul_492_i : mul_492 port map (
+		result => sig_652,
+		in_a => or_490,
+		in_b => "010001010100011"
+	);
+
+	mul_495_i : mul_495 port map (
+		result => sig_651,
+		in_a => or_493,
+		in_b => "0101001110011111"
+	);
+
+	mul_499_i : mul_499 port map (
+		result => sig_650,
+		in_a => or_435,
+		in_b => "0101001110011111"
+	);
+
+	mul_502_i : mul_502 port map (
+		result => sig_649,
+		in_a => or_500,
+		in_b => "010001010100011"
+	);
+
+	sub_503_i : sub_503 port map (
+		result => sig_648,
+		in_a => sig_650,
+		in_b => sig_649
+	);
+
+	add_508_i : add_508 port map (
+		result => sig_647,
+		in_a => or_504,
+		in_b => or_506
+	);
+
+	mul_511_i : mul_511 port map (
+		result => sig_646,
+		in_a => or_509,
+		in_b => "010110101000001"
+	);
+
+	add_516_i : add_516 port map (
+		result => sig_645,
+		in_a => or_512,
+		in_b => or_514
+	);
+
+	mul_520_i : mul_520 port map (
+		result => sig_644,
+		in_a => or_518,
+		in_b => "010110101000001"
+	);
+
+	mul_524_i : mul_524 port map (
+		result => sig_643,
+		in_a => or_522,
+		in_b => "010001010100011"
+	);
+
+	mul_527_i : mul_527 port map (
+		result => sig_642,
+		in_a => or_525,
+		in_b => "0101001110011111"
+	);
+
+	mul_531_i : mul_531 port map (
+		result => sig_641,
+		in_a => or_529,
+		in_b => "010110101000001"
+	);
+
+	mul_534_i : mul_534 port map (
+		result => sig_640,
+		in_a => or_532,
+		in_b => "010110101000001"
+	);
+
+	add_537_i : add_537 port map (
+		result => sig_639,
+		in_a => or_497,
+		in_b => or_535
+	);
+
+	mul_540_i : mul_540 port map (
+		result => sig_638,
+		in_a => or_538,
+		in_b => "0101001110011111"
+	);
+
+	mul_543_i : mul_543 port map (
+		result => sig_637,
+		in_a => or_541,
+		in_b => "010001010100011"
+	);
+
+	sub_544_i : sub_544 port map (
+		result => sig_636,
+		in_a => sig_638,
+		in_b => sig_637
+	);
+
+	mul_547_i : mul_547 port map (
+		result => sig_635,
+		in_a => or_545,
+		in_b => "010110101000001"
+	);
+
+	add_552_i : add_552 port map (
+		result => sig_634,
+		in_a => or_548,
+		in_b => or_550
+	);
+
+	sub_553_i : sub_553 port map (
+		result => sig_633,
+		in_a => or_548,
+		in_b => or_550
+	);
+
+	mul_556_i : mul_556 port map (
+		result => sig_632,
+		in_a => or_554,
+		in_b => "010110101000001"
+	);
+
+	mul_559_i : mul_559 port map (
+		result => sig_631,
+		in_a => or_557,
+		in_b => "010110101000001"
+	);
+
+	mul_561_i : mul_561 port map (
+		result => sig_630,
+		in_a => or_500,
+		in_b => "0101001110011111"
+	);
+
+	sub_562_i : sub_562 port map (
+		result => sig_629,
+		in_a => sig_708,
+		in_b => sig_630
+	);
+
+	sub_563_i : sub_563 port map (
+		result => sig_628,
+		in_a => or_504,
+		in_b => or_506
+	);
+
+	add_564_i : add_564 port map (
+		result => sig_627,
+		in_a => or_358,
+		in_b => or_360
+	);
+
+	mul_566_i : mul_566 port map (
+		result => sig_626,
+		in_a => or_366,
+		in_b => "010001010100011"
+	);
+
+	sub_567_i : sub_567 port map (
+		result => sig_625,
+		in_a => sig_707,
+		in_b => sig_626
+	);
+
+	add_570_i : add_570 port map (
+		result => sig_624,
+		in_a => or_417,
+		in_b => or_568
+	);
+
+	mul_573_i : mul_573 port map (
+		result => sig_623,
+		in_a => or_571,
+		in_b => "010110101000001"
+	);
+
+	sub_574_i : sub_574 port map (
+		result => sig_622,
+		in_a => or_417,
+		in_b => or_568
+	);
+
+	mul_577_i : mul_577 port map (
+		result => sig_621,
+		in_a => or_575,
+		in_b => "010110101000001"
+	);
+
+	mul_579_i : mul_579 port map (
+		result => sig_620,
+		in_a => or_541,
+		in_b => "0101001110011111"
+	);
+
+	sub_580_i : sub_580 port map (
+		result => sig_619,
+		in_a => sig_706,
+		in_b => sig_620
+	);
+
+	sub_585_i : sub_585 port map (
+		result => sig_618,
+		in_a => or_581,
+		in_b => or_583
+	);
+
+	sub_586_i : sub_586 port map (
+		result => sig_617,
+		in_a => sig_1115,
+		in_b => sig_1161
+	);
+
+	mul_589_i : mul_589 port map (
+		result => sig_616,
+		in_a => or_587,
+		in_b => "0101001110011111"
+	);
+
+	mul_592_i : mul_592 port map (
+		result => sig_615,
+		in_a => or_590,
+		in_b => "010001010100011"
+	);
+
+	sub_593_i : sub_593 port map (
+		result => sig_614,
+		in_a => sig_616,
+		in_b => sig_615
+	);
+
+	mul_594_i : mul_594 port map (
+		result => sig_613,
+		in_a => or_587,
+		in_b => "010001010100011"
+	);
+
+	mul_595_i : mul_595 port map (
+		result => sig_612,
+		in_a => or_590,
+		in_b => "0101001110011111"
+	);
+
+	sub_596_i : sub_596 port map (
+		result => sig_611,
+		in_a => sig_613,
+		in_b => sig_612
+	);
+
+	sub_599_i : sub_599 port map (
+		result => sig_610,
+		in_a => or_423,
+		in_b => or_597
+	);
+
+	add_600_i : add_600 port map (
+		result => sig_609,
+		in_a => or_423,
+		in_b => or_597
+	);
+
+	add_601_i : add_601 port map (
+		result => sig_608,
+		in_a => idct_2d_yc_reg2(31 downto 5),
+		in_b => "000000000000000000000000001"
+	);
+
+	add_602_i : add_602 port map (
+		result => sig_607,
+		in_a => sig_1160,
+		in_b => "00000000000000000001"
+	);
+
+	mul_605_i : mul_605 port map (
+		result => sig_606,
+		in_a => or_603,
+		in_b => "010110101000001"
+	);
+
+	-- Behaviour of component 'mux_66' model 'mux'
+	mux_66 <=
+		(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
+		(repeat(3, sig_947) and "110") or
+		(repeat(3, sig_945) and "101") or
+		(repeat(3, sig_943) and "100") or
+		(repeat(3, sig_941) and "011") or
+		(repeat(3, sig_949) and "111") or
+		(repeat(3, sig_939) and "010") or
+		(repeat(3, sig_937) and "001");
+
+	-- Behaviour of component 'mux_30' model 'mux'
+	mux_30 <=
+		(sig_873 and cp_en);
+
+	-- Behaviour of component 'mux_32' model 'mux'
+	mux_32 <=
+		(sig_1002 and sig_702) or
+		(sig_872 and sig_690);
+
+	-- Behaviour of component 'mux_33' model 'mux'
+	mux_33 <=
+		(sig_1039 and cp_din(0)) or
+		(sig_954 and '1');
+
+	-- Behaviour of component 'mux_34' model 'mux'
+	mux_34 <=
+		(sig_1038 and cp_rest) or
+		(sig_953 and '1');
+
+	-- Behaviour of component 'mux_58' model 'mux'
+	mux_58 <=
+		(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
+		(repeat(3, sig_966) and "110") or
+		(repeat(3, sig_957) and "101") or
+		(repeat(3, sig_956) and "100") or
+		(repeat(3, sig_990) and "011") or
+		(repeat(3, sig_996) and "111") or
+		(repeat(3, sig_986) and "010") or
+		(repeat(3, sig_984) and "001");
+
+	-- Behaviour of component 'mux_59' model 'mux'
+	mux_59 <=
+		(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
+		(repeat(3, sig_833) and augh_main_k(5 downto 3));
+
+	-- Behaviour of component 'mux_60' model 'mux'
+	mux_60 <=
+		(sig_1004 and and_161) or
+		(sig_995 and '1');
+
+	-- Behaviour of component 'mux_61' model 'mux'
+	mux_61 <=
+		(repeat(8, sig_1003) and cp_din(23 downto 16)) or
+		(repeat(8, sig_977) and mux_156);
+
+	-- Behaviour of component 'mux_62' model 'mux'
+	mux_62 <=
+		(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
+		(repeat(3, sig_974) and "110") or
+		(repeat(3, sig_1018) and "101") or
+		(repeat(3, sig_1016) and "100") or
+		(repeat(3, sig_1014) and "011") or
+		(repeat(3, sig_976) and "111") or
+		(repeat(3, sig_1012) and "010") or
+		(repeat(3, sig_1010) and "001");
+
+	-- Behaviour of component 'mux_63' model 'mux'
+	mux_63 <=
+		(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
+		(repeat(3, sig_833) and augh_main_k(5 downto 3));
+
+	-- Behaviour of component 'mux_64' model 'mux'
+	mux_64 <=
+		(sig_1004 and and_161) or
+		(sig_975 and '1');
+
+	-- Behaviour of component 'mux_65' model 'mux'
+	mux_65 <=
+		(repeat(8, sig_1003) and cp_din(31 downto 24)) or
+		(repeat(8, sig_950) and mux_156);
+
+	-- Behaviour of component 'mux_35' model 'mux'
+	mux_35 <=
+		(sig_954 and '1') or
+		(sig_874 and augh_main_k(0));
+
+	-- Behaviour of component 'mux_36' model 'mux'
+	mux_36 <=
+		(sig_953 and '1') or
+		(sig_873 and cp_en);
+
+	-- Behaviour of component 'mux_37' model 'mux'
+	mux_37 <=
+		(repeat(16, sig_1052) and sig_1128) or
+		(repeat(16, sig_874) and sig_691);
+
+	-- Behaviour of component 'mux_38' model 'mux'
+	mux_38 <=
+		(sig_1051 and cp_en) or
+		(sig_1049 and '1');
+
+	-- Behaviour of component 'mux_39' model 'mux'
+	mux_39 <=
+		(repeat(32, sig_1005) and cp_din(31 downto 0)) or
+		(repeat(32, sig_884) and sig_704) or
+		(repeat(32, sig_880) and sig_1124) or
+		(repeat(32, sig_862) and sig_1103) or
+		(repeat(32, sig_859) and sig_1102) or
+		(repeat(32, sig_887) and (sig_1084(28 downto 0) & "000")) or
+		(repeat(32, sig_831) and read32_ret0_10) or
+		(repeat(32, sig_733) and (sig_1085(28 downto 0) & "000"));
+
+	-- Behaviour of component 'mux_45' model 'mux'
+	mux_45 <=
+		(repeat(5, sig_857) and "01101") or
+		(repeat(5, sig_754) and "11011") or
+		(repeat(5, sig_742) and "10111") or
+		(repeat(5, sig_737) and "10001") or
+		(repeat(5, sig_770) and "11111");
+
+	-- Behaviour of component 'mux_46' model 'mux'
+	mux_46 <=
+		(repeat(5, sig_867) and "01010") or
+		(repeat(5, sig_852) and "01111") or
+		(repeat(5, sig_843) and "11110") or
+		(repeat(5, sig_769) and "11010") or
+		(repeat(5, sig_761) and "11111") or
+		(repeat(5, sig_857) and "01011") or
+		(repeat(5, sig_755) and "10110") or
+		(repeat(5, sig_741) and "10011");
+
+	-- Behaviour of component 'mux_47' model 'mux'
+	mux_47 <=
+		(repeat(5, sig_867) and "01011") or
+		(repeat(5, sig_852) and "01110") or
+		(repeat(5, sig_843) and "11111") or
+		(repeat(5, sig_788) and "00001") or
+		(repeat(5, sig_770) and "11011") or
+		(repeat(5, sig_730) and "00111") or
+		(repeat(5, sig_857) and "01001") or
+		(repeat(5, sig_764) and "00110") or
+		(repeat(5, sig_742) and "10010") or
+		(repeat(5, sig_735) and "10000") or
+		(repeat(5, sig_762) and "00010") or
+		(repeat(5, sig_761) and "11101") or
+		(repeat(5, sig_755) and "10111") or
+		(repeat(5, sig_752) and "11001");
+
+	-- Behaviour of component 'mux_48' model 'mux'
+	mux_48 <=
+		(repeat(5, sig_1005) and psc_loop_reg_13(4 downto 0)) or
+		(repeat(5, sig_865) and "01101") or
+		(repeat(5, sig_844) and "11101") or
+		(repeat(5, sig_823) and "11000") or
+		(repeat(5, sig_818) and "10100") or
+		(repeat(5, sig_810) and "00100") or
+		(repeat(5, sig_804) and "10001") or
+		(repeat(5, sig_797) and "10101") or
+		(repeat(5, sig_785) and "11001") or
+		(repeat(5, sig_758) and "10000") or
+		(repeat(5, sig_731) and "00101") or
+		(repeat(5, sig_1017) and "11011") or
+		(repeat(5, sig_1015) and "10111") or
+		(repeat(5, sig_1013) and "10011") or
+		(repeat(5, sig_1011) and "01111") or
+		(repeat(5, sig_918) and "01110") or
+		(repeat(5, sig_916) and "01010") or
+		(repeat(5, sig_915) and "00110") or
+		(repeat(5, sig_973) and "11111") or
+		(repeat(5, sig_913) and "00010") or
+		(repeat(5, sig_891) and "01001") or
+		(repeat(5, sig_871) and "01100") or
+		(repeat(5, sig_1009) and "01011") or
+		(repeat(5, sig_922) and "10110") or
+		(repeat(5, sig_920) and "10010") or
+		(repeat(5, sig_1058) and "00111") or
+		(repeat(5, sig_1056) and "00011") or
+		(repeat(5, sig_926) and "11110") or
+		(repeat(5, sig_924) and "11010");
+
+	-- Behaviour of component 'mux_49' model 'mux'
+	mux_49 <=
+		(repeat(5, sig_866) and "01000") or
+		(repeat(5, sig_842) and "11100") or
+		(repeat(5, sig_787) and "00011") or
+		(repeat(5, sig_770) and "11000") or
+		(repeat(5, sig_755) and "10100") or
+		(repeat(5, sig_850) and "01101") or
+		(repeat(5, sig_752) and "11011") or
+		(repeat(5, sig_742) and "10001") or
+		(repeat(5, sig_735) and "10010");
+
+	-- Behaviour of component 'mux_40' model 'mux'
+	mux_40 <=
+		(repeat(5, sig_1005) and psc_loop_reg_13(4 downto 0)) or
+		(repeat(5, sig_794) and "11000") or
+		(repeat(5, sig_782) and "10100") or
+		(repeat(5, sig_781) and "11100") or
+		(repeat(5, sig_780) and "11110") or
+		(repeat(5, sig_776) and "11001") or
+		(repeat(5, sig_773) and "01001") or
+		(repeat(5, sig_771) and "10011") or
+		(repeat(5, sig_763) and "10001") or
+		(repeat(5, sig_760) and "11010") or
+		(repeat(5, sig_759) and "10101") or
+		(repeat(5, sig_751) and "10110") or
+		(repeat(5, sig_750) and "00111") or
+		(repeat(5, sig_748) and "01011") or
+		(repeat(5, sig_744) and "01110") or
+		(repeat(5, sig_736) and "01100") or
+		(repeat(5, sig_883) and "00101") or
+		(repeat(5, sig_879) and "00010") or
+		(repeat(5, sig_875) and "00110") or
+		(repeat(5, sig_863) and "01010") or
+		(repeat(5, sig_828) and "10000") or
+		(repeat(5, sig_827) and "01111") or
+		(repeat(5, sig_886) and "01101") or
+		(repeat(5, sig_824) and "11011") or
+		(repeat(5, sig_807) and "00001") or
+		(repeat(5, sig_803) and "11111") or
+		(repeat(5, sig_861) and "00100") or
+		(repeat(5, sig_845) and "10111") or
+		(repeat(5, sig_831) and augh_main_k(5 downto 1)) or
+		(repeat(5, sig_860) and "10010") or
+		(repeat(5, sig_858) and "00011") or
+		(repeat(5, sig_854) and "01000") or
+		(repeat(5, sig_849) and "11101");
+
+	-- Behaviour of component 'mux_41' model 'mux'
+	mux_41 <=
+		(repeat(5, sig_857) and "01110") or
+		(repeat(5, sig_754) and "11010") or
+		(repeat(5, sig_742) and "10110") or
+		(repeat(5, sig_737) and "10010") or
+		(repeat(5, sig_770) and "11110");
+
+	-- Behaviour of component 'mux_42' model 'mux'
+	mux_42 <=
+		(sig_1053 and and_161) or
+		(sig_830 and sig_672) or
+		(sig_885 and '1');
+
+	-- Behaviour of component 'mux_43' model 'mux'
+	mux_43 <=
+		(repeat(5, sig_857) and "01111") or
+		(repeat(5, sig_826) and "00001") or
+		(repeat(5, sig_808) and "01011") or
+		(repeat(5, sig_768) and "11100") or
+		(repeat(5, sig_754) and "11000") or
+		(repeat(5, sig_836) and "00111") or
+		(repeat(5, sig_749) and "00101") or
+		(repeat(5, sig_728) and "00011") or
+		(repeat(5, sig_747) and "00110") or
+		(repeat(5, sig_742) and "10100") or
+		(repeat(5, sig_740) and "00010") or
+		(repeat(5, sig_737) and "10011");
+
+	-- Behaviour of component 'mux_44' model 'mux'
+	mux_44 <=
+		(repeat(5, sig_1005) and psc_loop_reg_13(4 downto 0)) or
+		(repeat(5, sig_902) and "10101") or
+		(repeat(5, sig_900) and "10001") or
+		(repeat(5, sig_898) and "01101") or
+		(repeat(5, sig_896) and "01001") or
+		(repeat(5, sig_895) and "00101") or
+		(repeat(5, sig_893) and "00001") or
+		(repeat(5, sig_856) and "01100") or
+		(repeat(5, sig_838) and "10100") or
+		(repeat(5, sig_837) and "00100") or
+		(repeat(5, sig_829) and "10000") or
+		(repeat(5, sig_821) and "01000") or
+		(repeat(5, sig_800) and "11000") or
+		(repeat(5, sig_958) and "11011") or
+		(repeat(5, sig_991) and "10111") or
+		(repeat(5, sig_987) and "10011") or
+		(repeat(5, sig_985) and "01111") or
+		(repeat(5, sig_938) and "01110") or
+		(repeat(5, sig_936) and "01010") or
+		(repeat(5, sig_935) and "00110") or
+		(repeat(5, sig_961) and "11111") or
+		(repeat(5, sig_933) and "00010") or
+		(repeat(5, sig_906) and "11101") or
+		(repeat(5, sig_904) and "11001") or
+		(repeat(5, sig_983) and "01011") or
+		(repeat(5, sig_942) and "10110") or
+		(repeat(5, sig_940) and "10010") or
+		(repeat(5, sig_982) and "00111") or
+		(repeat(5, sig_980) and "00011") or
+		(repeat(5, sig_946) and "11110") or
+		(repeat(5, sig_944) and "11010");
+
+	-- Behaviour of component 'mux_50' model 'mux'
+	mux_50 <=
+		(repeat(32, sig_1005) and cp_din(63 downto 32)) or
+		(repeat(32, sig_882) and sig_1111) or
+		(repeat(32, sig_877) and sig_1079) or
+		(repeat(32, sig_869) and sig_1149) or
+		(repeat(32, sig_847) and sig_1150) or
+		(repeat(32, sig_890) and (sig_1093(28 downto 0) & "000")) or
+		(repeat(32, sig_831) and read32_ret0_10) or
+		(repeat(32, sig_777) and (sig_1094(28 downto 0) & "000")) or
+		(repeat(32, sig_766) and (sig_1092(28 downto 0) & "000"));
+
+	-- Behaviour of component 'mux_51' model 'mux'
+	mux_51 <=
+		(repeat(5, sig_1005) and psc_loop_reg_13(4 downto 0)) or
+		(repeat(5, sig_796) and "10101") or
+		(repeat(5, sig_795) and "10110") or
+		(repeat(5, sig_793) and "11111") or
+		(repeat(5, sig_790) and "11101") or
+		(repeat(5, sig_779) and "11010") or
+		(repeat(5, sig_778) and "01011") or
+		(repeat(5, sig_775) and "11001") or
+		(repeat(5, sig_767) and "11100") or
+		(repeat(5, sig_765) and "01000") or
+		(repeat(5, sig_756) and "10000") or
+		(repeat(5, sig_753) and "10011") or
+		(repeat(5, sig_746) and "10010") or
+		(repeat(5, sig_745) and "01010") or
+		(repeat(5, sig_729) and "11110") or
+		(repeat(5, sig_881) and "00110") or
+		(repeat(5, sig_878) and "01111") or
+		(repeat(5, sig_876) and "00101") or
+		(repeat(5, sig_870) and "01100") or
+		(repeat(5, sig_817) and "10100") or
+		(repeat(5, sig_813) and "00010") or
+		(repeat(5, sig_812) and "00001") or
+		(repeat(5, sig_889) and "01001") or
+		(repeat(5, sig_809) and "00100") or
+		(repeat(5, sig_799) and "10001") or
+		(repeat(5, sig_798) and "11011") or
+		(repeat(5, sig_868) and "00011") or
+		(repeat(5, sig_831) and augh_main_k(5 downto 1)) or
+		(repeat(5, sig_819) and "10111") or
+		(repeat(5, sig_864) and "01101") or
+		(repeat(5, sig_855) and "01110") or
+		(repeat(5, sig_853) and "00111") or
+		(repeat(5, sig_846) and "11000");
+
+	-- Behaviour of component 'mux_52' model 'mux'
+	mux_52 <=
+		(sig_1053 and and_161) or
+		(sig_830 and sig_1064) or
+		(sig_888 and '1');
+
+	-- Behaviour of component 'mux_53' model 'mux'
+	mux_53 <=
+		(repeat(8, sig_1008) and mux_156) or
+		(repeat(8, sig_1003) and cp_din(7 downto 0));
+
+	-- Behaviour of component 'mux_54' model 'mux'
+	mux_54 <=
+		(repeat(3, sig_1007) and "111") or
+		(repeat(3, sig_1045) and "101") or
+		(repeat(3, sig_1043) and "100") or
+		(repeat(3, sig_1041) and "011") or
+		(repeat(3, sig_1037) and "010") or
+		(repeat(3, sig_1048) and "110") or
+		(repeat(3, sig_1035) and "001") or
+		(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0));
+
+	-- Behaviour of component 'mux_55' model 'mux'
+	mux_55 <=
+		(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
+		(repeat(3, sig_833) and augh_main_k(5 downto 3));
+
+	-- Behaviour of component 'mux_56' model 'mux'
+	mux_56 <=
+		(sig_1006 and '1') or
+		(sig_1004 and and_161);
+
+	-- Behaviour of component 'mux_57' model 'mux'
+	mux_57 <=
+		(repeat(8, sig_1003) and cp_din(15 downto 8)) or
+		(repeat(8, sig_997) and mux_156);
+
+	-- Behaviour of component 'mux_88' model 'mux'
+	mux_88 <=
+		(sig_1004 and and_161) or
+		(sig_839 and '1');
+
+	-- Behaviour of component 'mux_67' model 'mux'
+	mux_67 <=
+		(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
+		(repeat(3, sig_833) and augh_main_k(5 downto 3));
+
+	-- Behaviour of component 'mux_68' model 'mux'
+	mux_68 <=
+		(sig_1004 and and_161) or
+		(sig_948 and '1');
+
+	-- Behaviour of component 'mux_69' model 'mux'
+	mux_69 <=
+		(repeat(32, sig_1026) and sig_1102) or
+		(repeat(32, sig_974) and or_244) or
+		(repeat(32, sig_947) and or_266) or
+		(repeat(32, sig_927) and or_285) or
+		(repeat(32, sig_907) and or_304) or
+		(repeat(32, sig_966) and or_221) or
+		(repeat(32, sig_802) and or_378) or
+		(repeat(32, sig_727) and or_371) or
+		(repeat(32, sig_723) and or_470);
+
+	-- Behaviour of component 'mux_71' model 'mux'
+	mux_71 <=
+		(repeat(32, sig_1026) and sig_1149) or
+		(repeat(32, sig_1018) and or_246) or
+		(repeat(32, sig_945) and or_268) or
+		(repeat(32, sig_925) and or_287) or
+		(repeat(32, sig_905) and or_306) or
+		(repeat(32, sig_957) and or_224) or
+		(repeat(32, sig_801) and or_433) or
+		(repeat(32, sig_789) and or_438) or
+		(repeat(32, sig_786) and or_450);
+
+	-- Behaviour of component 'mux_73' model 'mux'
+	mux_73 <=
+		(repeat(32, sig_1026) and sig_1124) or
+		(repeat(32, sig_1016) and or_248) or
+		(repeat(32, sig_943) and or_270) or
+		(repeat(32, sig_923) and or_289) or
+		(repeat(32, sig_903) and or_308) or
+		(repeat(32, sig_956) and or_228) or
+		(repeat(32, sig_840) and or_384) or
+		(repeat(32, sig_792) and or_435) or
+		(repeat(32, sig_774) and or_452);
+
+	-- Behaviour of component 'mux_75' model 'mux'
+	mux_75 <=
+		(repeat(32, sig_1026) and sig_1111) or
+		(repeat(32, sig_1014) and or_250) or
+		(repeat(32, sig_941) and or_272) or
+		(repeat(32, sig_921) and or_291) or
+		(repeat(32, sig_901) and or_310) or
+		(repeat(32, sig_990) and or_231) or
+		(repeat(32, sig_825) and or_417) or
+		(repeat(32, sig_805) and or_431) or
+		(repeat(32, sig_757) and or_497);
+
+	-- Behaviour of component 'mux_77' model 'mux'
+	mux_77 <=
+		(repeat(32, sig_1026) and sig_704) or
+		(repeat(32, sig_1012) and or_252) or
+		(repeat(32, sig_939) and or_274) or
+		(repeat(32, sig_919) and or_293) or
+		(repeat(32, sig_899) and or_312) or
+		(repeat(32, sig_986) and or_233) or
+		(repeat(32, sig_806) and or_363) or
+		(repeat(32, sig_783) and or_346) or
+		(repeat(32, sig_743) and or_358);
+
+	-- Behaviour of component 'mux_79' model 'mux'
+	mux_79 <=
+		(repeat(32, sig_1026) and sig_1079) or
+		(repeat(32, sig_1010) and or_256) or
+		(repeat(32, sig_937) and or_278) or
+		(repeat(32, sig_917) and or_297) or
+		(repeat(32, sig_897) and or_316) or
+		(repeat(32, sig_984) and or_237) or
+		(repeat(32, sig_822) and or_421) or
+		(repeat(32, sig_738) and or_333) or
+		(repeat(32, sig_726) and or_326);
+
+	-- Behaviour of component 'mux_81' model 'mux'
+	mux_81 <=
+		(repeat(32, sig_1026) and sig_1103) or
+		(repeat(32, sig_1057) and or_258) or
+		(repeat(32, sig_934) and or_280) or
+		(repeat(32, sig_914) and or_299) or
+		(repeat(32, sig_894) and or_318) or
+		(repeat(32, sig_981) and or_239) or
+		(repeat(32, sig_784) and or_386) or
+		(repeat(32, sig_734) and or_479) or
+		(repeat(32, sig_724) and or_587);
+
+	-- Behaviour of component 'mux_83' model 'mux'
+	mux_83 <=
+		(repeat(32, sig_1026) and sig_1150) or
+		(repeat(32, sig_1055) and or_260) or
+		(repeat(32, sig_932) and or_282) or
+		(repeat(32, sig_912) and or_301) or
+		(repeat(32, sig_892) and or_320) or
+		(repeat(32, sig_979) and or_241) or
+		(repeat(32, sig_820) and or_423) or
+		(repeat(32, sig_811) and or_425) or
+		(repeat(32, sig_722) and or_440);
+
+	-- Behaviour of component 'mux_85' model 'mux'
+	mux_85 <=
+		(repeat(8, sig_1003) and cp_din(63 downto 56)) or
+		(repeat(8, sig_841) and mux_156);
+
+	-- Behaviour of component 'mux_86' model 'mux'
+	mux_86 <=
+		(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
+		(repeat(3, sig_825) and "011") or
+		(repeat(3, sig_822) and "001") or
+		(repeat(3, sig_801) and "101") or
+		(repeat(3, sig_840) and "100") or
+		(repeat(3, sig_783) and "010") or
+		(repeat(3, sig_725) and "111") or
+		(repeat(3, sig_723) and "110");
+
+	-- Behaviour of component 'mux_87' model 'mux'
+	mux_87 <=
+		(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
+		(repeat(3, sig_833) and augh_main_k(5 downto 3));
+
+	-- Behaviour of component 'mux_28' model 'mux'
+	mux_28 <=
+		(sig_873 and cp_en);
+
+	-- Behaviour of component 'mux_109' model 'mux'
+	mux_109 <=
+		(repeat(32, sig_972) and sig_1119) or
+		(repeat(32, sig_836) and sig_677) or
+		(repeat(32, sig_808) and sig_669) or
+		(repeat(32, sig_770) and sig_660) or
+		(repeat(32, sig_754) and sig_645) or
+		(repeat(32, sig_857) and sig_683) or
+		(repeat(32, sig_742) and sig_634) or
+		(repeat(32, sig_737) and sig_624) or
+		(repeat(32, sig_728) and sig_609);
+
+	-- Behaviour of component 'mux_154' model 'mux'
+	mux_154 <=
+		(sig_952 and sig_699);
+
+	-- Behaviour of component 'mux_156' model 'mux'
+	mux_156 <=
+		(repeat(8, sig_1130) and mux_158);
+
+	-- Behaviour of component 'mux_89' model 'mux'
+	mux_89 <=
+		(repeat(8, sig_1003) and cp_din(55 downto 48)) or
+		(repeat(8, sig_816) and mux_156);
+
+	-- Behaviour of component 'mux_90' model 'mux'
+	mux_90 <=
+		(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
+		(repeat(3, sig_806) and "010") or
+		(repeat(3, sig_805) and "011") or
+		(repeat(3, sig_792) and "100") or
+		(repeat(3, sig_786) and "101") or
+		(repeat(3, sig_815) and "111") or
+		(repeat(3, sig_727) and "110") or
+		(repeat(3, sig_726) and "001");
+
+	-- Behaviour of component 'mux_134' model 'mux'
+	mux_134 <=
+		(sig_873 and cp_en) or
+		(sig_832 and '1');
+
+	-- Behaviour of component 'mux_91' model 'mux'
+	mux_91 <=
+		(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
+		(repeat(3, sig_833) and augh_main_k(5 downto 3));
+
+	-- Behaviour of component 'mux_92' model 'mux'
+	mux_92 <=
+		(sig_1004 and and_161) or
+		(sig_814 and '1');
+
+	-- Behaviour of component 'mux_158' model 'mux'
+	mux_158 <=
+		(repeat(8, sig_1157) and "11111111") or
+		(repeat(8, sig_1106) and idct_2d_r(7 downto 0));
+
+	-- Behaviour of component 'mux_111' model 'mux'
+	mux_111 <=
+		(repeat(32, sig_960) and (sig_1132 & '0')) or
+		(repeat(32, sig_770) and (sig_659 & '0')) or
+		(repeat(32, sig_754) and (sig_644 & '0')) or
+		(repeat(32, sig_747) and (sig_640 & '0')) or
+		(repeat(32, sig_742) and (sig_632 & '0')) or
+		(repeat(32, sig_857) and (sig_1076 & '0')) or
+		(repeat(32, sig_740) and (sig_631 & '0')) or
+		(repeat(32, sig_737) and (sig_621 & '0')) or
+		(repeat(32, sig_721) and (sig_606 & '0'));
+
+	-- Behaviour of component 'mux_113' model 'mux'
+	mux_113 <=
+		(repeat(32, sig_989) and (sig_1112 & '0')) or
+		(repeat(32, sig_843) and (sig_678 & '0')) or
+		(repeat(32, sig_826) and (sig_671 & '0')) or
+		(repeat(32, sig_772) and (sig_712 & '0')) or
+		(repeat(32, sig_770) and (sig_661 & '0')) or
+		(repeat(32, sig_857) and (sig_682 & '0')) or
+		(repeat(32, sig_754) and (sig_646 & '0')) or
+		(repeat(32, sig_749) and (sig_641 & '0')) or
+		(repeat(32, sig_742) and (sig_635 & '0')) or
+		(repeat(32, sig_737) and (sig_623 & '0'));
+
+	-- Behaviour of component 'mux_115' model 'mux'
+	mux_115 <=
+		(repeat(32, sig_972) and sig_1142) or
+		(repeat(32, sig_836) and sig_676) or
+		(repeat(32, sig_808) and sig_1063) or
+		(repeat(32, sig_770) and sig_658) or
+		(repeat(32, sig_754) and sig_709) or
+		(repeat(32, sig_857) and sig_681) or
+		(repeat(32, sig_742) and sig_633) or
+		(repeat(32, sig_737) and sig_622) or
+		(repeat(32, sig_728) and sig_610);
+
+	-- Behaviour of component 'mux_117' model 'mux'
+	mux_117 <=
+		(repeat(32, sig_965) and sig_1136) or
+		(repeat(32, sig_843) and sig_1071) or
+		(repeat(32, sig_787) and sig_713) or
+		(repeat(32, sig_770) and sig_710) or
+		(repeat(32, sig_754) and sig_648) or
+		(repeat(32, sig_857) and sig_684) or
+		(repeat(32, sig_742) and sig_636) or
+		(repeat(32, sig_737) and sig_625) or
+		(repeat(32, sig_730) and sig_614);
+
+	-- Behaviour of component 'mux_119' model 'mux'
+	mux_119 <=
+		(repeat(32, sig_963) and sig_1133) or
+		(repeat(32, sig_851) and sig_1073) or
+		(repeat(32, sig_787) and sig_663) or
+		(repeat(32, sig_761) and sig_1061) or
+		(repeat(32, sig_752) and sig_1059) or
+		(repeat(32, sig_867) and sig_1078) or
+		(repeat(32, sig_739) and sig_629) or
+		(repeat(32, sig_735) and sig_619) or
+		(repeat(32, sig_730) and sig_611);
+
+	-- Behaviour of component 'mux_121' model 'mux'
+	mux_121 <=
+		(repeat(32, sig_993) and sig_1131) or
+		(repeat(32, sig_851) and sig_716) or
+		(repeat(32, sig_764) and sig_656) or
+		(repeat(32, sig_762) and sig_654) or
+		(repeat(32, sig_761) and sig_653) or
+		(repeat(32, sig_867) and sig_687) or
+		(repeat(32, sig_752) and sig_1060) or
+		(repeat(32, sig_739) and sig_628) or
+		(repeat(32, sig_735) and sig_618);
+
+	-- Behaviour of component 'mux_123' model 'mux'
+	mux_123 <=
+		(repeat(32, sig_955) and sig_1109) or
+		(repeat(32, sig_843) and sig_679) or
+		(repeat(32, sig_770) and sig_1062) or
+		(repeat(32, sig_764) and sig_657) or
+		(repeat(32, sig_762) and sig_655) or
+		(repeat(32, sig_857) and sig_686) or
+		(repeat(32, sig_754) and sig_647) or
+		(repeat(32, sig_742) and sig_639) or
+		(repeat(32, sig_737) and sig_627);
+
+	-- Behaviour of component 'or_224' model 'or'
+	or_224 <=
+		and_225;
+
+	-- Behaviour of component 'and_225' model 'and'
+	and_225 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_231' model 'or'
+	or_231 <=
+		and_232;
+
+	-- Behaviour of component 'and_232' model 'and'
+	and_232 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_250' model 'or'
+	or_250 <=
+		and_251;
+
+	-- Behaviour of component 'and_251' model 'and'
+	and_251 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_260' model 'or'
+	or_260 <=
+		and_261;
+
+	-- Behaviour of component 'and_261' model 'and'
+	and_261 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_282' model 'or'
+	or_282 <=
+		and_283;
+
+	-- Behaviour of component 'and_283' model 'and'
+	and_283 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_285' model 'or'
+	or_285 <=
+		and_286;
+
+	-- Behaviour of component 'and_286' model 'and'
+	and_286 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_289' model 'or'
+	or_289 <=
+		and_290;
+
+	-- Behaviour of component 'and_290' model 'and'
+	and_290 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_291' model 'or'
+	or_291 <=
+		and_292;
+
+	-- Behaviour of component 'and_292' model 'and'
+	and_292 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_297' model 'or'
+	or_297 <=
+		and_298;
+
+	-- Behaviour of component 'and_298' model 'and'
+	and_298 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_299' model 'or'
+	or_299 <=
+		and_300;
+
+	-- Behaviour of component 'and_300' model 'and'
+	and_300 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_320' model 'or'
+	or_320 <=
+		and_321;
+
+	-- Behaviour of component 'and_321' model 'and'
+	and_321 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_326' model 'or'
+	or_326 <=
+		and_327;
+
+	-- Behaviour of component 'and_327' model 'and'
+	and_327 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_333' model 'or'
+	or_333 <=
+		and_334;
+
+	-- Behaviour of component 'and_334' model 'and'
+	and_334 <=
+		sig_1092;
+
+	-- Behaviour of component 'or_363' model 'or'
+	or_363 <=
+		and_364;
+
+	-- Behaviour of component 'and_364' model 'and'
+	and_364 <=
+		sig_1092;
+
+	-- Behaviour of component 'and_403' model 'and'
+	and_403 <=
+		sig_1158 and
+		repeat(8, sig_1068);
+
+	-- Behaviour of component 'and_405' model 'and'
+	and_405 <=
+		sig_1159 and
+		repeat(8, sig_1067);
+
+	-- Behaviour of component 'and_407' model 'and'
+	and_407 <=
+		sig_1154 and
+		repeat(8, sig_1066);
+
+	-- Behaviour of component 'and_409' model 'and'
+	and_409 <=
+		sig_1153 and
+		repeat(8, sig_1065);
+
+	-- Behaviour of component 'and_415' model 'and'
+	and_415 <=
+		sig_1085(30 downto 0);
+
+	-- Behaviour of component 'or_464' model 'or'
+	or_464 <=
+		and_465;
+
+	-- Behaviour of component 'and_465' model 'and'
+	and_465 <=
+		sig_1095;
+
+	-- Behaviour of component 'or_470' model 'or'
+	or_470 <=
+		and_471;
+
+	-- Behaviour of component 'and_471' model 'and'
+	and_471 <=
+		sig_1085;
+
+	-- Behaviour of component 'or_472' model 'or'
+	or_472 <=
+		and_473;
+
+	-- Behaviour of component 'and_473' model 'and'
+	and_473 <=
+		sig_1083;
+
+	-- Behaviour of component 'or_500' model 'or'
+	or_500 <=
+		and_501;
+
+	-- Behaviour of component 'and_501' model 'and'
+	and_501 <=
+		sig_1094;
+
+	-- Behaviour of component 'or_504' model 'or'
+	or_504 <=
+		and_505;
+
+	-- Behaviour of component 'and_505' model 'and'
+	and_505 <=
+		sig_1092;
+
+	-- Behaviour of component 'or_506' model 'or'
+	or_506 <=
+		and_507;
+
+	-- Behaviour of component 'and_507' model 'and'
+	and_507 <=
+		sig_1095;
+
+	-- Behaviour of component 'or_514' model 'or'
+	or_514 <=
+		and_515;
+
+	-- Behaviour of component 'and_515' model 'and'
+	and_515 <=
+		sig_1083;
+
+	-- Behaviour of component 'or_522' model 'or'
+	or_522 <=
+		and_523;
+
+	-- Behaviour of component 'and_523' model 'and'
+	and_523 <=
+		sig_1094;
+
+	-- Behaviour of component 'mux_129' model 'mux'
+	mux_129 <=
+		(repeat(32, sig_1021) and sig_1114) or
+		(repeat(32, sig_1054) and sig_1100) or
+		(repeat(32, sig_931) and sig_1087) or
+		(repeat(32, sig_911) and sig_694) or
+		(repeat(32, sig_848) and sig_1072) or
+		(repeat(32, sig_978) and sig_1101) or
+		(repeat(32, sig_791) and sig_668) or
+		(repeat(32, sig_732) and sig_617);
+
+	-- Behaviour of component 'mux_133' model 'mux'
+	mux_133 <=
+		(repeat(8, sig_874) and cp_din(39 downto 32)) or
+		(repeat(8, sig_833) and or_394);
+
+	-- Behaviour of component 'mux_135' model 'mux'
+	mux_135 <=
+		(repeat(32, sig_1047) and (repeat(5, sig_1082(19)) & sig_1082 & sig_1155(7 downto 1))) or
+		(repeat(32, sig_1042) and (repeat(5, sig_1127(19)) & sig_1127 & sig_719(7 downto 1))) or
+		(repeat(32, sig_1040) and (repeat(5, sig_1152(19)) & sig_1152 & sig_1118(7 downto 1))) or
+		(repeat(32, sig_1036) and (repeat(5, sig_1126(19)) & sig_1126 & sig_1104(7 downto 1))) or
+		(repeat(32, sig_1035) and (repeat(5, sig_1151(19)) & sig_1151 & sig_718(7 downto 1))) or
+		(repeat(32, sig_822) and (repeat(5, sig_714(19)) & sig_714 & sig_670(7 downto 1))) or
+		(repeat(32, sig_726) and (repeat(5, sig_607(19)) & sig_607 & sig_608(7 downto 1))) or
+		(repeat(32, sig_1044) and (repeat(5, sig_1081(19)) & sig_1081 & sig_720(7 downto 1))) or
+		(repeat(32, sig_1034) and (repeat(5, sig_1080(19)) & sig_1080 & sig_1117(7 downto 1))) or
+		(repeat(32, sig_917) and (repeat(5, sig_695(19)) & sig_695 & sig_696(7 downto 1))) or
+		(repeat(32, sig_897) and (repeat(5, sig_693(19)) & sig_693 & sig_1107(7 downto 1))) or
+		(repeat(32, sig_1033) and (repeat(5, sig_1125(19)) & sig_1125 & sig_1116(7 downto 1))) or
+		(repeat(32, sig_984) and (repeat(5, sig_700(19)) & sig_700 & sig_1108(7 downto 1))) or
+		(repeat(32, sig_1010) and (repeat(5, sig_717(19)) & sig_717 & sig_1089(7 downto 1))) or
+		(repeat(32, sig_937) and (repeat(5, sig_697(19)) & sig_697 & sig_1088(7 downto 1)));
+
+	-- Behaviour of component 'mux_137' model 'mux'
+	mux_137 <=
+		(repeat(8, sig_1003) and cp_din(39 downto 32)) or
+		(repeat(8, sig_930) and mux_156);
+
+	-- Behaviour of component 'mux_138' model 'mux'
+	mux_138 <=
+		(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
+		(repeat(3, sig_927) and "110") or
+		(repeat(3, sig_925) and "101") or
+		(repeat(3, sig_923) and "100") or
+		(repeat(3, sig_921) and "011") or
+		(repeat(3, sig_929) and "111") or
+		(repeat(3, sig_919) and "010") or
+		(repeat(3, sig_917) and "001");
+
+	-- Behaviour of component 'mux_139' model 'mux'
+	mux_139 <=
+		(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
+		(repeat(3, sig_833) and augh_main_k(5 downto 3));
+
+	-- Behaviour of component 'mux_140' model 'mux'
+	mux_140 <=
+		(sig_1004 and and_161) or
+		(sig_928 and '1');
+
+	-- Behaviour of component 'mux_141' model 'mux'
+	mux_141 <=
+		(repeat(8, sig_1003) and cp_din(47 downto 40)) or
+		(repeat(8, sig_910) and mux_156);
+
+	-- Behaviour of component 'mux_142' model 'mux'
+	mux_142 <=
+		(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
+		(repeat(3, sig_907) and "110") or
+		(repeat(3, sig_905) and "101") or
+		(repeat(3, sig_903) and "100") or
+		(repeat(3, sig_901) and "011") or
+		(repeat(3, sig_909) and "111") or
+		(repeat(3, sig_899) and "010") or
+		(repeat(3, sig_897) and "001");
+
+	-- Behaviour of component 'mux_143' model 'mux'
+	mux_143 <=
+		(repeat(3, sig_1003) and psc_loop_reg_13(2 downto 0)) or
+		(repeat(3, sig_833) and augh_main_k(5 downto 3));
+
+	-- Behaviour of component 'mux_144' model 'mux'
+	mux_144 <=
+		(sig_1004 and and_161) or
+		(sig_908 and '1');
+
+	-- Behaviour of component 'mux_147' model 'mux'
+	mux_147 <=
+		(sig_951 and not_264);
+
+	-- Behaviour of component 'mux_149' model 'mux'
+	mux_149 <=
+		(repeat(32, sig_874) and cp_din(31 downto 0)) or
+		(repeat(32, sig_835) and sig_675);
+
+	-- Behaviour of component 'mux_150' model 'mux'
+	mux_150 <=
+		(sig_873 and cp_en) or
+		(sig_834 and '1');
+
+	-- Behaviour of component 'mux_151' model 'mux'
+	mux_151 <=
+		(sig_1005 and sig_705) or
+		(sig_1003 and sig_703) or
+		(sig_874 and sig_692) or
+		(sig_1050 and '1');
+
+	-- Behaviour of component 'mux_152' model 'mux'
+	mux_152 <=
+		(repeat(64, sig_1005) and (sig_1093 & sig_1084)) or
+		(repeat(64, sig_874) and (psc_stuff_reg_19 & cp_id_reg_14)) or
+		(repeat(64, sig_1003) and (sig_1153 & sig_1154 & sig_1159 & sig_1158 & sig_1099 & sig_1098 & sig_1097 & sig_1096));
+
+	-- Behaviour of component 'mux_155' model 'mux'
+	mux_155 <=
+		(sig_951 and sig_698);
+
+	-- Behaviour of component 'or_221' model 'or'
+	or_221 <=
+		and_222;
+
+	-- Behaviour of component 'and_222' model 'and'
+	and_222 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_233' model 'or'
+	or_233 <=
+		and_234;
+
+	-- Behaviour of component 'and_234' model 'and'
+	and_234 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_237' model 'or'
+	or_237 <=
+		and_238;
+
+	-- Behaviour of component 'and_238' model 'and'
+	and_238 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_252' model 'or'
+	or_252 <=
+		and_253;
+
+	-- Behaviour of component 'and_253' model 'and'
+	and_253 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_256' model 'or'
+	or_256 <=
+		and_257;
+
+	-- Behaviour of component 'and_257' model 'and'
+	and_257 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_268' model 'or'
+	or_268 <=
+		and_269;
+
+	-- Behaviour of component 'and_269' model 'and'
+	and_269 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_270' model 'or'
+	or_270 <=
+		and_271;
+
+	-- Behaviour of component 'and_271' model 'and'
+	and_271 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_274' model 'or'
+	or_274 <=
+		and_275;
+
+	-- Behaviour of component 'and_275' model 'and'
+	and_275 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_278' model 'or'
+	or_278 <=
+		and_279;
+
+	-- Behaviour of component 'and_279' model 'and'
+	and_279 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_310' model 'or'
+	or_310 <=
+		and_311;
+
+	-- Behaviour of component 'and_311' model 'and'
+	and_311 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_316' model 'or'
+	or_316 <=
+		and_317;
+
+	-- Behaviour of component 'and_317' model 'and'
+	and_317 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_358' model 'or'
+	or_358 <=
+		and_359;
+
+	-- Behaviour of component 'and_359' model 'and'
+	and_359 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_366' model 'or'
+	or_366 <=
+		and_367;
+
+	-- Behaviour of component 'and_367' model 'and'
+	and_367 <=
+		sig_1095;
+
+	-- Behaviour of component 'or_374' model 'or'
+	or_374 <=
+		and_375;
+
+	-- Behaviour of component 'and_375' model 'and'
+	and_375 <=
+		sig_1094;
+
+	-- Behaviour of component 'or_417' model 'or'
+	or_417 <=
+		and_418;
+
+	-- Behaviour of component 'and_418' model 'and'
+	and_418 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_421' model 'or'
+	or_421 <=
+		and_422;
+
+	-- Behaviour of component 'and_422' model 'and'
+	and_422 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_435' model 'or'
+	or_435 <=
+		and_436;
+
+	-- Behaviour of component 'and_436' model 'and'
+	and_436 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_452' model 'or'
+	or_452 <=
+		and_453;
+
+	-- Behaviour of component 'and_453' model 'and'
+	and_453 <=
+		sig_1093;
+
+	-- Behaviour of component 'and_494' model 'and'
+	and_494 <=
+		sig_1095;
+
+	-- Behaviour of component 'and_498' model 'and'
+	and_498 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_509' model 'or'
+	or_509 <=
+		and_510;
+
+	-- Behaviour of component 'and_510' model 'and'
+	and_510 <=
+		sig_1084(30 downto 0);
+
+	-- Behaviour of component 'or_550' model 'or'
+	or_550 <=
+		and_551;
+
+	-- Behaviour of component 'and_551' model 'and'
+	and_551 <=
+		sig_1083;
+
+	-- Behaviour of component 'or_581' model 'or'
+	or_581 <=
+		and_582;
+
+	-- Behaviour of component 'and_582' model 'and'
+	and_582 <=
+		sig_1094;
+
+	-- Behaviour of component 'or_583' model 'or'
+	or_583 <=
+		and_584;
+
+	-- Behaviour of component 'and_584' model 'and'
+	and_584 <=
+		sig_1092;
+
+	-- Behaviour of component 'or_587' model 'or'
+	or_587 <=
+		and_588;
+
+	-- Behaviour of component 'and_588' model 'and'
+	and_588 <=
+		sig_1093;
+
+	-- Behaviour of component 'and_161' model 'and'
+	and_161 <=
+		cp_en and
+		cp_rest;
+
+	-- Behaviour of component 'or_228' model 'or'
+	or_228 <=
+		and_229;
+
+	-- Behaviour of component 'and_229' model 'and'
+	and_229 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_239' model 'or'
+	or_239 <=
+		and_240;
+
+	-- Behaviour of component 'and_240' model 'and'
+	and_240 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_241' model 'or'
+	or_241 <=
+		and_242;
+
+	-- Behaviour of component 'and_242' model 'and'
+	and_242 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_244' model 'or'
+	or_244 <=
+		and_245;
+
+	-- Behaviour of component 'and_245' model 'and'
+	and_245 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_246' model 'or'
+	or_246 <=
+		and_247;
+
+	-- Behaviour of component 'and_247' model 'and'
+	and_247 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_248' model 'or'
+	or_248 <=
+		and_249;
+
+	-- Behaviour of component 'and_249' model 'and'
+	and_249 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_258' model 'or'
+	or_258 <=
+		and_259;
+
+	-- Behaviour of component 'and_259' model 'and'
+	and_259 <=
+		sig_1093;
+
+	-- Behaviour of component 'not_264' model 'not'
+	not_264 <= not (
+		cp_en
+	);
+
+	-- Behaviour of component 'or_266' model 'or'
+	or_266 <=
+		and_267;
+
+	-- Behaviour of component 'and_267' model 'and'
+	and_267 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_272' model 'or'
+	or_272 <=
+		and_273;
+
+	-- Behaviour of component 'and_273' model 'and'
+	and_273 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_280' model 'or'
+	or_280 <=
+		and_281;
+
+	-- Behaviour of component 'and_281' model 'and'
+	and_281 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_287' model 'or'
+	or_287 <=
+		and_288;
+
+	-- Behaviour of component 'and_288' model 'and'
+	and_288 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_293' model 'or'
+	or_293 <=
+		and_294;
+
+	-- Behaviour of component 'and_294' model 'and'
+	and_294 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_301' model 'or'
+	or_301 <=
+		and_302;
+
+	-- Behaviour of component 'and_302' model 'and'
+	and_302 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_304' model 'or'
+	or_304 <=
+		and_305;
+
+	-- Behaviour of component 'and_305' model 'and'
+	and_305 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_306' model 'or'
+	or_306 <=
+		and_307;
+
+	-- Behaviour of component 'and_307' model 'and'
+	and_307 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_308' model 'or'
+	or_308 <=
+		and_309;
+
+	-- Behaviour of component 'and_309' model 'and'
+	and_309 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_312' model 'or'
+	or_312 <=
+		and_313;
+
+	-- Behaviour of component 'and_313' model 'and'
+	and_313 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_318' model 'or'
+	or_318 <=
+		and_319;
+
+	-- Behaviour of component 'and_319' model 'and'
+	and_319 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_329' model 'or'
+	or_329 <=
+		and_330;
+
+	-- Behaviour of component 'and_330' model 'and'
+	and_330 <=
+		sig_1094;
+
+	-- Behaviour of component 'or_335' model 'or'
+	or_335 <=
+		and_336;
+
+	-- Behaviour of component 'and_336' model 'and'
+	and_336 <=
+		sig_1095;
+
+	-- Behaviour of component 'or_339' model 'or'
+	or_339 <=
+		and_340;
+
+	-- Behaviour of component 'and_340' model 'and'
+	and_340 <=
+		sig_1094;
+
+	-- Behaviour of component 'or_342' model 'or'
+	or_342 <=
+		and_343;
+
+	-- Behaviour of component 'and_343' model 'and'
+	and_343 <=
+		sig_1095;
+
+	-- Behaviour of component 'or_346' model 'or'
+	or_346 <=
+		and_347;
+
+	-- Behaviour of component 'and_347' model 'and'
+	and_347 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_348' model 'or'
+	or_348 <=
+		and_349;
+
+	-- Behaviour of component 'and_349' model 'and'
+	and_349 <=
+		sig_1085;
+
+	-- Behaviour of component 'or_351' model 'or'
+	or_351 <=
+		and_352;
+
+	-- Behaviour of component 'and_352' model 'and'
+	and_352 <=
+		sig_1083(30 downto 0);
+
+	-- Behaviour of component 'or_355' model 'or'
+	or_355 <=
+		and_356;
+
+	-- Behaviour of component 'and_356' model 'and'
+	and_356 <=
+		sig_1086(30 downto 0);
+
+	-- Behaviour of component 'or_360' model 'or'
+	or_360 <=
+		and_361;
+
+	-- Behaviour of component 'and_361' model 'and'
+	and_361 <=
+		sig_1094;
+
+	-- Behaviour of component 'or_371' model 'or'
+	or_371 <=
+		and_372;
+
+	-- Behaviour of component 'and_372' model 'and'
+	and_372 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_378' model 'or'
+	or_378 <=
+		and_379;
+
+	-- Behaviour of component 'and_379' model 'and'
+	and_379 <=
+		sig_1092;
+
+	-- Behaviour of component 'or_380' model 'or'
+	or_380 <=
+		and_381;
+
+	-- Behaviour of component 'and_381' model 'and'
+	and_381 <=
+		sig_1095;
+
+	-- Behaviour of component 'or_384' model 'or'
+	or_384 <=
+		and_385;
+
+	-- Behaviour of component 'and_385' model 'and'
+	and_385 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_386' model 'or'
+	or_386 <=
+		and_387;
+
+	-- Behaviour of component 'and_387' model 'and'
+	and_387 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_388' model 'or'
+	or_388 <=
+		and_389;
+
+	-- Behaviour of component 'and_389' model 'and'
+	and_389 <=
+		sig_1085;
+
+	-- Behaviour of component 'or_394' model 'or'
+	or_394 <=
+		and_395 or
+		and_399 or
+		and_401 or
+		and_403 or
+		and_405 or
+		and_397 or
+		and_407 or
+		and_409;
+
+	-- Behaviour of component 'and_395' model 'and'
+	and_395 <=
+		sig_1096 and
+		repeat(8, sig_674);
+
+	-- Behaviour of component 'and_397' model 'and'
+	and_397 <=
+		sig_1097 and
+		repeat(8, sig_1070);
+
+	-- Behaviour of component 'and_399' model 'and'
+	and_399 <=
+		sig_1098 and
+		repeat(8, sig_1069);
+
+	-- Behaviour of component 'and_401' model 'and'
+	and_401 <=
+		sig_1099 and
+		repeat(8, sig_673);
+
+	-- Behaviour of component 'or_414' model 'or'
+	or_414 <=
+		and_415;
+
+	-- Behaviour of component 'or_423' model 'or'
+	or_423 <=
+		and_424;
+
+	-- Behaviour of component 'and_424' model 'and'
+	and_424 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_425' model 'or'
+	or_425 <=
+		and_426;
+
+	-- Behaviour of component 'and_426' model 'and'
+	and_426 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_427' model 'or'
+	or_427 <=
+		and_428;
+
+	-- Behaviour of component 'and_428' model 'and'
+	and_428 <=
+		sig_1085;
+
+	-- Behaviour of component 'or_431' model 'or'
+	or_431 <=
+		and_432;
+
+	-- Behaviour of component 'and_432' model 'and'
+	and_432 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_433' model 'or'
+	or_433 <=
+		and_434;
+
+	-- Behaviour of component 'and_434' model 'and'
+	and_434 <=
+		sig_1084;
+
+	-- Behaviour of component 'or_438' model 'or'
+	or_438 <=
+		and_439;
+
+	-- Behaviour of component 'and_439' model 'and'
+	and_439 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_440' model 'or'
+	or_440 <=
+		and_441;
+
+	-- Behaviour of component 'and_441' model 'and'
+	and_441 <=
+		sig_1094;
+
+	-- Behaviour of component 'or_443' model 'or'
+	or_443 <=
+		and_444;
+
+	-- Behaviour of component 'and_444' model 'and'
+	and_444 <=
+		sig_1092;
+
+	-- Behaviour of component 'or_450' model 'or'
+	or_450 <=
+		and_451;
+
+	-- Behaviour of component 'and_451' model 'and'
+	and_451 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_454' model 'or'
+	or_454 <=
+		and_455;
+
+	-- Behaviour of component 'and_455' model 'and'
+	and_455 <=
+		sig_1084(30 downto 0);
+
+	-- Behaviour of component 'or_458' model 'or'
+	or_458 <=
+		and_459;
+
+	-- Behaviour of component 'and_459' model 'and'
+	and_459 <=
+		sig_1094;
+
+	-- Behaviour of component 'or_462' model 'or'
+	or_462 <=
+		and_463;
+
+	-- Behaviour of component 'and_463' model 'and'
+	and_463 <=
+		sig_1092;
+
+	-- Behaviour of component 'or_467' model 'or'
+	or_467 <=
+		and_468;
+
+	-- Behaviour of component 'and_468' model 'and'
+	and_468 <=
+		sig_1084(30 downto 0);
+
+	-- Behaviour of component 'or_475' model 'or'
+	or_475 <=
+		and_476;
+
+	-- Behaviour of component 'and_476' model 'and'
+	and_476 <=
+		sig_1086(30 downto 0);
+
+	-- Behaviour of component 'or_479' model 'or'
+	or_479 <=
+		and_480;
+
+	-- Behaviour of component 'and_480' model 'and'
+	and_480 <=
+		sig_1093;
+
+	-- Behaviour of component 'or_481' model 'or'
+	or_481 <=
+		and_482;
+
+	-- Behaviour of component 'and_482' model 'and'
+	and_482 <=
+		sig_1094;
+
+	-- Behaviour of component 'or_485' model 'or'
+	or_485 <=
+		and_486;
+
+	-- Behaviour of component 'and_486' model 'and'
+	and_486 <=
+		sig_1094;
+
+	-- Behaviour of component 'or_490' model 'or'
+	or_490 <=
+		and_491;
+
+	-- Behaviour of component 'and_491' model 'and'
+	and_491 <=
+		sig_1094;
+
+	-- Behaviour of component 'or_493' model 'or'
+	or_493 <=
+		and_494;
+
+	-- Behaviour of component 'or_497' model 'or'
+	or_497 <=
+		and_498;
+
+	-- Behaviour of component 'or_512' model 'or'
+	or_512 <=
+		and_513;
+
+	-- Behaviour of component 'and_513' model 'and'
+	and_513 <=
+		sig_1085;
+
+	-- Behaviour of component 'or_518' model 'or'
+	or_518 <=
+		and_519;
+
+	-- Behaviour of component 'and_519' model 'and'
+	and_519 <=
+		sig_1086(30 downto 0);
+
+	-- Behaviour of component 'or_525' model 'or'
+	or_525 <=
+		and_526;
+
+	-- Behaviour of component 'and_526' model 'and'
+	and_526 <=
+		sig_1092;
+
+	-- Behaviour of component 'or_529' model 'or'
+	or_529 <=
+		and_530;
+
+	-- Behaviour of component 'and_530' model 'and'
+	and_530 <=
+		sig_1085(30 downto 0);
+
+	-- Behaviour of component 'or_532' model 'or'
+	or_532 <=
+		and_533;
+
+	-- Behaviour of component 'and_533' model 'and'
+	and_533 <=
+		sig_1085(30 downto 0);
+
+	-- Behaviour of component 'or_535' model 'or'
+	or_535 <=
+		and_536;
+
+	-- Behaviour of component 'and_536' model 'and'
+	and_536 <=
+		sig_1094;
+
+	-- Behaviour of component 'or_538' model 'or'
+	or_538 <=
+		and_539;
+
+	-- Behaviour of component 'and_539' model 'and'
+	and_539 <=
+		sig_1092;
+
+	-- Behaviour of component 'or_541' model 'or'
+	or_541 <=
+		and_542;
+
+	-- Behaviour of component 'and_542' model 'and'
+	and_542 <=
+		sig_1095;
+
+	-- Behaviour of component 'or_545' model 'or'
+	or_545 <=
+		and_546;
+
+	-- Behaviour of component 'and_546' model 'and'
+	and_546 <=
+		sig_1084(30 downto 0);
+
+	-- Behaviour of component 'or_548' model 'or'
+	or_548 <=
+		and_549;
+
+	-- Behaviour of component 'and_549' model 'and'
+	and_549 <=
+		sig_1085;
+
+	-- Behaviour of component 'or_554' model 'or'
+	or_554 <=
+		and_555;
+
+	-- Behaviour of component 'and_555' model 'and'
+	and_555 <=
+		sig_1086(30 downto 0);
+
+	-- Behaviour of component 'or_557' model 'or'
+	or_557 <=
+		and_558;
+
+	-- Behaviour of component 'and_558' model 'and'
+	and_558 <=
+		sig_1085(30 downto 0);
+
+	-- Behaviour of component 'or_568' model 'or'
+	or_568 <=
+		and_569;
+
+	-- Behaviour of component 'and_569' model 'and'
+	and_569 <=
+		sig_1085;
+
+	-- Behaviour of component 'or_571' model 'or'
+	or_571 <=
+		and_572;
+
+	-- Behaviour of component 'and_572' model 'and'
+	and_572 <=
+		sig_1083(30 downto 0);
+
+	-- Behaviour of component 'or_575' model 'or'
+	or_575 <=
+		and_576;
+
+	-- Behaviour of component 'and_576' model 'and'
+	and_576 <=
+		sig_1086(30 downto 0);
+
+	-- Behaviour of component 'or_590' model 'or'
+	or_590 <=
+		and_591;
+
+	-- Behaviour of component 'and_591' model 'and'
+	and_591 <=
+		sig_1094;
+
+	-- Behaviour of component 'or_597' model 'or'
+	or_597 <=
+		and_598;
+
+	-- Behaviour of component 'and_598' model 'and'
+	and_598 <=
+		sig_1085;
+
+	-- Behaviour of component 'or_603' model 'or'
+	or_603 <=
+		and_604;
+
+	-- Behaviour of component 'and_604' model 'and'
+	and_604 <=
+		sig_1084(30 downto 0);
+
+	-- Behaviour of all components of model 'reg'
+	-- Registers with clock = sig_clock and reset = sig_reset active '1'
+	process(sig_clock, sig_reset)
+	begin
+		if sig_reset = '1' then
+			psc_stuff_reg_19 <= "000000000000000000000000000000000000000000000000000000000000000";
+		else
+			if rising_edge(sig_clock) then
+				if mux_28 = '1' then
+					psc_stuff_reg_19 <= psc_stuff_reg_18 & write8_u8 & augh_main_k(31 downto 1);
+				end if;
+			end if;
+		end if;
+	end process;
+	-- Registers with clock = sig_clock and no reset
+	process(sig_clock)
+	begin
+		if rising_edge(sig_clock) then
+			if mux_30 = '1' then
+				psc_stuff_reg_18 <= cp_din(63 downto 40);
+			end if;
+			if mux_34 = '1' then
+				cp_id_reg_stable_15 <= mux_33;
+			end if;
+			if mux_36 = '1' then
+				cp_id_reg_14 <= mux_35;
+			end if;
+			if mux_38 = '1' then
+				psc_loop_reg_13 <= mux_37;
+			end if;
+			if sig_1024 = '1' then
+				idct_2d_yc_reg7 <= mux_69;
+			end if;
+			if sig_1025 = '1' then
+				idct_2d_yc_reg6 <= mux_71;
+			end if;
+			if sig_1027 = '1' then
+				idct_2d_yc_reg5 <= mux_73;
+			end if;
+			if sig_1028 = '1' then
+				idct_2d_yc_reg4 <= mux_75;
+			end if;
+			if sig_1029 = '1' then
+				idct_2d_yc_reg3 <= mux_77;
+			end if;
+			if sig_1030 = '1' then
+				idct_2d_yc_reg2 <= mux_79;
+			end if;
+			if sig_1031 = '1' then
+				idct_2d_yc_reg1 <= mux_81;
+			end if;
+			if sig_1032 = '1' then
+				idct_2d_yc_reg0 <= mux_83;
+			end if;
+			if sig_1001 = '1' then
+				idct_z2_reg7 <= sig_1090;
+			end if;
+			if sig_998 = '1' then
+				idct_z2_reg6 <= sig_701;
+			end if;
+			if sig_999 = '1' then
+				idct_z2_reg5 <= sig_1113;
+			end if;
+			if sig_1000 = '1' then
+				idct_z2_reg4 <= sig_1120;
+			end if;
+			if sig_967 = '1' then
+				idct_z2_reg3 <= sig_1139;
+			end if;
+			if sig_968 = '1' then
+				idct_z2_reg2 <= sig_1140;
+			end if;
+			if sig_969 = '1' then
+				idct_z2_reg1 <= sig_1141;
+			end if;
+			if sig_970 = '1' then
+				idct_z2_reg0 <= sig_1110;
+			end if;
+			if sig_971 = '1' then
+				idct_z1_reg7 <= mux_109;
+			end if;
+			if sig_959 = '1' then
+				idct_z1_reg6 <= mux_111;
+			end if;
+			if sig_988 = '1' then
+				idct_z1_reg5 <= mux_113;
+			end if;
+			if sig_971 = '1' then
+				idct_z1_reg4 <= mux_115;
+			end if;
+			if sig_964 = '1' then
+				idct_z1_reg3 <= mux_117;
+			end if;
+			if sig_962 = '1' then
+				idct_z1_reg2 <= mux_119;
+			end if;
+			if sig_992 = '1' then
+				idct_z1_reg1 <= mux_121;
+			end if;
+			if sig_994 = '1' then
+				idct_z1_reg0 <= mux_123;
+			end if;
+			if sig_1023 = '1' then
+				idct_z3_reg7 <= sig_1147 & idct_z2_reg7(0);
+			end if;
+			if sig_1022 = '1' then
+				idct_z3_reg6 <= sig_1091 & idct_z2_reg6(1 downto 0);
+			end if;
+			if sig_1020 = '1' then
+				idct_z3_reg5 <= mux_129;
+			end if;
+			if sig_1019 = '1' then
+				idct_z3_reg4 <= sig_1121;
+			end if;
+			if mux_134 = '1' then
+				write8_u8 <= mux_133;
+			end if;
+			if sig_1046 = '1' then
+				idct_2d_r <= mux_135;
+			end if;
+			if mux_147 = '1' then
+				read32_ret0_10 <= stdin_data;
+			end if;
+			if mux_150 = '1' then
+				augh_main_k <= mux_149;
+			end if;
+		end if;
+	end process;
+
+	-- Remaining signal assignments
+	-- Those who are not assigned by component instantiation
+
+	sig_clock <= clock;
+	sig_reset <= reset;
+	sig_start <= start;
+	test_cp_0_16 <= mux_32;
+	sig_1160 <= sig_608(26) & sig_608(26 downto 8);
+	sig_1161 <= sig_1122 & "00";
+	sig_1162 <= sig_1122 & "00";
+	sig_1163 <= sig_1107(26) & sig_1107(26 downto 8);
+	sig_1164 <= sig_1122 & "00";
+	sig_1165 <= sig_696(26) & sig_696(26 downto 8);
+	sig_1166 <= sig_1088(26) & sig_1088(26 downto 8);
+	sig_1167 <= sig_1108(26) & sig_1108(26 downto 8);
+	sig_1168 <= sig_670(26) & sig_670(26 downto 8);
+	sig_1169 <= sig_1089(26) & sig_1089(26 downto 8);
+	sig_1170 <= sig_1122 & "00";
+	sig_1171 <= sig_1117(26) & sig_1117(26 downto 8);
+	sig_1172 <= sig_720(26) & sig_720(26 downto 8);
+	sig_1173 <= sig_1155(26) & sig_1155(26 downto 8);
+	sig_1174 <= sig_1122 & "00";
+	sig_1175 <= sig_1122 & "00";
+	sig_1176 <= sig_1122 & "00";
+	sig_1177 <= sig_1122 & "00";
+	sig_1178 <= sig_1143 & '0';
+	sig_1179 <= sig_1116(26) & sig_1116(26 downto 8);
+	sig_1180 <= sig_1104(26) & sig_1104(26 downto 8);
+	sig_1181 <= sig_719(26) & sig_719(26 downto 8);
+	sig_1182 <= sig_718(26) & sig_718(26 downto 8);
+	sig_1183 <= sig_1118(26) & sig_1118(26 downto 8);
+
+	-- Remaining top-level ports assignments
+	-- Those who are not assigned by component instantiation
+
+	cp_ok <= mux_151;
+	cp_dout <= mux_152;
+	stdout_data <= write8_u8;
+	stdout_rdy <= mux_154;
+	stdin_rdy <= mux_155;
+
+end architecture;
diff --git a/testsuite/gna/issue50/testsuite.sh b/testsuite/gna/issue50/testsuite.sh
new file mode 100755
index 000000000..ad042ea61
--- /dev/null
+++ b/testsuite/gna/issue50/testsuite.sh
@@ -0,0 +1,106 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+files="
+pkg_tb.vhd
+add_118.vhd
+add_134.vhd
+add_170.vhd
+add_171.vhd
+add_188.vhd
+add_214.vhd
+add_220.vhd
+assert_uut.vhd
+cmp_111.vhd
+cmp_112.vhd
+cmp_113.vhd
+cmp_114.vhd
+cmp_115.vhd
+cmp_119.vhd
+cmp_126.vhd
+cmp_127.vhd
+cmp_128.vhd
+cmp_129.vhd
+cmp_130.vhd
+cmp_131.vhd
+cmp_132.vhd
+cmp_133.vhd
+cmp_135.vhd
+cmp_136.vhd
+cmp_137.vhd
+cmp_138.vhd
+cmp_139.vhd
+cmp_140.vhd
+cmp_141.vhd
+cmp_142.vhd
+cmp_146.vhd
+cmp_148.vhd
+cmp_150.vhd
+cmp_152.vhd
+cmp_154.vhd
+cmp_156.vhd
+cmp_158.vhd
+cmp_160.vhd
+cmp_174.vhd
+cmp_176.vhd
+cmp_178.vhd
+cmp_180.vhd
+cmp_183.vhd
+cmp_185.vhd
+cmp_187.vhd
+cmp_191.vhd
+cmp_193.vhd
+cmp_195.vhd
+cmp_198.vhd
+cmp_200.vhd
+cmp_202.vhd
+cmp_204.vhd
+cmp_215.vhd
+cmp_216.vhd
+cmp_217.vhd
+cmp_218.vhd
+cmp_221.vhd
+fsm.vhd
+fsm_15.vhd
+muxb_117.vhd
+muxb_120.vhd
+muxb_121.vhd
+muxb_123.vhd
+muxb_124.vhd
+muxb_219.vhd
+prog.vhd
+sub_125.vhd
+sub_145.vhd
+sub_189.vhd
+sync_ram.vhd
+v_split0.vhd
+v_split1.vhd
+v_split2.vhd
+v_split3.vhd
+v_split4.vhd
+v_split5.vhd
+v_split6.vhd
+v_split7.vhd
+w_split0.vhd
+w_split1.vhd
+w_split2.vhd
+w_split3.vhd
+w_split4.vhd
+w_split5.vhd
+w_split6.vhd
+w_split7.vhd
+top.vhd
+cp3_test.vhd
+tb.vhd
+"
+
+for f in $files; do
+  analyze vector.d/$f
+done
+
+elab_simulate tb
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue50/vector.d/add_118.vhd b/testsuite/gna/issue50/vector.d/add_118.vhd
new file mode 100644
index 000000000..9134bc04d
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/add_118.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_118 is
+	port (
+		result : out std_logic_vector(15 downto 0);
+		in_a : in  std_logic_vector(15 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end add_118;
+
+architecture augh of add_118 is
+
+	signal carry_inA : std_logic_vector(17 downto 0);
+	signal carry_inB : std_logic_vector(17 downto 0);
+	signal carry_res : std_logic_vector(17 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(16 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/add_134.vhd b/testsuite/gna/issue50/vector.d/add_134.vhd
new file mode 100644
index 000000000..4f33da61f
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/add_134.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_134 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_134;
+
+architecture augh of add_134 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/add_170.vhd b/testsuite/gna/issue50/vector.d/add_170.vhd
new file mode 100644
index 000000000..dc7f53489
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/add_170.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_170 is
+	port (
+		result : out std_logic_vector(8 downto 0);
+		in_a : in  std_logic_vector(8 downto 0);
+		in_b : in  std_logic_vector(8 downto 0)
+	);
+end add_170;
+
+architecture augh of add_170 is
+
+	signal carry_inA : std_logic_vector(10 downto 0);
+	signal carry_inB : std_logic_vector(10 downto 0);
+	signal carry_res : std_logic_vector(10 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(9 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/add_171.vhd b/testsuite/gna/issue50/vector.d/add_171.vhd
new file mode 100644
index 000000000..82b3708ec
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/add_171.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_171 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_171;
+
+architecture augh of add_171 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/add_188.vhd b/testsuite/gna/issue50/vector.d/add_188.vhd
new file mode 100644
index 000000000..4bb414f53
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/add_188.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_188 is
+	port (
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end add_188;
+
+architecture augh of add_188 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/add_214.vhd b/testsuite/gna/issue50/vector.d/add_214.vhd
new file mode 100644
index 000000000..97020f26b
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/add_214.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_214 is
+	port (
+		result : out std_logic_vector(7 downto 0);
+		in_a : in  std_logic_vector(7 downto 0);
+		in_b : in  std_logic_vector(7 downto 0)
+	);
+end add_214;
+
+architecture augh of add_214 is
+
+	signal carry_inA : std_logic_vector(9 downto 0);
+	signal carry_inB : std_logic_vector(9 downto 0);
+	signal carry_res : std_logic_vector(9 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(8 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/add_220.vhd b/testsuite/gna/issue50/vector.d/add_220.vhd
new file mode 100644
index 000000000..b527a5d81
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/add_220.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_220 is
+	port (
+		result : out std_logic_vector(15 downto 0);
+		in_a : in  std_logic_vector(15 downto 0);
+		in_b : in  std_logic_vector(15 downto 0)
+	);
+end add_220;
+
+architecture augh of add_220 is
+
+	signal carry_inA : std_logic_vector(17 downto 0);
+	signal carry_inB : std_logic_vector(17 downto 0);
+	signal carry_res : std_logic_vector(17 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(16 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/assert_uut.vhd b/testsuite/gna/issue50/vector.d/assert_uut.vhd
new file mode 100644
index 000000000..b097652a9
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/assert_uut.vhd
@@ -0,0 +1,169 @@
+--test bench written by Alban Bourge @ TIMA
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+library work;
+use work.pkg_tb.all;
+
+entity assert_uut is
+	port(
+				clock        : in std_logic;
+				reset        : in std_logic;
+				context_uut  : in context_t;
+				en_feed      : in std_logic;
+				stdin_rdy    : in std_logic;
+				stdin_ack    : out std_logic;
+				stdin_data   : out stdin_vector;
+				en_check     : in std_logic;
+				stdout_rdy   : in std_logic;
+				stdout_ack   : out std_logic;
+				stdout_data  : in stdout_vector;
+				vecs_found   : out std_logic;
+				vec_read     : out std_logic;
+				n_error      : out std_logic
+			);
+end assert_uut;
+
+architecture rtl of assert_uut is
+
+	type vin_table  is array(0 to 2**VEC_NO_SIZE - 1) of stdin_vector;
+	type vout_table is array(0 to 2**VEC_NO_SIZE - 1) of stdout_vector;
+	constant input_vectors_1 : vin_table := (
+		--##INPUT_VECTORS_1_GO_DOWN_HERE##--
+		0 => x"00_00_00_07",
+		1 => x"00_00_00_03",
+		--##INPUT_VECTORS_1_GO_OVER_HERE##--
+		others => (others => '0'));
+	constant output_vectors_1 : vout_table := (
+		--##OUTPUT_VECTORS_1_GO_DOWN_HERE##--
+		0 => x"00_00_00_16",
+		--##OUTPUT_VECTORS_1_GO_OVER_HERE##--
+		others => (others => '0'));
+	constant input_vectors_2 : vin_table := (
+		--##INPUT_VECTORS_2_GO_DOWN_HERE##--
+		0 => x"00_00_00_07",
+		1 => x"00_00_00_03",
+		--##INPUT_VECTORS_2_GO_OVER_HERE##--
+		others => (others => '0'));
+	constant output_vectors_2 : vout_table := (
+		--##OUTPUT_VECTORS_2_GO_DOWN_HERE##--
+		0 => x"00_00_00_16",
+		--##OUTPUT_VECTORS_2_GO_OVER_HERE##--
+		others => (others => '0'));
+
+	signal out_vec_counter_1 : unsigned(VEC_NO_SIZE - 1 downto 0);
+	signal out_vec_counter_2 : unsigned(VEC_NO_SIZE - 1 downto 0);
+	signal stdin_ack_sig  : std_logic;
+	signal vector_read    : std_logic;
+
+begin
+
+	feed : process(reset, clock) is
+	variable in_vec_counter_1  : unsigned(VEC_NO_SIZE - 1 downto 0);
+	variable in_vec_counter_2  : unsigned(VEC_NO_SIZE - 1 downto 0);
+	begin
+		if (reset = '1') then
+			in_vec_counter_1 := (others => '0');
+			in_vec_counter_2 := (others => '0');
+			stdin_data       <= (others => '0');
+			stdin_ack_sig    <= '0';
+		elsif rising_edge(clock) then
+			case context_uut is
+				when "01" =>
+					if (en_feed = '1') then
+						stdin_data <= input_vectors_1(to_integer(in_vec_counter_1));
+						stdin_ack_sig  <= '1';
+						if (stdin_rdy = '1' and stdin_ack_sig = '1') then
+							in_vec_counter_1 := in_vec_counter_1 + 1;
+							stdin_ack_sig  <= '0';
+						end if;
+					else
+						--in_vec_counter_1 <= (others => '0');
+						stdin_data     <= (others => '0');
+						stdin_ack_sig  <= '0';
+					end if;
+				when "10" =>
+					if (en_feed = '1') then
+						stdin_data <= input_vectors_2(to_integer(in_vec_counter_2));
+						stdin_ack_sig  <= '1';
+						if (stdin_rdy = '1' and stdin_ack_sig = '1') then
+							in_vec_counter_2 := in_vec_counter_2 + 1;
+							stdin_ack_sig  <= '0';
+						end if;
+					else
+						--in_vec_counter_2 <= (others => '0');
+						stdin_data     <= (others => '0');
+						stdin_ack_sig  <= '0';
+					end if;
+				when others =>
+			end case;
+		end if;
+	end process feed;
+
+	check : process(reset, clock) is
+	begin
+		if (reset = '1') then
+			n_error     <= '1';
+			vec_read <= '0';
+		elsif rising_edge(clock) then
+			vec_read <= '0';
+			if (en_check = '1') then
+				if (stdout_rdy = '1') then
+					vec_read <= '1';
+					case context_uut is
+						when "01" =>
+							assert (stdout_data = output_vectors_1(to_integer(out_vec_counter_1)))
+							report "ERROR ---> Bad output vector found";
+							--synthesizable check
+							if (stdout_data /= output_vectors_1(to_integer(out_vec_counter_1))) then
+								n_error <= '0';
+							end if;
+						when "10" =>
+							assert (stdout_data = output_vectors_2(to_integer(out_vec_counter_2)))
+							report "ERROR ---> Bad output vector found";
+							--synthesizable check
+							if (stdout_data /= output_vectors_2(to_integer(out_vec_counter_2))) then
+								n_error <= '0';
+							end if;
+						when others =>
+					end case;
+				end if;
+			end if;
+		end if;
+	end process check;
+
+	read_counter : process(reset, clock) is
+	begin
+		if (reset = '1') then
+			out_vec_counter_1 <= (others => '0');
+			out_vec_counter_2 <= (others => '0');
+		elsif rising_edge(clock) then
+			if (en_check = '1') then
+				if (stdout_rdy = '1') then
+					case context_uut is
+						when "01" =>
+							out_vec_counter_1 <= out_vec_counter_1 + 1;
+						when "10" =>
+							out_vec_counter_2 <= out_vec_counter_2 + 1;
+						when others =>
+					end case;
+				end if;
+			--else
+			--	case context_uut is
+			--		when "01" =>
+			--			out_vec_counter_1 <= (others => '0');
+			--		when "10" =>
+			--			out_vec_counter_2 <= (others => '0');
+			--		when others =>
+			--	end case;
+			end if;
+		end if;
+	end process read_counter;
+
+	--asynchronous declarations
+	stdout_ack <= en_check;
+	stdin_ack <= stdin_ack_sig;
+	vecs_found <= '1' when (out_vec_counter_1 /= 0 or out_vec_counter_2 /= 0) else '0';
+
+end rtl;
diff --git a/testsuite/gna/issue50/vector.d/cmp_111.vhd b/testsuite/gna/issue50/vector.d/cmp_111.vhd
new file mode 100644
index 000000000..5e35d5292
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_111.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_111 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_111;
+
+architecture augh of cmp_111 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_112.vhd b/testsuite/gna/issue50/vector.d/cmp_112.vhd
new file mode 100644
index 000000000..e27456ee4
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_112.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_112 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_112;
+
+architecture augh of cmp_112 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_113.vhd b/testsuite/gna/issue50/vector.d/cmp_113.vhd
new file mode 100644
index 000000000..f83b71ce1
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_113.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_113 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_113;
+
+architecture augh of cmp_113 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_114.vhd b/testsuite/gna/issue50/vector.d/cmp_114.vhd
new file mode 100644
index 000000000..e15bf43cd
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_114.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_114 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_114;
+
+architecture augh of cmp_114 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_115.vhd b/testsuite/gna/issue50/vector.d/cmp_115.vhd
new file mode 100644
index 000000000..00d218957
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_115.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_115 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_115;
+
+architecture augh of cmp_115 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_119.vhd b/testsuite/gna/issue50/vector.d/cmp_119.vhd
new file mode 100644
index 000000000..2b2245787
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_119.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_119 is
+	port (
+		ne : out std_logic;
+		in0 : in  std_logic_vector(15 downto 0);
+		in1 : in  std_logic_vector(15 downto 0)
+	);
+end cmp_119;
+
+architecture augh of cmp_119 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	ne <= not(tmp);
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_126.vhd b/testsuite/gna/issue50/vector.d/cmp_126.vhd
new file mode 100644
index 000000000..f2a630842
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_126.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_126 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_126;
+
+architecture augh of cmp_126 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_127.vhd b/testsuite/gna/issue50/vector.d/cmp_127.vhd
new file mode 100644
index 000000000..94611a018
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_127.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_127 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_127;
+
+architecture augh of cmp_127 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_128.vhd b/testsuite/gna/issue50/vector.d/cmp_128.vhd
new file mode 100644
index 000000000..d23132fd4
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_128.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_128 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_128;
+
+architecture augh of cmp_128 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_129.vhd b/testsuite/gna/issue50/vector.d/cmp_129.vhd
new file mode 100644
index 000000000..cc56d03b8
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_129.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_129 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_129;
+
+architecture augh of cmp_129 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_130.vhd b/testsuite/gna/issue50/vector.d/cmp_130.vhd
new file mode 100644
index 000000000..6e3e529eb
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_130.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_130 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_130;
+
+architecture augh of cmp_130 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_131.vhd b/testsuite/gna/issue50/vector.d/cmp_131.vhd
new file mode 100644
index 000000000..c7450e430
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_131.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_131 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_131;
+
+architecture augh of cmp_131 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_132.vhd b/testsuite/gna/issue50/vector.d/cmp_132.vhd
new file mode 100644
index 000000000..12cbe3918
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_132.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_132 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_132;
+
+architecture augh of cmp_132 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_133.vhd b/testsuite/gna/issue50/vector.d/cmp_133.vhd
new file mode 100644
index 000000000..efee40dc7
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_133.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_133 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_133;
+
+architecture augh of cmp_133 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_135.vhd b/testsuite/gna/issue50/vector.d/cmp_135.vhd
new file mode 100644
index 000000000..d5e1d49e3
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_135.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_135 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_135;
+
+architecture augh of cmp_135 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_136.vhd b/testsuite/gna/issue50/vector.d/cmp_136.vhd
new file mode 100644
index 000000000..1dfb02bc3
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_136.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_136 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_136;
+
+architecture augh of cmp_136 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_137.vhd b/testsuite/gna/issue50/vector.d/cmp_137.vhd
new file mode 100644
index 000000000..064415f94
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_137.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_137 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_137;
+
+architecture augh of cmp_137 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_138.vhd b/testsuite/gna/issue50/vector.d/cmp_138.vhd
new file mode 100644
index 000000000..c5f42eaa5
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_138.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_138 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_138;
+
+architecture augh of cmp_138 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_139.vhd b/testsuite/gna/issue50/vector.d/cmp_139.vhd
new file mode 100644
index 000000000..809619fbf
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_139.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_139 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_139;
+
+architecture augh of cmp_139 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_140.vhd b/testsuite/gna/issue50/vector.d/cmp_140.vhd
new file mode 100644
index 000000000..033dd940a
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_140.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_140 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_140;
+
+architecture augh of cmp_140 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_141.vhd b/testsuite/gna/issue50/vector.d/cmp_141.vhd
new file mode 100644
index 000000000..f514e59d4
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_141.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_141 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_141;
+
+architecture augh of cmp_141 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_142.vhd b/testsuite/gna/issue50/vector.d/cmp_142.vhd
new file mode 100644
index 000000000..8e618fb9b
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_142.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_142 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_142;
+
+architecture augh of cmp_142 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_146.vhd b/testsuite/gna/issue50/vector.d/cmp_146.vhd
new file mode 100644
index 000000000..56262f16c
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_146.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_146 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_146;
+
+architecture augh of cmp_146 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_148.vhd b/testsuite/gna/issue50/vector.d/cmp_148.vhd
new file mode 100644
index 000000000..de5f67862
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_148.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_148 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_148;
+
+architecture augh of cmp_148 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_150.vhd b/testsuite/gna/issue50/vector.d/cmp_150.vhd
new file mode 100644
index 000000000..75c66f25a
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_150.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_150 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_150;
+
+architecture augh of cmp_150 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_152.vhd b/testsuite/gna/issue50/vector.d/cmp_152.vhd
new file mode 100644
index 000000000..4d05e52bf
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_152.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_152 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_152;
+
+architecture augh of cmp_152 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_154.vhd b/testsuite/gna/issue50/vector.d/cmp_154.vhd
new file mode 100644
index 000000000..b9dde5333
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_154.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_154 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_154;
+
+architecture augh of cmp_154 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_156.vhd b/testsuite/gna/issue50/vector.d/cmp_156.vhd
new file mode 100644
index 000000000..75cf950bd
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_156.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_156 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_156;
+
+architecture augh of cmp_156 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_158.vhd b/testsuite/gna/issue50/vector.d/cmp_158.vhd
new file mode 100644
index 000000000..82efe368c
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_158.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_158 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_158;
+
+architecture augh of cmp_158 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_160.vhd b/testsuite/gna/issue50/vector.d/cmp_160.vhd
new file mode 100644
index 000000000..9fb84d1cd
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_160.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_160 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_160;
+
+architecture augh of cmp_160 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_174.vhd b/testsuite/gna/issue50/vector.d/cmp_174.vhd
new file mode 100644
index 000000000..86a3b443b
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_174.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_174 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_174;
+
+architecture augh of cmp_174 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_176.vhd b/testsuite/gna/issue50/vector.d/cmp_176.vhd
new file mode 100644
index 000000000..9ba5527e2
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_176.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_176 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_176;
+
+architecture augh of cmp_176 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_178.vhd b/testsuite/gna/issue50/vector.d/cmp_178.vhd
new file mode 100644
index 000000000..f594227ac
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_178.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_178 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_178;
+
+architecture augh of cmp_178 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_180.vhd b/testsuite/gna/issue50/vector.d/cmp_180.vhd
new file mode 100644
index 000000000..b69344eec
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_180.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_180 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_180;
+
+architecture augh of cmp_180 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_183.vhd b/testsuite/gna/issue50/vector.d/cmp_183.vhd
new file mode 100644
index 000000000..3fea5412e
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_183.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_183 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_183;
+
+architecture augh of cmp_183 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_185.vhd b/testsuite/gna/issue50/vector.d/cmp_185.vhd
new file mode 100644
index 000000000..e45f5ca03
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_185.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_185 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_185;
+
+architecture augh of cmp_185 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_187.vhd b/testsuite/gna/issue50/vector.d/cmp_187.vhd
new file mode 100644
index 000000000..4254b67ab
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_187.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_187 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_187;
+
+architecture augh of cmp_187 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_191.vhd b/testsuite/gna/issue50/vector.d/cmp_191.vhd
new file mode 100644
index 000000000..af123383f
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_191.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_191 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_191;
+
+architecture augh of cmp_191 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_193.vhd b/testsuite/gna/issue50/vector.d/cmp_193.vhd
new file mode 100644
index 000000000..3eeeba859
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_193.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_193 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_193;
+
+architecture augh of cmp_193 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_195.vhd b/testsuite/gna/issue50/vector.d/cmp_195.vhd
new file mode 100644
index 000000000..61851b275
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_195.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_195 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_195;
+
+architecture augh of cmp_195 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_198.vhd b/testsuite/gna/issue50/vector.d/cmp_198.vhd
new file mode 100644
index 000000000..6620b9de3
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_198.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_198 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_198;
+
+architecture augh of cmp_198 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_200.vhd b/testsuite/gna/issue50/vector.d/cmp_200.vhd
new file mode 100644
index 000000000..794a2ddad
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_200.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_200 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_200;
+
+architecture augh of cmp_200 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_202.vhd b/testsuite/gna/issue50/vector.d/cmp_202.vhd
new file mode 100644
index 000000000..a16cc719a
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_202.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_202 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_202;
+
+architecture augh of cmp_202 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_204.vhd b/testsuite/gna/issue50/vector.d/cmp_204.vhd
new file mode 100644
index 000000000..18c2cade8
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_204.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_204 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_204;
+
+architecture augh of cmp_204 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_215.vhd b/testsuite/gna/issue50/vector.d/cmp_215.vhd
new file mode 100644
index 000000000..2671110bd
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_215.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_215 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_215;
+
+architecture augh of cmp_215 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_216.vhd b/testsuite/gna/issue50/vector.d/cmp_216.vhd
new file mode 100644
index 000000000..37307f2b6
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_216.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_216 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_216;
+
+architecture augh of cmp_216 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_217.vhd b/testsuite/gna/issue50/vector.d/cmp_217.vhd
new file mode 100644
index 000000000..ca2756b70
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_217.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_217 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_217;
+
+architecture augh of cmp_217 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_218.vhd b/testsuite/gna/issue50/vector.d/cmp_218.vhd
new file mode 100644
index 000000000..09b8d9273
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_218.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_218 is
+	port (
+		eq : out std_logic;
+		in0 : in  std_logic_vector(2 downto 0);
+		in1 : in  std_logic_vector(2 downto 0)
+	);
+end cmp_218;
+
+architecture augh of cmp_218 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	eq <= tmp;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cmp_221.vhd b/testsuite/gna/issue50/vector.d/cmp_221.vhd
new file mode 100644
index 000000000..6c7aaac74
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cmp_221.vhd
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_221 is
+	port (
+		ne : out std_logic;
+		in0 : in  std_logic_vector(15 downto 0);
+		in1 : in  std_logic_vector(15 downto 0)
+	);
+end cmp_221;
+
+architecture augh of cmp_221 is
+
+	signal tmp : std_logic;
+
+begin
+
+	-- Compute the result
+	tmp <=
+		'0' when in0 /= in1 else
+		'1';
+
+	-- Set the outputs
+	ne <= not(tmp);
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/cp3_test.vhd b/testsuite/gna/issue50/vector.d/cp3_test.vhd
new file mode 100644
index 000000000..99fdbb678
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/cp3_test.vhd
@@ -0,0 +1,280 @@
+-- written by Alban Bourge @ TIMA
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.pkg_tb.all;
+
+entity cp3_test is
+	port(
+				clock   : in std_logic;
+				reset   : in std_logic;
+				n_error : out std_logic;
+				stopped : out std_logic
+			);
+end cp3_test;
+
+architecture rtl of cp3_test is
+
+	--TOP signals
+	signal reset_top   : std_logic := '0';
+	signal stdin_data  : stdin_vector;
+	signal stdin_rdy   : std_logic;
+	signal stdin_ack   : std_logic;
+	signal stdout_data : stdout_vector;
+	signal stdout_rdy  : std_logic;
+	signal stdout_ack  : std_logic;
+	--ASSERT_UNIT signals
+	signal context_uut : context_t;
+	signal en_feed     : std_logic;
+	signal en_check    : std_logic;
+	signal n_error_s   : std_logic;
+	signal vecs_found  : std_logic;
+	signal vec_read    : std_logic;
+	--PROG unit signals
+	signal instr_next  : instruction;
+	-- FSM unit signals
+	signal step        : std_logic;
+	signal start       : std_logic;
+	-- FSM signals
+	signal reset_fsm   : std_logic;
+	signal stopped_s   : std_logic;
+
+
+--------------------------------------
+--   PART OF ARCHITECTURE WITH CP3  --
+
+	--TOP signals
+	signal cp_en       : std_logic := '0';
+	signal cp_rest     : std_logic := '0';
+	signal cp_ok       : std_logic;
+	signal cp_din      : cp_vector := (others => '0');
+	signal cp_dout     : cp_vector;
+	--RAM signals
+	signal ram_1       : ram_instruction;
+	signal ram_2       : ram_instruction;
+	signal address1    : std_logic_vector(12 downto 0) := (others => '0');
+	signal address2    : std_logic_vector(12 downto 0) := (others => '0');
+	signal datain      : cp_vector := (others => '0');
+	signal dout1       : cp_vector;
+	signal dout2       : cp_vector;
+
+	--dut component declaration
+	component top is
+		port (
+			clock : in  std_logic;
+			reset : in  std_logic;
+			start : in  std_logic;
+			stdin_data : in  stdin_vector;
+			stdin_rdy : out std_logic;
+			stdin_ack : in  std_logic;
+			stdout_data : out stdout_vector;
+			stdout_rdy : out std_logic;
+			stdout_ack : in  std_logic;
+			cp_en : in  std_logic;
+			cp_rest : in  std_logic;
+			cp_din : in  cp_vector;
+			cp_dout : out cp_vector;
+			cp_ok : out std_logic
+		);
+	end component top;
+
+begin
+
+	uut : entity work.top(augh)
+	port map(
+						clock       => clock,
+						reset       => reset_top,
+						start       => start,
+						stdin_data  => stdin_data,
+						stdin_rdy   => stdin_rdy,
+						stdin_ack   => stdin_ack,
+						cp_en       => cp_en,
+						cp_rest     => cp_rest,
+						cp_ok       => cp_ok,
+						cp_din      => cp_din,
+						cp_dout     => cp_dout,
+						stdout_data => stdout_data,
+						stdout_rdy  => stdout_rdy,
+						stdout_ack  => stdout_ack
+					);
+
+	ram1 : entity work.sync_ram(rtl)
+	port map(
+						clock   => clock,
+						we      => ram_1.we,
+						address => address1,
+						datain  => datain,
+						dataout => dout1
+					);
+
+	ram2 : entity work.sync_ram(rtl)
+	port map(
+						clock   => clock,
+						we      => ram_2.we,
+						address => address2,
+						datain  => datain,
+						dataout => dout2
+					);
+
+	fsm_unit : entity work.fsm(rtl)
+	port map(
+						clock      => clock,
+						reset      => reset,
+						--prog interface
+						instr_next => instr_next,
+						step       => step,
+						--uut interface
+						cp_ok      => cp_ok,
+						stdin_rdy  => stdin_rdy,
+						stdin_ack  => stdin_ack,
+						reset_fsm  => reset_fsm,
+						start      => start,
+						cp_en      => cp_en,
+						cp_rest    => cp_rest,
+						--ram interface
+						ram_1      => ram_1,
+						ram_2      => ram_2,
+						--assert_uut interface
+						context_uut => context_uut,
+						en_feed    => en_feed,
+						en_check   => en_check,
+						vecs_found => vecs_found,
+						vec_read   => vec_read,
+						--tb interface
+						stopped    => stopped_s
+					);
+
+	--RAM ADDRESS controller 1
+	ram_ctrl1 : process(clock, reset)
+	begin
+		if (reset = '1') then
+			address1 <= (others => '0');
+		elsif rising_edge(clock) then
+			if (ram_1.addr_z = '1') then
+				address1 <= (others => '0');
+			elsif (ram_1.addr_up = '1') then
+				address1 <= std_logic_vector(unsigned(address1) + 1);
+			end if;
+		end if;
+	end process ram_ctrl1;
+
+	--RAM ADDRESS controller 2
+	ram_ctrl2 : process(clock, reset)
+	begin
+		if (reset = '1') then
+			address2 <= (others => '0');
+		elsif rising_edge(clock) then
+			if (ram_2.addr_z = '1') then
+				address2 <= (others => '0');
+			elsif (ram_2.addr_up = '1') then
+				address2 <= std_logic_vector(unsigned(address2) + 1);
+			end if;
+		end if;
+	end process ram_ctrl2;
+
+	--other comb signals
+	datain <= cp_dout;
+	cp_din <= dout2 when ram_2.sel = '1' else dout1;
+
+--   END OF ARCHITECTURE WITH CP3  --
+--------------------------------------
+
+--------------------------------------
+-- PART OF ARCHITECTURE WITHOUT CP3 --
+--
+--	--dut component declaration
+--	component top is
+--		port (
+--			clock : in  std_logic;
+--			reset : in  std_logic;
+--			start : in  std_logic;
+--			stdin_data : in  stdin_vector;
+--			stdin_rdy : out std_logic;
+--			stdin_ack : in  std_logic;
+--			stdout_data : out stdout_vector;
+--			stdout_rdy : out std_logic;
+--			stdout_ack : in  std_logic
+--		);
+--	end component top;
+--
+--begin
+--
+--	uut : entity work.top(augh)
+--	port map(
+--						clock       => clock,
+--						reset       => reset_top,
+--						start       => start,
+--						stdin_data  => stdin_data,
+--						stdin_rdy   => stdin_rdy,
+--						stdin_ack   => stdin_ack,
+--						stdout_data => stdout_data,
+--						stdout_rdy  => stdout_rdy,
+--						stdout_ack  => stdout_ack
+--					);
+--
+--	fsm_unit : entity work.fsm(rtl)
+--	port map(
+--						clock      => clock,
+--						reset      => reset,
+--						--prog interface
+--						instr_next => instr_next,
+--						step       => step,
+--						--uut interface
+--						cp_ok      => '0',
+--						stdin_rdy  => stdin_rdy,
+--						stdin_ack  => stdin_ack,
+--						reset_fsm  => reset_fsm,
+--						start      => start,
+--						cp_en      => open,
+--						cp_rest    => open,
+--						--ram interface
+--						ram_1      => open,
+--						ram_2      => open,
+--						--assert_uut interface
+--						context_uut => context_uut,
+--						en_feed    => en_feed,
+--						en_check   => en_check,
+--						vecs_found => vecs_found,
+--						vec_read   => vec_read,
+--						--tb interface
+--						stopped    => stopped_s
+--					);
+--
+-- END OF ARCHITECTURE WITHOUT CP3 --
+--------------------------------------
+
+	assert_unit : entity work.assert_uut(rtl)
+	port map(
+						clock       => clock,
+						reset       => reset,
+						context_uut => context_uut,
+						en_feed     => en_feed,
+						stdin_rdy   => stdin_rdy,
+						stdin_ack   => stdin_ack,
+						stdin_data  => stdin_data,
+						en_check    => en_check,
+						stdout_rdy  => stdout_rdy,
+						stdout_ack  => stdout_ack,
+						stdout_data => stdout_data,
+						vecs_found  => vecs_found,
+						vec_read    => vec_read,
+						n_error     => n_error_s
+					);
+
+	prog_unit : entity work.prog(rtl)
+	port map(
+						clock      => clock,
+						reset      => reset,
+						step       => step,
+						instr_next => instr_next
+					);
+
+	--other comb signals
+	reset_top <= reset or reset_fsm;
+
+	--outputs
+	n_error <= n_error_s;
+	stopped <= stopped_s;
+
+end rtl;
diff --git a/testsuite/gna/issue50/vector.d/fsm.vhd b/testsuite/gna/issue50/vector.d/fsm.vhd
new file mode 100644
index 000000000..2f4ef87ee
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/fsm.vhd
@@ -0,0 +1,396 @@
+--test bench written by Alban Bourge @ TIMA
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+library work;
+use work.pkg_tb.all;
+
+entity fsm is
+	port(
+				clock      : in std_logic;
+				reset      : in std_logic;
+				--prog interface
+				instr_next : in instruction;
+				step       : out std_logic;
+				--uut interface
+				cp_ok      : in std_logic;
+				stdin_rdy  : in std_logic;
+				stdin_ack  : in std_logic;
+				reset_fsm  : out std_logic;
+				start      : out std_logic;
+				cp_en      : out std_logic;
+				cp_rest    : out std_logic;
+				--ram interface
+				ram_1      : out ram_instruction;
+				ram_2      : out ram_instruction;
+				--assert_uut interface
+				context_uut : out context_t;
+				en_feed    : out std_logic;
+				en_check   : out std_logic;
+				vecs_found : in std_logic;
+				vec_read   : in std_logic;
+				--tb interface
+				stopped    : out std_logic
+			);
+end fsm;
+
+architecture rtl of fsm is
+
+	-- read output
+	signal step_sig  : std_logic;
+	-- FSM signals
+	signal instr_c   : instruction := instr_rst;
+	signal instr_n   : instruction := instr_rst;
+	-- TIMER signal
+	signal times_en  : std_logic := '0';
+	signal times_z   : std_logic := '0';
+	signal times     : unsigned(ARG_WIDTH - 1 downto 0);
+	signal times_max : unsigned(ARG_WIDTH - 1 downto 0);
+	signal times_ok  : std_logic := '0';
+	-- COUNTER signal
+	signal count_en  : std_logic := '0';
+	signal count_z   : std_logic := '0';
+	signal count     : unsigned(ARG_WIDTH - 1 downto 0);
+	signal count_max : unsigned(ARG_WIDTH - 1 downto 0);
+	signal count_ok  : std_logic := '0';
+	-- runtime counter
+	signal runtime_en : std_logic := '0';
+	signal runtime    : integer range 0 to 99999999; --100 million cycles
+
+begin
+
+	-- FSM
+	state_reg : process (clock, reset) is
+	begin
+		if (reset = '1') then
+			instr_c <= instr_rst;
+		elsif rising_edge(clock) then
+			instr_c <= instr_n;
+		end if;
+	end process state_reg;
+
+	comb_logic: process(instr_next, instr_c, stdin_rdy, count_ok, times_ok, cp_ok, stdin_ack, vecs_found, vec_read)
+	begin
+		--default definition for fsm control signals
+		instr_n    <= instr_rst;
+		step_sig   <= '0';
+		--top
+		reset_fsm  <= '0';
+		start      <= '0';
+		cp_en      <= '0';
+		cp_rest    <= '0';
+		--counter & timer
+		times_en   <= '0';
+		times_max  <= (others => '0');
+		count_en   <= '0';
+		count_max  <= (others => '0');
+		--runtime counter
+		runtime_en <= '0';
+		--ram
+		ram_1      <= ram_instr_z;
+		ram_2      <= ram_instr_z;
+		--assert_uut
+		en_feed    <= '0';
+		en_check   <= '0';
+		--tb interface
+		stopped    <= '0';
+
+		case instr_c.state is
+			when Rst =>
+				--signals
+				reset_fsm    <= '1';
+				ram_1.addr_z <= '1';
+				ram_2.addr_z <= '1';
+				step_sig     <= '1'; --demand for next instruction
+				--transition
+				instr_n <= instr_next;
+
+			when Sig_start =>
+				--signals
+				start    <= '1';
+				step_sig <= '1'; --demand for next instruction
+				--transition
+				instr_n <= instr_next;
+				--if (instr_next.state = Ack_data) then
+					--en_feed <= '1';
+				--end if;
+
+			when Ack_data =>
+				times_max <= instr_c.arg - 1;
+				--signals
+				en_feed <= '1';
+				--transition
+				if (stdin_rdy = '1' and stdin_ack = '1') then
+					times_en <= '1';
+				end if;
+				if (times_ok = '1') then
+					en_feed <= '0';
+					step_sig <= '1';
+					instr_n <= instr_next;
+				else
+					instr_n <= instr_c;
+				end if;
+
+			when Running =>
+				--signals
+				count_max <= instr_c.arg;
+				count_en  <= '1';
+				--en_check  <= '1';
+				--runtime counter
+				if(vecs_found = '0') then
+					runtime_en <= '1';
+				end if;
+				--transition
+				if (count_ok = '1') then
+					step_sig <= '1';
+					instr_n  <= instr_next;
+				else
+					instr_n <= instr_c;
+				end if;
+
+			when Waitfor =>
+				--signals
+				count_max <= instr_c.arg;
+				en_check  <= '1';
+				if(vec_read = '1') then
+					count_en  <= '1';
+				end if;
+				--runtime counter
+				if(vecs_found = '0') then
+					runtime_en <= '1';
+				end if;
+				--transition
+				if (count_ok = '1') then
+					step_sig <= '1';
+					instr_n  <= instr_next;
+				else
+					instr_n <= instr_c;
+				end if;
+
+			when Cp_search =>
+				--signals
+				cp_en <= '1';
+				--transition
+				if (cp_ok = '1') then
+					case instr_c.context_uut is
+						when "01" =>
+							ram_1.we <= '1';
+							ram_1.addr_up  <= '1';
+							ram_1.sel  <= '1';
+						when "10" =>
+							ram_2.we <= '1';
+							ram_2.addr_up  <= '1';
+							ram_2.sel  <= '1';
+						when others =>
+					end case;
+					instr_n  <= (state => Cp_save, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
+				else
+					instr_n <= instr_c;
+				end if;
+
+			when Cp_save =>
+				--signals
+				cp_en    <= '1';
+				case instr_c.context_uut is
+					when "01" =>
+						ram_1.we <= '1';
+						ram_1.addr_up  <= '1';
+						ram_1.sel  <= '1';
+					when "10" =>
+						ram_2.we <= '1';
+						ram_2.addr_up  <= '1';
+						ram_2.sel  <= '1';
+					when others =>
+				end case;
+				--transition
+				if (cp_ok = '0') then
+					case instr_c.context_uut is
+						when "01" =>
+							ram_1.we <= '0';
+							ram_1.addr_up  <= '0';
+						when "10" =>
+							ram_2.we <= '0';
+							ram_2.addr_up  <= '0';
+						when others =>
+					end case;
+					step_sig <= '1';
+					instr_n  <= instr_next;
+				else
+					instr_n  <= instr_c;
+				end if;
+
+			when Idle => 
+				--signals
+				count_max <= instr_c.arg;
+				count_en <= '1';
+				--transition
+				if (count_ok = '1') then
+					step_sig <= '1';
+					instr_n <= instr_next;
+				else
+					instr_n <= instr_c;
+				end if;
+
+			when Rst_uut =>
+				--signals
+				reset_fsm <= '1';
+				ram_1.addr_z <= '1';
+				ram_2.addr_z <= '1';
+				--transition
+				step_sig <= '1';
+				instr_n <= instr_next;
+
+			when Rest_ini0 =>
+				--signals
+				start   <= '1';
+				cp_en   <= '1';
+				cp_rest <= '1';
+				--this is for restoration : reading the first word of the right memory
+				case instr_c.context_uut is
+					when "01" =>
+						ram_1.sel  <= '1';
+					when "10" =>
+						ram_2.sel  <= '1';
+					when others =>
+				end case;
+				--transition
+				instr_n <= (state => Rest_ini1, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
+
+			when Rest_ini1 =>
+				--signals
+				cp_en   <= '1';
+				cp_rest <= '1';
+				case instr_c.context_uut is
+					when "01" =>
+						ram_1.addr_up  <= '1';
+						ram_1.sel  <= '1';
+					when "10" =>
+						ram_2.addr_up  <= '1';
+						ram_2.sel  <= '1';
+					when others =>
+				end case;
+				--transition
+				instr_n <= (state => Rest, context_uut => instr_c.context_uut, arg => (others => '0')); --hard coded
+
+			when Rest =>
+				--signals
+				cp_en   <= '1';
+				cp_rest <= '1';
+				case instr_c.context_uut is
+					when "01" =>
+						ram_1.addr_up  <= '1';
+						ram_1.sel  <= '1';
+					when "10" =>
+						ram_2.addr_up  <= '1';
+						ram_2.sel  <= '1';
+					when others =>
+				end case;
+				--transition
+				if (cp_ok = '0') then
+					step_sig <= '1';
+					instr_n  <= instr_next;
+				else
+					instr_n  <= instr_c;
+				end if;
+
+			when Stop =>
+				--signals
+				stopped   <= '1';
+				reset_fsm <= '1';
+				report "RUNTIME:" & integer'image(runtime);
+				assert (vecs_found = '0')
+				report "END_OF_SIM ---> Stop state reached, some output vectors were read." severity note;
+				--transition
+				instr_n <= (state => Stop, context_uut => "00", arg => (others => '0')); --hard coded
+
+			when others =>
+		end case;
+	end process comb_logic;
+
+	--*ER reset combo logic
+	--if a step_sig signal is sent, it means a instr_next will be consumed
+	reseter : process(step_sig)
+	begin
+		if (step_sig = '0') then
+			times_z    <= '0';
+			count_z    <= '0';
+		else
+			times_z    <= '1';
+			count_z    <= '1';
+		end if;
+	end process reseter;
+
+	--TIMER
+	timer : process(clock, reset)
+	begin
+		if (reset =  '1') then
+			times    <= (others => '0');
+			times_ok <= '0';
+		elsif rising_edge(clock) then
+			if (times_z = '1') then
+				times    <= (others => '0');
+				times_ok <= '0';
+			else
+				if (times_en = '1') then
+					times <= times + 1;
+					if (times = times_max) then
+						times_ok <= '1';
+					else
+						times_ok <= '0';
+					end if;
+				end if;
+			end if;
+		end if;
+	end process timer;
+
+	--COUNTER
+	counter : process(clock, reset)
+	begin
+		if (reset =  '1') then
+			count <= (others => '0');
+			count_ok <= '0';
+		elsif rising_edge(clock) then
+			--count_ok driving if
+			if (count_z = '1') then
+				count_ok <= '0';
+				count    <= (others => '0');
+			else
+				if (count = count_max) then
+					count_ok <= '1';
+				else
+					count_ok <= '0';
+					if (count_en = '1') then
+						count <= count + 1;
+					end if;
+				end if;
+			end if;
+		end if;
+		end process counter;
+
+	--Runtime counter
+	runtime_counter : process(clock, reset)
+	begin
+		if (reset =  '1') then
+			runtime <= 0;
+		elsif rising_edge(clock) then
+			if (runtime_en = '1') then
+				runtime <= runtime + 1;
+				if ((runtime mod 1000) = 0) then
+					report "Running since:" & integer'image(runtime) severity note;
+				end if;
+			end if;
+		end if;
+	end process runtime_counter;
+
+	-- process only used for reporting current instruction
+	reporter : process(instr_c)
+	begin
+		--report "Instruction: " & state_t'image(instr_c.state) severity note;
+		report "Instruction: " & state_t'image(instr_c.state) & " (context " & integer'image(to_integer(unsigned(instr_c.context_uut))) & ")" severity note;
+	end process reporter;
+
+	--Combinational
+	step <= step_sig;
+	context_uut <= instr_c.context_uut;
+end rtl;
diff --git a/testsuite/gna/issue50/vector.d/fsm_15.vhd b/testsuite/gna/issue50/vector.d/fsm_15.vhd
new file mode 100644
index 000000000..576089e8b
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/fsm_15.vhd
@@ -0,0 +1,539 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity fsm_15 is
+	port (
+		clock : in  std_logic;
+		reset : in  std_logic;
+		out3 : out std_logic;
+		out157 : out std_logic;
+		out159 : out std_logic;
+		out160 : out std_logic;
+		out171 : out std_logic;
+		out172 : out std_logic;
+		out173 : out std_logic;
+		out175 : out std_logic;
+		out178 : out std_logic;
+		in0 : in  std_logic;
+		out0 : out std_logic;
+		in5 : in  std_logic;
+		in6 : in  std_logic;
+		in7 : in  std_logic;
+		out35 : out std_logic;
+		out39 : out std_logic;
+		out40 : out std_logic;
+		out41 : out std_logic;
+		out44 : out std_logic;
+		out46 : out std_logic;
+		out140 : out std_logic;
+		in8 : in  std_logic;
+		in9 : in  std_logic;
+		in10 : in  std_logic;
+		in11 : in  std_logic;
+		in12 : in  std_logic;
+		in13 : in  std_logic;
+		in14 : in  std_logic;
+		out65 : out std_logic;
+		in1 : in  std_logic;
+		in2 : in  std_logic;
+		in3 : in  std_logic;
+		in4 : in  std_logic;
+		out225 : out std_logic;
+		out227 : out std_logic;
+		out231 : out std_logic;
+		out235 : out std_logic;
+		out236 : out std_logic;
+		out237 : out std_logic;
+		out238 : out std_logic;
+		out97 : out std_logic;
+		out98 : out std_logic;
+		out101 : out std_logic;
+		out102 : out std_logic;
+		out124 : out std_logic;
+		out125 : out std_logic;
+		out80 : out std_logic;
+		out81 : out std_logic;
+		out84 : out std_logic;
+		out86 : out std_logic;
+		out88 : out std_logic;
+		out93 : out std_logic;
+		out94 : out std_logic
+	);
+end fsm_15;
+
+architecture augh of fsm_15 is
+
+	signal state_cur  : std_logic_vector(0 to 21) := (19 => '1', others => '0');
+	signal state_next : std_logic_vector(0 to 21) := (19 => '1', others => '0');
+
+	-- Buffers for outputs
+	signal out0_buf : std_logic := '0';
+	signal out0_bufn : std_logic;
+	signal out40_buf : std_logic := '0';
+	signal out40_bufn : std_logic;
+	signal out101_buf : std_logic := '0';
+	signal out101_bufn : std_logic;
+	signal out172_buf : std_logic := '0';
+	signal out172_bufn : std_logic;
+
+	-- Function calls: return IDs
+	signal funccall0 :      unsigned(0 downto 0) := (others => '0');
+	signal funccall0_next : unsigned(0 downto 0) := (others => '0');
+
+begin
+
+	-- Sequential process
+	-- Set the current state
+
+	process (clock)
+	begin
+		if rising_edge(clock) then
+
+			-- Next state
+			state_cur <= state_next;
+			-- Buffers for outputs
+			out0_buf <= out0_bufn;
+			out40_buf <= out40_bufn;
+			out101_buf <= out101_bufn;
+			out172_buf <= out172_bufn;
+			-- Function calls: return IDs
+			funccall0 <= funccall0_next;
+
+		end if;
+	end process;
+
+	-- Combinatorial process
+	-- Compute the next state
+	-- Compute the outputs
+
+	process (
+		-- Inputs of the FSM
+		reset, in0, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in1, in2, in3, in4,
+		-- Function calls: return IDs
+		funccall0,
+		-- Current state
+		state_cur
+	)
+	begin
+
+		-- Reset the next state value
+
+		state_next <= (others => '0');
+
+		-- Default value to the outputs or output buffers
+
+		out46 <= '0';
+		out35 <= '0';
+		out65 <= '0';
+		out39 <= '0';
+		out3 <= '0';
+		out44 <= '0';
+		out0_bufn <= '0';
+		out41 <= '0';
+		out40_bufn <= '0';
+		out80 <= '0';
+		out81 <= '0';
+		out84 <= '0';
+		out86 <= '0';
+		out88 <= '0';
+		out93 <= '0';
+		out94 <= '0';
+		out97 <= '0';
+		out98 <= '0';
+		out101_bufn <= '0';
+		out102 <= '0';
+		out124 <= '0';
+		out125 <= '0';
+		out140 <= '0';
+		out157 <= '0';
+		out159 <= '0';
+		out160 <= '0';
+		out171 <= '0';
+		out172_bufn <= '0';
+		out173 <= '0';
+		out175 <= '0';
+		out178 <= '0';
+		out225 <= '0';
+		out227 <= '0';
+		out231 <= '0';
+		out235 <= '0';
+		out236 <= '0';
+		out237 <= '0';
+		out238 <= '0';
+
+		-- Function calls: default values (no change)
+		funccall0_next <= funccall0;
+
+		-- For all states, compute the next state bits
+		--   And the outputs, and the next value for buffered outputs
+
+		if state_cur(0) = '1' then
+			-- Next state
+			if ((in4) or (in3) or (in2)) = '1' then
+				state_next(17) <= '1';
+				-- Next values for buffered outputs
+			else
+				if (in1) = '1' then
+					-- Function call: memextrct_0
+					-- Save the origin of the call
+					funccall0_next <= to_unsigned(0, 1);
+					-- This is where the function call leads
+					state_next(4) <= '1';
+					-- Next values for buffered outputs
+					out0_bufn <= '1';
+				else
+					if (in0) = '1' then
+						-- Function call: memextrct_1
+						state_next(2) <= '1';
+						-- Next values for buffered outputs
+						out0_bufn <= '1';
+					else
+						state_next(17) <= '1';
+						-- Next values for buffered outputs
+					end if;
+				end if;
+			end if;
+			-- Assignment of non-buffered outputs
+			out3 <= '1';
+		end if;
+
+		if state_cur(1) = '1' then
+			-- Next state
+			if (in5) = '1' then
+				state_next(1) <= '1';
+				-- Next values for buffered outputs
+				out40_bufn <= '1';
+			else
+				-- Return from function: memextrct_1
+				-- Function call: memextrct_0
+				-- Save the origin of the call
+				funccall0_next <= to_unsigned(1, 1);
+				-- This is where the function call leads
+				state_next(4) <= '1';
+				-- Next values for buffered outputs
+				out0_bufn <= '1';
+			end if;
+			-- Assignment of non-buffered outputs
+			out41 <= '1';
+			out39 <= '1';
+			out35 <= '1';
+		end if;
+
+		if state_cur(2) = '1' then
+			-- Next state
+			state_next(1) <= '1';
+			-- Next values for buffered outputs
+			out40_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out44 <= '1';
+		end if;
+
+		if state_cur(3) = '1' then
+			-- Next state
+			if (in6) = '1' then
+				state_next(3) <= '1';
+				-- Next values for buffered outputs
+				out40_bufn <= '1';
+			else
+				-- Return from function: memextrct_0
+				if funccall0 = 1 then
+					state_next(17) <= '1';
+					-- Next values for buffered outputs
+				end if;
+				-- Return from function: memextrct_0
+				if funccall0 = 0 then
+					state_next(17) <= '1';
+					-- Next values for buffered outputs
+				end if;
+			end if;
+			-- Assignment of non-buffered outputs
+			out41 <= '1';
+			out65 <= '1';
+			out46 <= '1';
+		end if;
+
+		if state_cur(4) = '1' then
+			-- Next state
+			state_next(3) <= '1';
+			-- Next values for buffered outputs
+			out40_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out44 <= '1';
+		end if;
+
+		if state_cur(5) = '1' then
+			-- Next state
+			if (in8) = '1' then
+				state_next(20) <= '1';
+				-- Next values for buffered outputs
+			else
+				if (not (in7)) = '1' then
+					state_next(5) <= '1';
+					-- Next values for buffered outputs
+				else
+					state_next(6) <= '1';
+					-- Next values for buffered outputs
+				end if;
+			end if;
+			-- Assignment of non-buffered outputs
+			out84 <= '1';
+			out81 <= '1';
+			out80 <= '1';
+		end if;
+
+		if state_cur(6) = '1' then
+			-- Next state
+			if (in8) = '1' then
+				state_next(20) <= '1';
+				-- Next values for buffered outputs
+			else
+				if (not (in9)) = '1' then
+					state_next(6) <= '1';
+					-- Next values for buffered outputs
+				else
+					state_next(7) <= '1';
+					-- Next values for buffered outputs
+				end if;
+			end if;
+			-- Assignment of non-buffered outputs
+			out88 <= '1';
+			out86 <= '1';
+			out81 <= '1';
+		end if;
+
+		if state_cur(7) = '1' then
+			-- Next state
+			if (in8) = '1' then
+				state_next(20) <= '1';
+				-- Next values for buffered outputs
+			else
+				if (not (in9)) = '1' then
+					state_next(7) <= '1';
+					-- Next values for buffered outputs
+				else
+					state_next(16) <= '1';
+					-- Next values for buffered outputs
+				end if;
+			end if;
+			-- Assignment of non-buffered outputs
+			out94 <= '1';
+			out93 <= '1';
+			out81 <= '1';
+		end if;
+
+		if state_cur(8) = '1' then
+			-- Next state
+			state_next(14) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out98 <= '1';
+			out97 <= '1';
+		end if;
+
+		if state_cur(9) = '1' then
+			-- Next state
+			if (in10) = '1' then
+				state_next(10) <= '1';
+				-- Next values for buffered outputs
+				out101_bufn <= '1';
+			else
+				state_next(5) <= '1';
+				-- Next values for buffered outputs
+			end if;
+			-- Assignment of non-buffered outputs
+		end if;
+
+		if state_cur(10) = '1' then
+			-- Next state
+			state_next(11) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out102 <= '1';
+		end if;
+
+		if state_cur(11) = '1' then
+			-- Next state
+			state_next(13) <= '1';
+			-- Next values for buffered outputs
+			out172_bufn <= '1';
+			-- Assignment of non-buffered outputs
+			out125 <= '1';
+			out124 <= '1';
+		end if;
+
+		if state_cur(12) = '1' then
+			-- Next state
+			state_next(9) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out159 <= '1';
+			out157 <= '1';
+			out140 <= '1';
+		end if;
+
+		if state_cur(13) = '1' then
+			-- Next state
+			if (in8) = '1' then
+				state_next(20) <= '1';
+				-- Next values for buffered outputs
+			else
+				state_next(9) <= '1';
+				-- Next values for buffered outputs
+			end if;
+			-- Assignment of non-buffered outputs
+			out173 <= '1';
+			out171 <= '1';
+			out160 <= '1';
+			out81 <= '1';
+		end if;
+
+		if state_cur(14) = '1' then
+			-- Next state
+			if (in11) = '1' then
+				state_next(15) <= '1';
+				-- Next values for buffered outputs
+				out172_bufn <= '1';
+				out101_bufn <= '1';
+			else
+				state_next(12) <= '1';
+				-- Next values for buffered outputs
+			end if;
+			-- Assignment of non-buffered outputs
+		end if;
+
+		if state_cur(15) = '1' then
+			-- Next state
+			if (in8) = '1' then
+				state_next(20) <= '1';
+				-- Next values for buffered outputs
+			else
+				state_next(14) <= '1';
+				-- Next values for buffered outputs
+			end if;
+			-- Assignment of non-buffered outputs
+			out173 <= '1';
+			out178 <= '1';
+			out175 <= '1';
+			out81 <= '1';
+		end if;
+
+		if state_cur(16) = '1' then
+			-- Next state
+			state_next(8) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out159 <= '1';
+			out227 <= '1';
+			out225 <= '1';
+		end if;
+
+		if state_cur(17) = '1' then
+			-- Next state
+			if (in12) = '1' then
+				if (in4) = '1' then
+					state_next(5) <= '1';
+					-- Next values for buffered outputs
+				else
+					if (in3) = '1' then
+						state_next(6) <= '1';
+						-- Next values for buffered outputs
+					else
+						if (in2) = '1' then
+							state_next(7) <= '1';
+							-- Next values for buffered outputs
+						else
+							if (in1) = '1' then
+								state_next(13) <= '1';
+								-- Next values for buffered outputs
+								out172_bufn <= '1';
+							else
+								state_next(15) <= '1';
+								-- Next values for buffered outputs
+								out172_bufn <= '1';
+								out101_bufn <= '1';
+							end if;
+						end if;
+					end if;
+				end if;
+			else
+				state_next(18) <= '1';
+				-- Next values for buffered outputs
+			end if;
+			-- Assignment of non-buffered outputs
+			out231 <= '1';
+		end if;
+
+		if state_cur(18) = '1' then
+			-- Next state
+			state_next(18) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+		end if;
+
+		-- Info: This is the init/reset state
+		if state_cur(19) = '1' then
+			-- Next state
+			if (not (in13)) = '1' then
+				state_next(19) <= '1';
+				-- Next values for buffered outputs
+			else
+				if (in12) = '1' then
+					state_next(20) <= '1';
+					-- Next values for buffered outputs
+				else
+					state_next(6) <= '1';
+					-- Next values for buffered outputs
+				end if;
+			end if;
+			-- Assignment of non-buffered outputs
+			out236 <= '1';
+			out235 <= '1';
+		end if;
+
+		if state_cur(20) = '1' then
+			-- Next state
+			state_next(21) <= '1';
+			-- Next values for buffered outputs
+			-- Assignment of non-buffered outputs
+			out44 <= '1';
+		end if;
+
+		if state_cur(21) = '1' then
+			-- Next state
+			if (in14) = '1' then
+				state_next(21) <= '1';
+				-- Next values for buffered outputs
+			else
+				state_next(0) <= '1';
+				-- Next values for buffered outputs
+				out0_bufn <= '1';
+			end if;
+			-- Assignment of non-buffered outputs
+			out41 <= '1';
+			out238 <= '1';
+			out237 <= '1';
+		end if;
+
+		-- Reset input
+		if reset = '1' then
+			-- Set the reset state
+			state_next <= (19 => '1', others => '0');
+			-- Note: Resetting all buffers for outputs here is not necessary.
+			-- It would cost hardware. They will be reset at the next clock front.
+			-- Reset state: set the buffered outputs
+		end if;
+
+	end process;
+
+	-- Assignment of buffered outputs
+
+	out0 <= out0_buf;
+	out40 <= out40_buf;
+	out101 <= out101_buf;
+	out172 <= out172_buf;
+
+end architecture;
+
diff --git a/testsuite/gna/issue50/vector.d/muxb_117.vhd b/testsuite/gna/issue50/vector.d/muxb_117.vhd
new file mode 100644
index 000000000..6f615b120
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/muxb_117.vhd
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity muxb_117 is
+	port (
+		in_sel : in  std_logic;
+		out_data : out std_logic;
+		in_data0 : in  std_logic;
+		in_data1 : in  std_logic
+	);
+end muxb_117;
+
+architecture augh of muxb_117 is
+begin
+
+	out_data <= in_data0 when in_sel = '0' else in_data1;
+
+end architecture;
+
diff --git a/testsuite/gna/issue50/vector.d/muxb_120.vhd b/testsuite/gna/issue50/vector.d/muxb_120.vhd
new file mode 100644
index 000000000..e04495904
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/muxb_120.vhd
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity muxb_120 is
+	port (
+		in_sel : in  std_logic;
+		out_data : out std_logic;
+		in_data0 : in  std_logic;
+		in_data1 : in  std_logic
+	);
+end muxb_120;
+
+architecture augh of muxb_120 is
+begin
+
+	out_data <= in_data0 when in_sel = '0' else in_data1;
+
+end architecture;
+
diff --git a/testsuite/gna/issue50/vector.d/muxb_121.vhd b/testsuite/gna/issue50/vector.d/muxb_121.vhd
new file mode 100644
index 000000000..a87b25e2e
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/muxb_121.vhd
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity muxb_121 is
+	port (
+		in_sel : in  std_logic;
+		out_data : out std_logic;
+		in_data0 : in  std_logic;
+		in_data1 : in  std_logic
+	);
+end muxb_121;
+
+architecture augh of muxb_121 is
+begin
+
+	out_data <= in_data0 when in_sel = '0' else in_data1;
+
+end architecture;
+
diff --git a/testsuite/gna/issue50/vector.d/muxb_123.vhd b/testsuite/gna/issue50/vector.d/muxb_123.vhd
new file mode 100644
index 000000000..150ed33cd
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/muxb_123.vhd
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity muxb_123 is
+	port (
+		in_sel : in  std_logic;
+		out_data : out std_logic;
+		in_data0 : in  std_logic;
+		in_data1 : in  std_logic
+	);
+end muxb_123;
+
+architecture augh of muxb_123 is
+begin
+
+	out_data <= in_data0 when in_sel = '0' else in_data1;
+
+end architecture;
+
diff --git a/testsuite/gna/issue50/vector.d/muxb_124.vhd b/testsuite/gna/issue50/vector.d/muxb_124.vhd
new file mode 100644
index 000000000..72f4f37dc
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/muxb_124.vhd
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity muxb_124 is
+	port (
+		in_sel : in  std_logic;
+		out_data : out std_logic;
+		in_data0 : in  std_logic;
+		in_data1 : in  std_logic
+	);
+end muxb_124;
+
+architecture augh of muxb_124 is
+begin
+
+	out_data <= in_data0 when in_sel = '0' else in_data1;
+
+end architecture;
+
diff --git a/testsuite/gna/issue50/vector.d/muxb_219.vhd b/testsuite/gna/issue50/vector.d/muxb_219.vhd
new file mode 100644
index 000000000..d26913c7c
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/muxb_219.vhd
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity muxb_219 is
+	port (
+		in_sel : in  std_logic;
+		out_data : out std_logic;
+		in_data0 : in  std_logic;
+		in_data1 : in  std_logic
+	);
+end muxb_219;
+
+architecture augh of muxb_219 is
+begin
+
+	out_data <= in_data0 when in_sel = '0' else in_data1;
+
+end architecture;
+
diff --git a/testsuite/gna/issue50/vector.d/pkg_tb.vhd b/testsuite/gna/issue50/vector.d/pkg_tb.vhd
new file mode 100644
index 000000000..89886725d
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/pkg_tb.vhd
@@ -0,0 +1,60 @@
+--test bench written by alban bourge @ tima
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package pkg_tb is
+
+	--fsm state types
+	type state_t is (Rst,Sig_start,Ack_data,Running,Waitfor,Cp_search,Cp_save,Idle,Rst_uut,Rest_ini0,Rest_ini1,Rest,Stop);
+	--context descriptor
+	subtype context_t is std_logic_vector(1 downto 0);
+	--argument width and type of fsm instruction
+	constant ARG_WIDTH : integer := 8;
+	subtype argument_t is unsigned(ARG_WIDTH - 1 downto 0);
+
+	type instruction is 
+		record
+			state       : state_t;
+			context_uut : context_t;
+			arg         : argument_t;
+		end record;
+
+	--reset instruction
+	constant instr_rst : instruction := (state => Rst, context_uut => (others =>'0'), arg => (others =>'0'));
+
+	--ram instruction
+	type ram_instruction is
+		record
+			sel     : std_logic;
+			we      : std_logic;
+			addr_up : std_logic;
+			addr_z  : std_logic;
+		end record;
+
+	constant ram_instr_z : ram_instruction := (sel => '0', we => '0', addr_up => '0', addr_z => '0');
+
+	--assert unit instruction
+	type assert_instruction is
+		record
+			en_feed  : std_logic;
+			en_check : std_logic;
+		end record;
+
+	constant assert_instr_z : assert_instruction := (en_feed => '0', en_check => '0');
+	
+	--size of instruction table defined by PC_SIZE i.e. width of program counter
+	constant PC_SIZE : integer := 5;
+	type table_behavior is array (0 to 2**PC_SIZE - 1) of instruction;
+
+	--constraint fixed by unit under test (augh dependant)
+	--##CONSTRAINTS_START##--
+	subtype stdin_vector is std_logic_vector(31 downto 0);
+	subtype stdout_vector is std_logic_vector(31 downto 0);
+	subtype cp_vector is std_logic_vector(63 downto 0);
+	--##CONSTRAINTS_END##--
+
+	--assert_uut vector number counter size
+	constant VEC_NO_SIZE : integer := 20;
+
+end pkg_tb;
diff --git a/testsuite/gna/issue50/vector.d/prog.vhd b/testsuite/gna/issue50/vector.d/prog.vhd
new file mode 100644
index 000000000..4d7aa42db
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/prog.vhd
@@ -0,0 +1,71 @@
+--test bench written by Alban Bourge @ TIMA
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.pkg_tb.all;
+
+entity prog is
+	port(
+				clock      : in std_logic;
+				reset      : in std_logic;
+				step       : in std_logic;
+				instr_next : out instruction
+			);
+end prog;
+
+architecture rtl of prog is
+
+	signal instr_n : instruction := instr_rst;
+
+	--Table describing fsm behavior
+	constant fsm_behavior : table_behavior := (
+		--##PROGRAM_GOES_DOWN_HERE##--
+		0 => (state => Rst, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
+		1 => (state => Rst, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
+		2 => (state => Sig_start, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
+		3 => (state => Ack_data, context_uut => "01", arg => to_unsigned(2,ARG_WIDTH)),
+		4 => (state => Running, context_uut => "01", arg => to_unsigned(5,ARG_WIDTH)),
+		5 => (state => Cp_search, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
+		6 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
+		7 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
+		8 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
+		9 => (state => Sig_start, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
+		10 => (state => Ack_data, context_uut => "10", arg => to_unsigned(2,ARG_WIDTH)),
+		11 => (state => Running, context_uut => "10", arg => to_unsigned(6,ARG_WIDTH)),
+		12 => (state => Cp_search, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
+		13 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
+		14 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
+		15 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
+		16 => (state => Rest_ini0, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
+		17 => (state => Waitfor, context_uut => "01", arg => to_unsigned(1,ARG_WIDTH)),
+		18 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
+		19 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
+		20 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
+		21 => (state => Rest_ini0, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
+		22 => (state => Waitfor, context_uut => "10", arg => to_unsigned(1,ARG_WIDTH)),
+		23 => (state => Stop, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
+		--##PROGRAM_GOES_OVER_HERE##--
+		others => instr_rst);
+
+	signal pc : unsigned(PC_SIZE - 1 downto 0) := (others => '0');
+
+begin
+
+	drive_state : process (reset,clock) is
+	begin
+		if reset = '1' then
+			instr_n <= instr_rst;
+			pc      <= (others => '0');
+		elsif rising_edge(clock) then
+			if (step = '1') then
+				pc <= pc + 1;
+			end if;
+			instr_n <= fsm_behavior(to_integer(pc));
+		end if;
+	end process drive_state;
+
+	--instr_next <= instr_n;
+	instr_next <= fsm_behavior(to_integer(pc));
+
+end rtl;
diff --git a/testsuite/gna/issue50/vector.d/sub_125.vhd b/testsuite/gna/issue50/vector.d/sub_125.vhd
new file mode 100644
index 000000000..dd458f161
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/sub_125.vhd
@@ -0,0 +1,64 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_125 is
+	port (
+		le : out std_logic;
+		sign : in  std_logic;
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_125;
+
+architecture augh of sub_125 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+	-- Signals to generate the comparison outputs
+	signal msb_abr  : std_logic_vector(2 downto 0);
+	signal tmp_sign : std_logic;
+	signal tmp_eq   : std_logic;
+	signal tmp_le   : std_logic;
+	signal tmp_ge   : std_logic;
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+	-- Other comparison outputs
+
+	-- Temporary signals
+	msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32);
+	tmp_sign <= sign;
+	tmp_eq  <= '1' when in_a = in_b else '0';
+
+	tmp_le <=
+		tmp_eq when msb_abr = "000" or msb_abr = "110" else
+		'1' when msb_abr = "001" or msb_abr = "111" else
+		'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
+		'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
+		'0';
+
+	tmp_ge <=
+		'1' when msb_abr = "000" or msb_abr = "110" else
+		'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
+		'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
+		'0';
+
+	le <= tmp_le;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/sub_145.vhd b/testsuite/gna/issue50/vector.d/sub_145.vhd
new file mode 100644
index 000000000..d8fe56a80
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/sub_145.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_145 is
+	port (
+		result : out std_logic_vector(3 downto 0);
+		in_a : in  std_logic_vector(3 downto 0);
+		in_b : in  std_logic_vector(3 downto 0)
+	);
+end sub_145;
+
+architecture augh of sub_145 is
+
+	signal carry_inA : std_logic_vector(5 downto 0);
+	signal carry_inB : std_logic_vector(5 downto 0);
+	signal carry_res : std_logic_vector(5 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(4 downto 1);
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/sub_189.vhd b/testsuite/gna/issue50/vector.d/sub_189.vhd
new file mode 100644
index 000000000..02a52c0d2
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/sub_189.vhd
@@ -0,0 +1,64 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity sub_189 is
+	port (
+		lt : out std_logic;
+		sign : in  std_logic;
+		result : out std_logic_vector(31 downto 0);
+		in_a : in  std_logic_vector(31 downto 0);
+		in_b : in  std_logic_vector(31 downto 0)
+	);
+end sub_189;
+
+architecture augh of sub_189 is
+
+	signal carry_inA : std_logic_vector(33 downto 0);
+	signal carry_inB : std_logic_vector(33 downto 0);
+	signal carry_res : std_logic_vector(33 downto 0);
+
+	-- Signals to generate the comparison outputs
+	signal msb_abr  : std_logic_vector(2 downto 0);
+	signal tmp_sign : std_logic;
+	signal tmp_eq   : std_logic;
+	signal tmp_le   : std_logic;
+	signal tmp_ge   : std_logic;
+
+begin
+
+	-- To handle the CI input, the operation is '0' - CI
+	-- If CI is not present, the operation is '0' - '0'
+	carry_inA <= '0' & in_a & '0';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
+
+	-- Set the outputs
+	result <= carry_res(32 downto 1);
+
+	-- Other comparison outputs
+
+	-- Temporary signals
+	msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32);
+	tmp_sign <= sign;
+	tmp_eq  <= '1' when in_a = in_b else '0';
+
+	tmp_le <=
+		tmp_eq when msb_abr = "000" or msb_abr = "110" else
+		'1' when msb_abr = "001" or msb_abr = "111" else
+		'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
+		'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
+		'0';
+
+	tmp_ge <=
+		'1' when msb_abr = "000" or msb_abr = "110" else
+		'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
+		'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
+		'0';
+
+	lt <= not(tmp_ge);
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/sync_ram.vhd b/testsuite/gna/issue50/vector.d/sync_ram.vhd
new file mode 100644
index 000000000..83aecf543
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/sync_ram.vhd
@@ -0,0 +1,42 @@
+-- Simple generic RAM Model
+--
+-- +-----------------------------+
+-- |    Copyright 2008 DOULOS    |
+-- |   designer :  JK            |
+-- +-----------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity sync_ram is
+  port (
+    clock   : in  std_logic;
+    we      : in  std_logic;
+    address : in  std_logic_vector;
+    datain  : in  std_logic_vector;
+    dataout : out std_logic_vector
+  );
+end entity sync_ram;
+
+architecture rtl of sync_ram is
+
+   type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(datain'range);
+   signal ram : ram_type;
+   signal read_address : std_logic_vector(address'range);
+
+begin
+
+  ramproc: process(clock) is
+  begin
+    if rising_edge(clock) then
+      if we = '1' then
+        ram(to_integer(unsigned(address))) <= datain;
+      end if;
+      read_address <= address;
+    end if;
+  end process ramproc;
+
+  dataout <= ram(to_integer(unsigned(read_address)));
+
+end architecture rtl;
diff --git a/testsuite/gna/issue50/vector.d/tb.vhd b/testsuite/gna/issue50/vector.d/tb.vhd
new file mode 100644
index 000000000..94a534963
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/tb.vhd
@@ -0,0 +1,44 @@
+--test bench written by Alban Bourge @ TIMA
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.pkg_tb.all;
+
+entity tb is
+end tb;
+
+architecture behavior of tb is
+
+	signal clock      : std_logic  := '0';
+	signal clock_next : std_logic  := '0';
+	signal reset      : std_logic  := '0';
+	--TOP signals
+	signal n_error    : std_logic;
+	signal stopped    : std_logic;
+
+begin
+
+	test : entity work.cp3_test(rtl)
+	port map(
+						clock   => clock,
+						reset   => reset,
+						n_error => n_error,
+						stopped => stopped
+					);
+
+	--clock generator
+	clock <= clock_next after 10 ns;
+	clock_next <= not clock when stopped = '0' else '0';
+
+	reset_proc : process
+	begin
+		reset <= '1';
+		for i in 1 to 5 loop
+			wait until rising_edge(clock);
+		end loop;
+		reset <= '0';
+		wait;
+	end process reset_proc;
+
+end behavior;
diff --git a/testsuite/gna/issue50/vector.d/top.vhd b/testsuite/gna/issue50/vector.d/top.vhd
new file mode 100644
index 000000000..b82be5e72
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/top.vhd
@@ -0,0 +1,2504 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity top is
+	port (
+		clock : in  std_logic;
+		reset : in  std_logic;
+		start : in  std_logic;
+		stdin_data : in  std_logic_vector(31 downto 0);
+		stdin_rdy : out std_logic;
+		stdin_ack : in  std_logic;
+		stdout_data : out std_logic_vector(31 downto 0);
+		stdout_rdy : out std_logic;
+		stdout_ack : in  std_logic;
+		cp_en : in  std_logic;
+		cp_rest : in  std_logic;
+		cp_din : in  std_logic_vector(63 downto 0);
+		cp_dout : out std_logic_vector(63 downto 0);
+		cp_ok : out std_logic
+	);
+end top;
+
+architecture augh of top is
+
+	-- Declaration of components
+
+	component v_split0 is
+		port (
+			clk : in  std_logic;
+			ra0_data : out std_logic_vector(7 downto 0);
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic;
+			wa0_en : in  std_logic;
+			ra0_addr : in  std_logic
+		);
+	end component;
+
+	component v_split1 is
+		port (
+			clk : in  std_logic;
+			ra0_data : out std_logic_vector(7 downto 0);
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic;
+			wa0_en : in  std_logic;
+			ra0_addr : in  std_logic
+		);
+	end component;
+
+	component v_split2 is
+		port (
+			clk : in  std_logic;
+			ra0_data : out std_logic_vector(7 downto 0);
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic;
+			wa0_en : in  std_logic;
+			ra0_addr : in  std_logic
+		);
+	end component;
+
+	component v_split3 is
+		port (
+			clk : in  std_logic;
+			ra0_data : out std_logic_vector(7 downto 0);
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic;
+			wa0_en : in  std_logic;
+			ra0_addr : in  std_logic
+		);
+	end component;
+
+	component v_split4 is
+		port (
+			clk : in  std_logic;
+			ra0_data : out std_logic_vector(7 downto 0);
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic;
+			wa0_en : in  std_logic;
+			ra0_addr : in  std_logic
+		);
+	end component;
+
+	component v_split5 is
+		port (
+			clk : in  std_logic;
+			ra0_data : out std_logic_vector(7 downto 0);
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic;
+			wa0_en : in  std_logic;
+			ra0_addr : in  std_logic
+		);
+	end component;
+
+	component v_split6 is
+		port (
+			clk : in  std_logic;
+			ra0_data : out std_logic_vector(7 downto 0);
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic;
+			wa0_en : in  std_logic;
+			ra0_addr : in  std_logic
+		);
+	end component;
+
+	component v_split7 is
+		port (
+			clk : in  std_logic;
+			ra0_data : out std_logic_vector(7 downto 0);
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic;
+			wa0_en : in  std_logic;
+			ra0_addr : in  std_logic
+		);
+	end component;
+
+	component w_split0 is
+		port (
+			clk : in  std_logic;
+			ra0_data : out std_logic_vector(7 downto 0);
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic;
+			wa0_en : in  std_logic;
+			ra0_addr : in  std_logic
+		);
+	end component;
+
+	component w_split1 is
+		port (
+			clk : in  std_logic;
+			ra0_data : out std_logic_vector(7 downto 0);
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic;
+			wa0_en : in  std_logic;
+			ra0_addr : in  std_logic
+		);
+	end component;
+
+	component w_split2 is
+		port (
+			clk : in  std_logic;
+			ra0_data : out std_logic_vector(7 downto 0);
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic;
+			wa0_en : in  std_logic;
+			ra0_addr : in  std_logic
+		);
+	end component;
+
+	component w_split3 is
+		port (
+			clk : in  std_logic;
+			ra0_data : out std_logic_vector(7 downto 0);
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic;
+			wa0_en : in  std_logic;
+			ra0_addr : in  std_logic
+		);
+	end component;
+
+	component w_split4 is
+		port (
+			clk : in  std_logic;
+			ra0_data : out std_logic_vector(7 downto 0);
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic;
+			wa0_en : in  std_logic;
+			ra0_addr : in  std_logic
+		);
+	end component;
+
+	component w_split5 is
+		port (
+			clk : in  std_logic;
+			ra0_data : out std_logic_vector(7 downto 0);
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic;
+			wa0_en : in  std_logic;
+			ra0_addr : in  std_logic
+		);
+	end component;
+
+	component w_split6 is
+		port (
+			clk : in  std_logic;
+			ra0_data : out std_logic_vector(7 downto 0);
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic;
+			wa0_en : in  std_logic;
+			ra0_addr : in  std_logic
+		);
+	end component;
+
+	component w_split7 is
+		port (
+			clk : in  std_logic;
+			ra0_data : out std_logic_vector(7 downto 0);
+			wa0_data : in  std_logic_vector(7 downto 0);
+			wa0_addr : in  std_logic;
+			wa0_en : in  std_logic;
+			ra0_addr : in  std_logic
+		);
+	end component;
+
+	component add_171 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component cmp_183 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_185 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_193 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_195 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component muxb_120 is
+		port (
+			in_sel : in  std_logic;
+			out_data : out std_logic;
+			in_data0 : in  std_logic;
+			in_data1 : in  std_logic
+		);
+	end component;
+
+	component muxb_124 is
+		port (
+			in_sel : in  std_logic;
+			out_data : out std_logic;
+			in_data0 : in  std_logic;
+			in_data1 : in  std_logic
+		);
+	end component;
+
+	component cmp_128 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_130 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_132 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_136 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_137 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_138 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_139 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_140 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_141 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_142 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component muxb_117 is
+		port (
+			in_sel : in  std_logic;
+			out_data : out std_logic;
+			in_data0 : in  std_logic;
+			in_data1 : in  std_logic
+		);
+	end component;
+
+	component add_118 is
+		port (
+			result : out std_logic_vector(15 downto 0);
+			in_a : in  std_logic_vector(15 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component cmp_119 is
+		port (
+			ne : out std_logic;
+			in0 : in  std_logic_vector(15 downto 0);
+			in1 : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component muxb_121 is
+		port (
+			in_sel : in  std_logic;
+			out_data : out std_logic;
+			in_data0 : in  std_logic;
+			in_data1 : in  std_logic
+		);
+	end component;
+
+	component muxb_123 is
+		port (
+			in_sel : in  std_logic;
+			out_data : out std_logic;
+			in_data0 : in  std_logic;
+			in_data1 : in  std_logic
+		);
+	end component;
+
+	component sub_125 is
+		port (
+			le : out std_logic;
+			sign : in  std_logic;
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component cmp_126 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component add_134 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_145 is
+		port (
+			result : out std_logic_vector(3 downto 0);
+			in_a : in  std_logic_vector(3 downto 0);
+			in_b : in  std_logic_vector(3 downto 0)
+		);
+	end component;
+
+	component cmp_146 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component add_170 is
+		port (
+			result : out std_logic_vector(8 downto 0);
+			in_a : in  std_logic_vector(8 downto 0);
+			in_b : in  std_logic_vector(8 downto 0)
+		);
+	end component;
+
+	component cmp_174 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_176 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_178 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_180 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_187 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component add_188 is
+		port (
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component sub_189 is
+		port (
+			lt : out std_logic;
+			sign : in  std_logic;
+			result : out std_logic_vector(31 downto 0);
+			in_a : in  std_logic_vector(31 downto 0);
+			in_b : in  std_logic_vector(31 downto 0)
+		);
+	end component;
+
+	component cmp_191 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_198 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_200 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_202 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_204 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component add_214 is
+		port (
+			result : out std_logic_vector(7 downto 0);
+			in_a : in  std_logic_vector(7 downto 0);
+			in_b : in  std_logic_vector(7 downto 0)
+		);
+	end component;
+
+	component cmp_215 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component muxb_219 is
+		port (
+			in_sel : in  std_logic;
+			out_data : out std_logic;
+			in_data0 : in  std_logic;
+			in_data1 : in  std_logic
+		);
+	end component;
+
+	component add_220 is
+		port (
+			result : out std_logic_vector(15 downto 0);
+			in_a : in  std_logic_vector(15 downto 0);
+			in_b : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component cmp_221 is
+		port (
+			ne : out std_logic;
+			in0 : in  std_logic_vector(15 downto 0);
+			in1 : in  std_logic_vector(15 downto 0)
+		);
+	end component;
+
+	component cmp_111 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_113 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_216 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_217 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_218 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component fsm_15 is
+		port (
+			clock : in  std_logic;
+			reset : in  std_logic;
+			out3 : out std_logic;
+			out157 : out std_logic;
+			out159 : out std_logic;
+			out160 : out std_logic;
+			out171 : out std_logic;
+			out172 : out std_logic;
+			out173 : out std_logic;
+			out175 : out std_logic;
+			out178 : out std_logic;
+			in0 : in  std_logic;
+			out0 : out std_logic;
+			in5 : in  std_logic;
+			in6 : in  std_logic;
+			in7 : in  std_logic;
+			out35 : out std_logic;
+			out39 : out std_logic;
+			out40 : out std_logic;
+			out41 : out std_logic;
+			out44 : out std_logic;
+			out46 : out std_logic;
+			out140 : out std_logic;
+			in8 : in  std_logic;
+			in9 : in  std_logic;
+			in10 : in  std_logic;
+			in11 : in  std_logic;
+			in12 : in  std_logic;
+			in13 : in  std_logic;
+			in14 : in  std_logic;
+			out65 : out std_logic;
+			in1 : in  std_logic;
+			in2 : in  std_logic;
+			in3 : in  std_logic;
+			in4 : in  std_logic;
+			out225 : out std_logic;
+			out227 : out std_logic;
+			out231 : out std_logic;
+			out235 : out std_logic;
+			out236 : out std_logic;
+			out237 : out std_logic;
+			out238 : out std_logic;
+			out97 : out std_logic;
+			out98 : out std_logic;
+			out101 : out std_logic;
+			out102 : out std_logic;
+			out124 : out std_logic;
+			out125 : out std_logic;
+			out80 : out std_logic;
+			out81 : out std_logic;
+			out84 : out std_logic;
+			out86 : out std_logic;
+			out88 : out std_logic;
+			out93 : out std_logic;
+			out94 : out std_logic
+		);
+	end component;
+
+	component cmp_112 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_114 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_115 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_148 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_150 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_152 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_154 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_156 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_158 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_160 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_127 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_129 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_131 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_133 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	component cmp_135 is
+		port (
+			eq : out std_logic;
+			in0 : in  std_logic_vector(2 downto 0);
+			in1 : in  std_logic_vector(2 downto 0)
+		);
+	end component;
+
+	-- Declaration of signals
+
+	signal sig_clock : std_logic;
+	signal sig_reset : std_logic;
+	signal sig_222 : std_logic;
+	signal sig_223 : std_logic;
+	signal sig_224 : std_logic;
+	signal sig_225 : std_logic;
+	signal sig_226 : std_logic;
+	signal sig_227 : std_logic;
+	signal sig_228 : std_logic;
+	signal sig_229 : std_logic;
+	signal sig_230 : std_logic;
+	signal sig_231 : std_logic;
+	signal sig_232 : std_logic;
+	signal sig_233 : std_logic;
+	signal sig_234 : std_logic;
+	signal sig_235 : std_logic;
+	signal sig_236 : std_logic;
+	signal sig_237 : std_logic;
+	signal sig_238 : std_logic;
+	signal sig_239 : std_logic;
+	signal sig_240 : std_logic;
+	signal sig_241 : std_logic;
+	signal sig_242 : std_logic;
+	signal sig_243 : std_logic;
+	signal sig_244 : std_logic;
+	signal sig_245 : std_logic;
+	signal sig_246 : std_logic;
+	signal sig_247 : std_logic;
+	signal sig_248 : std_logic;
+	signal sig_249 : std_logic;
+	signal sig_250 : std_logic;
+	signal sig_251 : std_logic;
+	signal sig_252 : std_logic;
+	signal sig_253 : std_logic;
+	signal sig_254 : std_logic;
+	signal sig_255 : std_logic;
+	signal sig_256 : std_logic;
+	signal sig_257 : std_logic;
+	signal sig_258 : std_logic;
+	signal sig_259 : std_logic;
+	signal sig_260 : std_logic;
+	signal sig_261 : std_logic;
+	signal sig_262 : std_logic;
+	signal sig_263 : std_logic;
+	signal sig_264 : std_logic;
+	signal sig_265 : std_logic;
+	signal sig_266 : std_logic;
+	signal sig_267 : std_logic;
+	signal sig_268 : std_logic;
+	signal sig_269 : std_logic;
+	signal sig_270 : std_logic;
+	signal sig_271 : std_logic;
+	signal sig_272 : std_logic;
+	signal sig_273 : std_logic;
+	signal sig_274 : std_logic;
+	signal sig_275 : std_logic;
+	signal sig_276 : std_logic;
+	signal sig_277 : std_logic;
+	signal sig_278 : std_logic;
+	signal augh_test_0 : std_logic;
+	signal augh_test_1 : std_logic;
+	signal sig_start : std_logic;
+	signal test_cp_4_6 : std_logic;
+	signal test_cp_3_7 : std_logic;
+	signal test_cp_0_8 : std_logic;
+	signal test_cp_1_9 : std_logic;
+	signal test_cp_2_10 : std_logic;
+	signal memextrct_loop_sig_13 : std_logic;
+	signal memextrct_loop_sig_14 : std_logic;
+	signal psc_loop_sig_12 : std_logic;
+	signal sig_279 : std_logic_vector(15 downto 0);
+	signal sig_280 : std_logic;
+	signal sig_281 : std_logic;
+	signal sig_282 : std_logic_vector(7 downto 0);
+	signal sig_283 : std_logic;
+	signal sig_284 : std_logic;
+	signal sig_285 : std_logic;
+	signal sig_286 : std_logic;
+	signal sig_287 : std_logic;
+	signal sig_288 : std_logic_vector(31 downto 0);
+	signal sig_289 : std_logic_vector(31 downto 0);
+	signal sig_290 : std_logic;
+	signal sig_291 : std_logic;
+	signal sig_292 : std_logic;
+	signal sig_293 : std_logic;
+	signal sig_294 : std_logic;
+	signal sig_295 : std_logic_vector(8 downto 0);
+	signal sig_296 : std_logic;
+	signal sig_297 : std_logic_vector(3 downto 0);
+	signal sig_298 : std_logic_vector(31 downto 0);
+	signal sig_299 : std_logic;
+	signal sig_300 : std_logic_vector(31 downto 0);
+	signal sig_301 : std_logic;
+	signal sig_302 : std_logic;
+	signal sig_303 : std_logic;
+	signal sig_304 : std_logic_vector(15 downto 0);
+	signal sig_305 : std_logic;
+	signal sig_306 : std_logic;
+	signal sig_307 : std_logic;
+	signal sig_308 : std_logic;
+	signal sig_309 : std_logic;
+	signal sig_310 : std_logic;
+	signal sig_311 : std_logic;
+	signal sig_312 : std_logic;
+	signal sig_313 : std_logic;
+	signal sig_314 : std_logic;
+	signal sig_315 : std_logic;
+	signal sig_316 : std_logic;
+	signal sig_317 : std_logic;
+	signal sig_318 : std_logic;
+	signal sig_319 : std_logic;
+	signal sig_320 : std_logic;
+	signal sig_321 : std_logic;
+	signal sig_322 : std_logic_vector(31 downto 0);
+	signal sig_323 : std_logic_vector(7 downto 0);
+	signal sig_324 : std_logic_vector(7 downto 0);
+	signal sig_325 : std_logic_vector(7 downto 0);
+	signal sig_326 : std_logic_vector(7 downto 0);
+	signal sig_327 : std_logic_vector(7 downto 0);
+	signal sig_328 : std_logic_vector(7 downto 0);
+	signal sig_329 : std_logic_vector(7 downto 0);
+	signal sig_330 : std_logic_vector(7 downto 0);
+	signal sig_331 : std_logic_vector(7 downto 0);
+	signal sig_332 : std_logic_vector(7 downto 0);
+	signal sig_333 : std_logic_vector(7 downto 0);
+	signal sig_334 : std_logic_vector(7 downto 0);
+	signal sig_335 : std_logic_vector(7 downto 0);
+	signal sig_336 : std_logic_vector(7 downto 0);
+	signal sig_337 : std_logic_vector(7 downto 0);
+	signal sig_338 : std_logic_vector(7 downto 0);
+	signal sig_339 : std_logic_vector(31 downto 0);
+	signal sig_340 : std_logic_vector(8 downto 0);
+	signal sig_341 : std_logic_vector(8 downto 0);
+	signal sig_342 : std_logic_vector(31 downto 0);
+
+	-- Other inlined components
+
+	signal mux_25 : std_logic;
+	signal mux_26 : std_logic_vector(2 downto 0);
+	signal mux_27 : std_logic;
+	signal mux_28 : std_logic_vector(2 downto 0);
+	signal mux_29 : std_logic;
+	signal mux_30 : std_logic_vector(15 downto 0);
+	signal mux_31 : std_logic;
+	signal mux_32 : std_logic_vector(7 downto 0);
+	signal mux_33 : std_logic;
+	signal mux_34 : std_logic;
+	signal mux_35 : std_logic;
+	signal mux_36 : std_logic_vector(7 downto 0);
+	signal mux_37 : std_logic;
+	signal mux_38 : std_logic;
+	signal mux_39 : std_logic;
+	signal mux_40 : std_logic_vector(7 downto 0);
+	signal mux_41 : std_logic;
+	signal mux_42 : std_logic;
+	signal mux_43 : std_logic;
+	signal augh_main_max_iter : std_logic_vector(31 downto 0) := (others => '0');
+	signal augh_main_std_addition : std_logic_vector(31 downto 0) := (others => '0');
+	signal augh_main_result : std_logic_vector(31 downto 0) := (others => '0');
+	signal augh_main_i : std_logic_vector(31 downto 0) := (others => '0');
+	signal mux_23 : std_logic;
+	signal mux_24 : std_logic;
+	signal mux_44 : std_logic_vector(7 downto 0);
+	signal mux_45 : std_logic;
+	signal mux_46 : std_logic;
+	signal mux_47 : std_logic;
+	signal mux_48 : std_logic_vector(7 downto 0);
+	signal mux_49 : std_logic;
+	signal mux_50 : std_logic;
+	signal mux_51 : std_logic;
+	signal mux_52 : std_logic_vector(7 downto 0);
+	signal mux_53 : std_logic;
+	signal mux_54 : std_logic;
+	signal mux_55 : std_logic;
+	signal mux_56 : std_logic_vector(7 downto 0);
+	signal mux_57 : std_logic;
+	signal mux_58 : std_logic;
+	signal mux_59 : std_logic;
+	signal mux_60 : std_logic_vector(7 downto 0);
+	signal mux_61 : std_logic;
+	signal mux_62 : std_logic;
+	signal mux_63 : std_logic;
+	signal mux_64 : std_logic_vector(31 downto 0);
+	signal mux_65 : std_logic;
+	signal mux_66 : std_logic_vector(31 downto 0);
+	signal mux_67 : std_logic;
+	signal mux_68 : std_logic_vector(31 downto 0);
+	signal mux_69 : std_logic;
+	signal mux_70 : std_logic_vector(31 downto 0);
+	signal mux_71 : std_logic;
+	signal mux_72 : std_logic_vector(7 downto 0);
+	signal mux_73 : std_logic;
+	signal mux_74 : std_logic;
+	signal mux_75 : std_logic;
+	signal mux_76 : std_logic_vector(7 downto 0);
+	signal mux_77 : std_logic;
+	signal mux_78 : std_logic;
+	signal mux_79 : std_logic;
+	signal mux_80 : std_logic_vector(7 downto 0);
+	signal mux_20 : std_logic;
+	signal mux_22 : std_logic;
+	signal and_163 : std_logic_vector(7 downto 0);
+	signal and_164 : std_logic_vector(7 downto 0);
+	signal and_165 : std_logic_vector(7 downto 0);
+	signal and_166 : std_logic_vector(7 downto 0);
+	signal and_167 : std_logic_vector(7 downto 0);
+	signal and_168 : std_logic_vector(7 downto 0);
+	signal and_169 : std_logic_vector(7 downto 0);
+	signal and_182 : std_logic_vector(7 downto 0);
+	signal and_184 : std_logic_vector(7 downto 0);
+	signal and_186 : std_logic_vector(7 downto 0);
+	signal and_192 : std_logic;
+	signal and_194 : std_logic;
+	signal and_196 : std_logic;
+	signal mux_81 : std_logic;
+	signal mux_82 : std_logic;
+	signal mux_83 : std_logic;
+	signal mux_84 : std_logic_vector(7 downto 0);
+	signal mux_85 : std_logic;
+	signal mux_86 : std_logic;
+	signal mux_87 : std_logic;
+	signal mux_88 : std_logic_vector(7 downto 0);
+	signal mux_89 : std_logic;
+	signal mux_90 : std_logic;
+	signal mux_91 : std_logic;
+	signal mux_92 : std_logic_vector(7 downto 0);
+	signal mux_93 : std_logic;
+	signal mux_94 : std_logic;
+	signal mux_95 : std_logic;
+	signal mux_96 : std_logic_vector(7 downto 0);
+	signal mux_97 : std_logic;
+	signal mux_98 : std_logic;
+	signal mux_99 : std_logic;
+	signal mux_100 : std_logic_vector(7 downto 0);
+	signal mux_101 : std_logic;
+	signal mux_102 : std_logic;
+	signal mux_103 : std_logic;
+	signal mux_106 : std_logic;
+	signal mux_108 : std_logic;
+	signal mux_109 : std_logic_vector(63 downto 0);
+	signal mux_110 : std_logic;
+	signal and_116 : std_logic;
+	signal not_122 : std_logic;
+	signal or_143 : std_logic_vector(7 downto 0);
+	signal and_147 : std_logic_vector(7 downto 0);
+	signal and_149 : std_logic_vector(7 downto 0);
+	signal and_151 : std_logic_vector(7 downto 0);
+	signal and_153 : std_logic_vector(7 downto 0);
+	signal and_155 : std_logic_vector(7 downto 0);
+	signal and_157 : std_logic_vector(7 downto 0);
+	signal and_159 : std_logic_vector(7 downto 0);
+	signal or_161 : std_logic_vector(7 downto 0);
+	signal and_162 : std_logic_vector(7 downto 0);
+	signal or_172 : std_logic_vector(7 downto 0);
+	signal and_173 : std_logic_vector(7 downto 0);
+	signal and_175 : std_logic_vector(7 downto 0);
+	signal and_177 : std_logic_vector(7 downto 0);
+	signal and_179 : std_logic_vector(7 downto 0);
+	signal and_181 : std_logic_vector(7 downto 0);
+	signal and_190 : std_logic;
+	signal and_197 : std_logic;
+	signal and_199 : std_logic;
+	signal and_201 : std_logic;
+	signal and_203 : std_logic;
+	signal or_205 : std_logic_vector(7 downto 0);
+	signal and_206 : std_logic_vector(7 downto 0);
+	signal and_207 : std_logic_vector(7 downto 0);
+	signal and_208 : std_logic_vector(7 downto 0);
+	signal and_209 : std_logic_vector(7 downto 0);
+	signal and_210 : std_logic_vector(7 downto 0);
+	signal and_211 : std_logic_vector(7 downto 0);
+	signal and_212 : std_logic_vector(7 downto 0);
+	signal and_213 : std_logic_vector(7 downto 0);
+	signal psc_loop_reg_3 : std_logic_vector(15 downto 0) := (others => '0');
+	signal cp_id_reg_4 : std_logic_vector(2 downto 0) := (others => '0');
+	signal cp_id_reg_stable_5 : std_logic_vector(2 downto 0) := (others => '0');
+	signal psc_stuff_reg_11 : std_logic_vector(60 downto 0) := "0000000000000000000000000000000000000000000000000000000000000";
+	signal and_144 : std_logic_vector(7 downto 0);
+
+	-- This utility function is used for to generate concatenations of std_logic
+
+	-- Little utility function to ease concatenation of an std_logic
+	-- and explicitely return an std_logic_vector
+	function repeat(N: natural; B: std_logic) return std_logic_vector is
+		variable result: std_logic_vector(N-1 downto 0);
+	begin
+		result := (others => B);
+		return result;
+	end;
+
+begin
+
+	-- Instantiation of components
+
+	v_split0_i : v_split0 port map (
+		clk => sig_clock,
+		ra0_data => sig_338,
+		wa0_data => mux_100,
+		wa0_addr => mux_101,
+		wa0_en => mux_102,
+		ra0_addr => mux_103
+	);
+
+	v_split1_i : v_split1 port map (
+		clk => sig_clock,
+		ra0_data => sig_337,
+		wa0_data => mux_96,
+		wa0_addr => mux_97,
+		wa0_en => mux_98,
+		ra0_addr => mux_99
+	);
+
+	v_split2_i : v_split2 port map (
+		clk => sig_clock,
+		ra0_data => sig_336,
+		wa0_data => mux_92,
+		wa0_addr => mux_93,
+		wa0_en => mux_94,
+		ra0_addr => mux_95
+	);
+
+	v_split3_i : v_split3 port map (
+		clk => sig_clock,
+		ra0_data => sig_335,
+		wa0_data => mux_88,
+		wa0_addr => mux_89,
+		wa0_en => mux_90,
+		ra0_addr => mux_91
+	);
+
+	v_split4_i : v_split4 port map (
+		clk => sig_clock,
+		ra0_data => sig_334,
+		wa0_data => mux_84,
+		wa0_addr => mux_85,
+		wa0_en => mux_86,
+		ra0_addr => mux_87
+	);
+
+	v_split5_i : v_split5 port map (
+		clk => sig_clock,
+		ra0_data => sig_333,
+		wa0_data => mux_80,
+		wa0_addr => mux_81,
+		wa0_en => mux_82,
+		ra0_addr => mux_83
+	);
+
+	v_split6_i : v_split6 port map (
+		clk => sig_clock,
+		ra0_data => sig_332,
+		wa0_data => mux_76,
+		wa0_addr => mux_77,
+		wa0_en => mux_78,
+		ra0_addr => mux_79
+	);
+
+	v_split7_i : v_split7 port map (
+		clk => sig_clock,
+		ra0_data => sig_331,
+		wa0_data => mux_72,
+		wa0_addr => mux_73,
+		wa0_en => mux_74,
+		ra0_addr => mux_75
+	);
+
+	w_split0_i : w_split0 port map (
+		clk => sig_clock,
+		ra0_data => sig_330,
+		wa0_data => mux_60,
+		wa0_addr => mux_61,
+		wa0_en => mux_62,
+		ra0_addr => mux_63
+	);
+
+	w_split1_i : w_split1 port map (
+		clk => sig_clock,
+		ra0_data => sig_329,
+		wa0_data => mux_56,
+		wa0_addr => mux_57,
+		wa0_en => mux_58,
+		ra0_addr => mux_59
+	);
+
+	w_split2_i : w_split2 port map (
+		clk => sig_clock,
+		ra0_data => sig_328,
+		wa0_data => mux_52,
+		wa0_addr => mux_53,
+		wa0_en => mux_54,
+		ra0_addr => mux_55
+	);
+
+	w_split3_i : w_split3 port map (
+		clk => sig_clock,
+		ra0_data => sig_327,
+		wa0_data => mux_48,
+		wa0_addr => mux_49,
+		wa0_en => mux_50,
+		ra0_addr => mux_51
+	);
+
+	w_split4_i : w_split4 port map (
+		clk => sig_clock,
+		ra0_data => sig_326,
+		wa0_data => mux_44,
+		wa0_addr => mux_45,
+		wa0_en => mux_46,
+		ra0_addr => mux_47
+	);
+
+	w_split5_i : w_split5 port map (
+		clk => sig_clock,
+		ra0_data => sig_325,
+		wa0_data => mux_40,
+		wa0_addr => mux_41,
+		wa0_en => mux_42,
+		ra0_addr => mux_43
+	);
+
+	w_split6_i : w_split6 port map (
+		clk => sig_clock,
+		ra0_data => sig_324,
+		wa0_data => mux_36,
+		wa0_addr => mux_37,
+		wa0_en => mux_38,
+		ra0_addr => mux_39
+	);
+
+	w_split7_i : w_split7 port map (
+		clk => sig_clock,
+		ra0_data => sig_323,
+		wa0_data => mux_32,
+		wa0_addr => mux_33,
+		wa0_en => mux_34,
+		ra0_addr => mux_35
+	);
+
+	add_171_i : add_171 port map (
+		result => sig_322,
+		in_a => sig_342,
+		in_b => augh_main_std_addition
+	);
+
+	cmp_183_i : cmp_183 port map (
+		eq => sig_321,
+		in0 => "010",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	cmp_185_i : cmp_185 port map (
+		eq => sig_320,
+		in0 => "001",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	cmp_193_i : cmp_193 port map (
+		eq => sig_319,
+		in0 => "110",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	cmp_195_i : cmp_195 port map (
+		eq => sig_318,
+		in0 => "101",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	muxb_120_i : muxb_120 port map (
+		in_sel => cp_en,
+		out_data => sig_317,
+		in_data0 => '0',
+		in_data1 => '1'
+	);
+
+	muxb_124_i : muxb_124 port map (
+		in_sel => not_122,
+		out_data => sig_316,
+		in_data0 => '0',
+		in_data1 => '1'
+	);
+
+	cmp_128_i : cmp_128 port map (
+		eq => sig_315,
+		in0 => "101",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	cmp_130_i : cmp_130 port map (
+		eq => sig_314,
+		in0 => "011",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	cmp_132_i : cmp_132 port map (
+		eq => sig_313,
+		in0 => "001",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	cmp_136_i : cmp_136 port map (
+		eq => sig_312,
+		in0 => "110",
+		in1 => sig_298(2 downto 0)
+	);
+
+	cmp_137_i : cmp_137 port map (
+		eq => sig_311,
+		in0 => "101",
+		in1 => sig_298(2 downto 0)
+	);
+
+	cmp_138_i : cmp_138 port map (
+		eq => sig_310,
+		in0 => "100",
+		in1 => sig_298(2 downto 0)
+	);
+
+	cmp_139_i : cmp_139 port map (
+		eq => sig_309,
+		in0 => "011",
+		in1 => sig_298(2 downto 0)
+	);
+
+	cmp_140_i : cmp_140 port map (
+		eq => sig_308,
+		in0 => "010",
+		in1 => sig_298(2 downto 0)
+	);
+
+	cmp_141_i : cmp_141 port map (
+		eq => sig_307,
+		in0 => "001",
+		in1 => sig_298(2 downto 0)
+	);
+
+	cmp_142_i : cmp_142 port map (
+		eq => sig_306,
+		in0 => "000",
+		in1 => sig_298(2 downto 0)
+	);
+
+	muxb_117_i : muxb_117 port map (
+		in_sel => cp_en,
+		out_data => sig_305,
+		in_data0 => '0',
+		in_data1 => '1'
+	);
+
+	add_118_i : add_118 port map (
+		result => sig_304,
+		in_a => psc_loop_reg_3,
+		in_b => "0000000000000001"
+	);
+
+	cmp_119_i : cmp_119 port map (
+		ne => sig_303,
+		in0 => "0000000000000001",
+		in1 => psc_loop_reg_3
+	);
+
+	muxb_121_i : muxb_121 port map (
+		in_sel => not_122,
+		out_data => sig_302,
+		in_data0 => '0',
+		in_data1 => '1'
+	);
+
+	muxb_123_i : muxb_123 port map (
+		in_sel => not_122,
+		out_data => sig_301,
+		in_data0 => '0',
+		in_data1 => '1'
+	);
+
+	sub_125_i : sub_125 port map (
+		le => augh_test_1,
+		sign => '1',
+		result => sig_300,
+		in_a => augh_main_i,
+		in_b => "00000000000000000000000000000111"
+	);
+
+	cmp_126_i : cmp_126 port map (
+		eq => sig_299,
+		in0 => "111",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	add_134_i : add_134 port map (
+		result => sig_298,
+		in_a => augh_main_i,
+		in_b => "00000000000000000000000000000001"
+	);
+
+	sub_145_i : sub_145 port map (
+		result => sig_297,
+		in_a => augh_main_max_iter(3 downto 0),
+		in_b => "0001"
+	);
+
+	cmp_146_i : cmp_146 port map (
+		eq => sig_296,
+		in0 => "111",
+		in1 => sig_297(2 downto 0)
+	);
+
+	add_170_i : add_170 port map (
+		result => sig_295,
+		in_a => sig_341,
+		in_b => sig_340
+	);
+
+	cmp_174_i : cmp_174 port map (
+		eq => sig_294,
+		in0 => "111",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	cmp_176_i : cmp_176 port map (
+		eq => sig_293,
+		in0 => "110",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	cmp_178_i : cmp_178 port map (
+		eq => sig_292,
+		in0 => "101",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	cmp_180_i : cmp_180 port map (
+		eq => sig_291,
+		in0 => "100",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	cmp_187_i : cmp_187 port map (
+		eq => sig_290,
+		in0 => "000",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	add_188_i : add_188 port map (
+		result => sig_289,
+		in_a => augh_main_result,
+		in_b => sig_339
+	);
+
+	sub_189_i : sub_189 port map (
+		lt => augh_test_0,
+		sign => '1',
+		result => sig_288,
+		in_a => augh_main_i,
+		in_b => augh_main_max_iter
+	);
+
+	cmp_191_i : cmp_191 port map (
+		eq => sig_287,
+		in0 => "111",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	cmp_198_i : cmp_198 port map (
+		eq => sig_286,
+		in0 => "011",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	cmp_200_i : cmp_200 port map (
+		eq => sig_285,
+		in0 => "010",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	cmp_202_i : cmp_202 port map (
+		eq => sig_284,
+		in0 => "001",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	cmp_204_i : cmp_204 port map (
+		eq => sig_283,
+		in0 => "000",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	add_214_i : add_214 port map (
+		result => sig_282,
+		in_a => or_205,
+		in_b => augh_main_i(7 downto 0)
+	);
+
+	cmp_215_i : cmp_215 port map (
+		eq => sig_281,
+		in0 => "001",
+		in1 => cp_id_reg_stable_5
+	);
+
+	muxb_219_i : muxb_219 port map (
+		in_sel => cp_en,
+		out_data => sig_280,
+		in_data0 => '0',
+		in_data1 => '1'
+	);
+
+	add_220_i : add_220 port map (
+		result => sig_279,
+		in_a => psc_loop_reg_3,
+		in_b => "0000000000000001"
+	);
+
+	cmp_221_i : cmp_221 port map (
+		ne => psc_loop_sig_12,
+		in0 => "0000000000000010",
+		in1 => psc_loop_reg_3
+	);
+
+	cmp_111_i : cmp_111 port map (
+		eq => test_cp_2_10,
+		in0 => "010",
+		in1 => cp_id_reg_stable_5
+	);
+
+	cmp_113_i : cmp_113 port map (
+		eq => sig_278,
+		in0 => "000",
+		in1 => cp_id_reg_stable_5
+	);
+
+	cmp_216_i : cmp_216 port map (
+		eq => sig_277,
+		in0 => "000",
+		in1 => cp_id_reg_stable_5
+	);
+
+	cmp_217_i : cmp_217 port map (
+		eq => sig_276,
+		in0 => "011",
+		in1 => cp_id_reg_stable_5
+	);
+
+	cmp_218_i : cmp_218 port map (
+		eq => sig_275,
+		in0 => "100",
+		in1 => cp_id_reg_stable_5
+	);
+
+	fsm_15_i : fsm_15 port map (
+		clock => sig_clock,
+		reset => sig_reset,
+		out3 => sig_274,
+		out157 => sig_273,
+		out159 => sig_272,
+		out160 => sig_271,
+		out171 => sig_270,
+		out172 => sig_269,
+		out173 => sig_268,
+		out175 => sig_267,
+		out178 => sig_266,
+		in0 => test_cp_4_6,
+		out0 => sig_265,
+		in5 => memextrct_loop_sig_14,
+		in6 => memextrct_loop_sig_13,
+		in7 => stdout_ack,
+		out35 => sig_264,
+		out39 => sig_263,
+		out40 => sig_262,
+		out41 => sig_261,
+		out44 => sig_260,
+		out46 => sig_259,
+		out140 => sig_258,
+		in8 => cp_en,
+		in9 => stdin_ack,
+		in10 => augh_test_1,
+		in11 => augh_test_0,
+		in12 => cp_rest,
+		in13 => sig_start,
+		in14 => psc_loop_sig_12,
+		out65 => sig_257,
+		in1 => test_cp_3_7,
+		in2 => test_cp_0_8,
+		in3 => test_cp_1_9,
+		in4 => test_cp_2_10,
+		out225 => sig_256,
+		out227 => sig_255,
+		out231 => sig_254,
+		out235 => sig_253,
+		out236 => sig_252,
+		out237 => sig_251,
+		out238 => sig_250,
+		out97 => sig_249,
+		out98 => sig_248,
+		out101 => sig_247,
+		out102 => sig_246,
+		out124 => sig_245,
+		out125 => sig_244,
+		out80 => sig_243,
+		out81 => sig_242,
+		out84 => sig_241,
+		out86 => sig_240,
+		out88 => sig_239,
+		out93 => sig_238,
+		out94 => sig_237
+	);
+
+	cmp_112_i : cmp_112 port map (
+		eq => sig_236,
+		in0 => "001",
+		in1 => cp_id_reg_stable_5
+	);
+
+	cmp_114_i : cmp_114 port map (
+		eq => sig_235,
+		in0 => "011",
+		in1 => cp_id_reg_stable_5
+	);
+
+	cmp_115_i : cmp_115 port map (
+		eq => sig_234,
+		in0 => "100",
+		in1 => cp_id_reg_stable_5
+	);
+
+	cmp_148_i : cmp_148 port map (
+		eq => sig_233,
+		in0 => "110",
+		in1 => sig_297(2 downto 0)
+	);
+
+	cmp_150_i : cmp_150 port map (
+		eq => sig_232,
+		in0 => "101",
+		in1 => sig_297(2 downto 0)
+	);
+
+	cmp_152_i : cmp_152 port map (
+		eq => sig_231,
+		in0 => "100",
+		in1 => sig_297(2 downto 0)
+	);
+
+	cmp_154_i : cmp_154 port map (
+		eq => sig_230,
+		in0 => "011",
+		in1 => sig_297(2 downto 0)
+	);
+
+	cmp_156_i : cmp_156 port map (
+		eq => sig_229,
+		in0 => "010",
+		in1 => sig_297(2 downto 0)
+	);
+
+	cmp_158_i : cmp_158 port map (
+		eq => sig_228,
+		in0 => "001",
+		in1 => sig_297(2 downto 0)
+	);
+
+	cmp_160_i : cmp_160 port map (
+		eq => sig_227,
+		in0 => "000",
+		in1 => sig_297(2 downto 0)
+	);
+
+	cmp_127_i : cmp_127 port map (
+		eq => sig_226,
+		in0 => "110",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	cmp_129_i : cmp_129 port map (
+		eq => sig_225,
+		in0 => "100",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	cmp_131_i : cmp_131 port map (
+		eq => sig_224,
+		in0 => "010",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	cmp_133_i : cmp_133 port map (
+		eq => sig_223,
+		in0 => "000",
+		in1 => augh_main_i(2 downto 0)
+	);
+
+	cmp_135_i : cmp_135 port map (
+		eq => sig_222,
+		in0 => "111",
+		in1 => sig_298(2 downto 0)
+	);
+
+	-- Behaviour of component 'mux_25' model 'mux'
+	mux_25 <=
+		(sig_274 and sig_234) or
+		(sig_254 and sig_275);
+
+	-- Behaviour of component 'mux_26' model 'mux'
+	mux_26 <=
+		(repeat(3, sig_243) and "010") or
+		(repeat(3, sig_253) and cp_din(2 downto 0)) or
+		(repeat(3, sig_240) and "001") or
+		(repeat(3, sig_271) and "011") or
+		(repeat(3, sig_267) and "100");
+
+	-- Behaviour of component 'mux_27' model 'mux'
+	mux_27 <=
+		(sig_242 and '1') or
+		(sig_252 and cp_rest);
+
+	-- Behaviour of component 'mux_28' model 'mux'
+	mux_28 <=
+		(repeat(3, sig_243) and "010") or
+		(repeat(3, sig_251) and augh_main_result(2 downto 0)) or
+		(repeat(3, sig_240) and "001") or
+		(repeat(3, sig_271) and "011") or
+		(repeat(3, sig_267) and "100");
+
+	-- Behaviour of component 'mux_29' model 'mux'
+	mux_29 <=
+		(sig_242 and '1') or
+		(sig_250 and cp_en);
+
+	-- Behaviour of component 'mux_30' model 'mux'
+	mux_30 <=
+		(repeat(16, sig_262) and sig_304) or
+		(repeat(16, sig_251) and sig_279);
+
+	-- Behaviour of component 'mux_31' model 'mux'
+	mux_31 <=
+		(sig_261 and cp_en) or
+		(sig_260 and '1');
+
+	-- Behaviour of component 'mux_32' model 'mux'
+	mux_32 <=
+		(repeat(8, sig_263) and cp_din(7 downto 0)) or
+		(repeat(8, sig_267) and sig_282);
+
+	-- Behaviour of component 'mux_33' model 'mux'
+	mux_33 <=
+		(sig_263 and psc_loop_reg_3(0)) or
+		(sig_267 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_34' model 'mux'
+	mux_34 <=
+		(sig_264 and and_116) or
+		(sig_266 and and_190);
+
+	-- Behaviour of component 'mux_35' model 'mux'
+	mux_35 <=
+		(sig_263 and psc_loop_reg_3(0)) or
+		(sig_258 and sig_297(3)) or
+		(sig_267 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_36' model 'mux'
+	mux_36 <=
+		(repeat(8, sig_263) and cp_din(15 downto 8)) or
+		(repeat(8, sig_267) and sig_282);
+
+	-- Behaviour of component 'mux_37' model 'mux'
+	mux_37 <=
+		(sig_263 and psc_loop_reg_3(0)) or
+		(sig_267 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_38' model 'mux'
+	mux_38 <=
+		(sig_264 and and_116) or
+		(sig_266 and and_192);
+
+	-- Behaviour of component 'mux_39' model 'mux'
+	mux_39 <=
+		(sig_263 and psc_loop_reg_3(0)) or
+		(sig_258 and sig_297(3)) or
+		(sig_267 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_40' model 'mux'
+	mux_40 <=
+		(repeat(8, sig_263) and cp_din(23 downto 16)) or
+		(repeat(8, sig_267) and sig_282);
+
+	-- Behaviour of component 'mux_41' model 'mux'
+	mux_41 <=
+		(sig_263 and psc_loop_reg_3(0)) or
+		(sig_267 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_42' model 'mux'
+	mux_42 <=
+		(sig_264 and and_116) or
+		(sig_266 and and_194);
+
+	-- Behaviour of component 'mux_43' model 'mux'
+	mux_43 <=
+		(sig_263 and psc_loop_reg_3(0)) or
+		(sig_258 and sig_297(3)) or
+		(sig_267 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_23' model 'mux'
+	mux_23 <=
+		(sig_274 and sig_278) or
+		(sig_254 and sig_277);
+
+	-- Behaviour of component 'mux_24' model 'mux'
+	mux_24 <=
+		(sig_274 and sig_235) or
+		(sig_254 and sig_276);
+
+	-- Behaviour of component 'mux_44' model 'mux'
+	mux_44 <=
+		(repeat(8, sig_263) and cp_din(31 downto 24)) or
+		(repeat(8, sig_267) and sig_282);
+
+	-- Behaviour of component 'mux_45' model 'mux'
+	mux_45 <=
+		(sig_263 and psc_loop_reg_3(0)) or
+		(sig_249 and '1') or
+		(sig_267 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_46' model 'mux'
+	mux_46 <=
+		(sig_264 and and_116) or
+		(sig_248 and '1') or
+		(sig_266 and and_196);
+
+	-- Behaviour of component 'mux_47' model 'mux'
+	mux_47 <=
+		(sig_263 and psc_loop_reg_3(0)) or
+		(sig_258 and sig_297(3)) or
+		(sig_267 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_48' model 'mux'
+	mux_48 <=
+		(repeat(8, sig_263) and cp_din(39 downto 32)) or
+		(repeat(8, sig_267) and sig_282);
+
+	-- Behaviour of component 'mux_49' model 'mux'
+	mux_49 <=
+		(sig_263 and psc_loop_reg_3(0)) or
+		(sig_267 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_50' model 'mux'
+	mux_50 <=
+		(sig_264 and and_116) or
+		(sig_266 and and_197);
+
+	-- Behaviour of component 'mux_51' model 'mux'
+	mux_51 <=
+		(sig_263 and psc_loop_reg_3(0)) or
+		(sig_258 and sig_297(3)) or
+		(sig_267 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_52' model 'mux'
+	mux_52 <=
+		(repeat(8, sig_263) and cp_din(47 downto 40)) or
+		(repeat(8, sig_267) and sig_282);
+
+	-- Behaviour of component 'mux_53' model 'mux'
+	mux_53 <=
+		(sig_263 and psc_loop_reg_3(0)) or
+		(sig_267 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_54' model 'mux'
+	mux_54 <=
+		(sig_264 and and_116) or
+		(sig_266 and and_199);
+
+	-- Behaviour of component 'mux_55' model 'mux'
+	mux_55 <=
+		(sig_263 and psc_loop_reg_3(0)) or
+		(sig_258 and sig_297(3)) or
+		(sig_267 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_56' model 'mux'
+	mux_56 <=
+		(repeat(8, sig_263) and cp_din(55 downto 48)) or
+		(repeat(8, sig_267) and sig_282) or
+		(repeat(8, sig_256) and "00000011");
+
+	-- Behaviour of component 'mux_57' model 'mux'
+	mux_57 <=
+		(sig_263 and psc_loop_reg_3(0)) or
+		(sig_267 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_58' model 'mux'
+	mux_58 <=
+		(sig_264 and and_116) or
+		(sig_266 and and_201) or
+		(sig_255 and '1');
+
+	-- Behaviour of component 'mux_59' model 'mux'
+	mux_59 <=
+		(sig_263 and psc_loop_reg_3(0)) or
+		(sig_258 and sig_297(3)) or
+		(sig_267 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_60' model 'mux'
+	mux_60 <=
+		(repeat(8, sig_263) and cp_din(63 downto 56)) or
+		(repeat(8, sig_267) and sig_282);
+
+	-- Behaviour of component 'mux_61' model 'mux'
+	mux_61 <=
+		(sig_263 and psc_loop_reg_3(0)) or
+		(sig_267 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_62' model 'mux'
+	mux_62 <=
+		(sig_264 and and_116) or
+		(sig_266 and and_203);
+
+	-- Behaviour of component 'mux_63' model 'mux'
+	mux_63 <=
+		(sig_263 and psc_loop_reg_3(0)) or
+		(sig_258 and sig_297(3)) or
+		(sig_267 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_64' model 'mux'
+	mux_64 <=
+		(repeat(32, sig_269) and sig_298) or
+		(repeat(32, sig_251) and augh_main_std_addition);
+
+	-- Behaviour of component 'mux_65' model 'mux'
+	mux_65 <=
+		(sig_272 and '1') or
+		(sig_268 and not_122) or
+		(sig_250 and cp_en);
+
+	-- Behaviour of component 'mux_66' model 'mux'
+	mux_66 <=
+		(repeat(32, sig_258) and sig_322) or
+		(repeat(32, sig_271) and sig_289) or
+		(repeat(32, sig_251) and augh_main_max_iter);
+
+	-- Behaviour of component 'mux_67' model 'mux'
+	mux_67 <=
+		(sig_273 and '1') or
+		(sig_270 and not_122) or
+		(sig_250 and cp_en);
+
+	-- Behaviour of component 'mux_68' model 'mux'
+	mux_68 <=
+		(repeat(32, sig_237) and stdin_data) or
+		(repeat(32, sig_251) and cp_din(63 downto 32));
+
+	-- Behaviour of component 'mux_69' model 'mux'
+	mux_69 <=
+		(sig_238 and not_122) or
+		(sig_250 and cp_en);
+
+	-- Behaviour of component 'mux_70' model 'mux'
+	mux_70 <=
+		(repeat(32, sig_240) and stdin_data) or
+		(repeat(32, sig_251) and cp_din(31 downto 0));
+
+	-- Behaviour of component 'mux_71' model 'mux'
+	mux_71 <=
+		(sig_239 and not_122) or
+		(sig_250 and cp_en);
+
+	-- Behaviour of component 'mux_72' model 'mux'
+	mux_72 <=
+		(repeat(8, sig_259) and cp_din(7 downto 0)) or
+		(repeat(8, sig_267) and augh_main_i(7 downto 0));
+
+	-- Behaviour of component 'mux_73' model 'mux'
+	mux_73 <=
+		(sig_259 and psc_loop_reg_3(0)) or
+		(sig_247 and augh_main_i(3)) or
+		(sig_245 and sig_298(3));
+
+	-- Behaviour of component 'mux_74' model 'mux'
+	mux_74 <=
+		(sig_257 and and_116) or
+		(sig_246 and sig_299) or
+		(sig_244 and sig_222) or
+		(sig_266 and and_190);
+
+	-- Behaviour of component 'mux_75' model 'mux'
+	mux_75 <=
+		(sig_259 and psc_loop_reg_3(0)) or
+		(sig_258 and sig_297(3)) or
+		(sig_271 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_76' model 'mux'
+	mux_76 <=
+		(repeat(8, sig_259) and cp_din(15 downto 8)) or
+		(repeat(8, sig_267) and augh_main_i(7 downto 0));
+
+	-- Behaviour of component 'mux_77' model 'mux'
+	mux_77 <=
+		(sig_259 and psc_loop_reg_3(0)) or
+		(sig_247 and augh_main_i(3)) or
+		(sig_245 and sig_298(3));
+
+	-- Behaviour of component 'mux_78' model 'mux'
+	mux_78 <=
+		(sig_257 and and_116) or
+		(sig_246 and sig_226) or
+		(sig_244 and sig_312) or
+		(sig_266 and and_192);
+
+	-- Behaviour of component 'mux_79' model 'mux'
+	mux_79 <=
+		(sig_259 and psc_loop_reg_3(0)) or
+		(sig_258 and sig_297(3)) or
+		(sig_271 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_80' model 'mux'
+	mux_80 <=
+		(repeat(8, sig_259) and cp_din(23 downto 16)) or
+		(repeat(8, sig_267) and augh_main_i(7 downto 0)) or
+		(repeat(8, sig_256) and "00001100");
+
+	-- Behaviour of component 'mux_20' model 'mux'
+	mux_20 <=
+		(sig_250 and cp_en);
+
+	-- Behaviour of component 'mux_22' model 'mux'
+	mux_22 <=
+		(sig_274 and sig_236) or
+		(sig_254 and sig_281);
+
+	-- Behaviour of component 'and_163' model 'and'
+	and_163 <=
+		sig_324 and
+		repeat(8, sig_233);
+
+	-- Behaviour of component 'and_164' model 'and'
+	and_164 <=
+		sig_325 and
+		repeat(8, sig_232);
+
+	-- Behaviour of component 'and_165' model 'and'
+	and_165 <=
+		sig_326 and
+		repeat(8, sig_231);
+
+	-- Behaviour of component 'and_166' model 'and'
+	and_166 <=
+		sig_327 and
+		repeat(8, sig_230);
+
+	-- Behaviour of component 'and_167' model 'and'
+	and_167 <=
+		sig_328 and
+		repeat(8, sig_229);
+
+	-- Behaviour of component 'and_168' model 'and'
+	and_168 <=
+		sig_329 and
+		repeat(8, sig_228);
+
+	-- Behaviour of component 'and_169' model 'and'
+	and_169 <=
+		sig_330 and
+		repeat(8, sig_227);
+
+	-- Behaviour of component 'and_182' model 'and'
+	and_182 <=
+		sig_336 and
+		repeat(8, sig_321);
+
+	-- Behaviour of component 'and_184' model 'and'
+	and_184 <=
+		sig_337 and
+		repeat(8, sig_320);
+
+	-- Behaviour of component 'and_186' model 'and'
+	and_186 <=
+		sig_338 and
+		repeat(8, sig_290);
+
+	-- Behaviour of component 'and_192' model 'and'
+	and_192 <=
+		not_122 and
+		sig_319;
+
+	-- Behaviour of component 'and_194' model 'and'
+	and_194 <=
+		not_122 and
+		sig_318;
+
+	-- Behaviour of component 'and_196' model 'and'
+	and_196 <=
+		not_122 and
+		sig_225;
+
+	-- Behaviour of component 'mux_81' model 'mux'
+	mux_81 <=
+		(sig_259 and psc_loop_reg_3(0)) or
+		(sig_247 and augh_main_i(3)) or
+		(sig_245 and sig_298(3));
+
+	-- Behaviour of component 'mux_82' model 'mux'
+	mux_82 <=
+		(sig_257 and and_116) or
+		(sig_246 and sig_315) or
+		(sig_244 and sig_311) or
+		(sig_266 and and_194) or
+		(sig_255 and '1');
+
+	-- Behaviour of component 'mux_83' model 'mux'
+	mux_83 <=
+		(sig_259 and psc_loop_reg_3(0)) or
+		(sig_258 and sig_297(3)) or
+		(sig_271 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_84' model 'mux'
+	mux_84 <=
+		(repeat(8, sig_259) and cp_din(31 downto 24)) or
+		(repeat(8, sig_267) and augh_main_i(7 downto 0));
+
+	-- Behaviour of component 'mux_85' model 'mux'
+	mux_85 <=
+		(sig_259 and psc_loop_reg_3(0)) or
+		(sig_247 and augh_main_i(3)) or
+		(sig_245 and sig_298(3));
+
+	-- Behaviour of component 'mux_86' model 'mux'
+	mux_86 <=
+		(sig_257 and and_116) or
+		(sig_246 and sig_225) or
+		(sig_244 and sig_310) or
+		(sig_266 and and_196);
+
+	-- Behaviour of component 'mux_87' model 'mux'
+	mux_87 <=
+		(sig_259 and psc_loop_reg_3(0)) or
+		(sig_258 and sig_297(3)) or
+		(sig_271 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_88' model 'mux'
+	mux_88 <=
+		(repeat(8, sig_259) and cp_din(39 downto 32)) or
+		(repeat(8, sig_267) and augh_main_i(7 downto 0));
+
+	-- Behaviour of component 'mux_89' model 'mux'
+	mux_89 <=
+		(sig_259 and psc_loop_reg_3(0)) or
+		(sig_247 and augh_main_i(3)) or
+		(sig_245 and sig_298(3));
+
+	-- Behaviour of component 'mux_90' model 'mux'
+	mux_90 <=
+		(sig_257 and and_116) or
+		(sig_246 and sig_314) or
+		(sig_244 and sig_309) or
+		(sig_266 and and_197);
+
+	-- Behaviour of component 'mux_91' model 'mux'
+	mux_91 <=
+		(sig_259 and psc_loop_reg_3(0)) or
+		(sig_258 and sig_297(3)) or
+		(sig_271 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_92' model 'mux'
+	mux_92 <=
+		(repeat(8, sig_259) and cp_din(47 downto 40)) or
+		(repeat(8, sig_267) and augh_main_i(7 downto 0));
+
+	-- Behaviour of component 'mux_93' model 'mux'
+	mux_93 <=
+		(sig_259 and psc_loop_reg_3(0)) or
+		(sig_247 and augh_main_i(3)) or
+		(sig_245 and sig_298(3));
+
+	-- Behaviour of component 'mux_94' model 'mux'
+	mux_94 <=
+		(sig_257 and and_116) or
+		(sig_246 and sig_224) or
+		(sig_244 and sig_308) or
+		(sig_266 and and_199);
+
+	-- Behaviour of component 'mux_95' model 'mux'
+	mux_95 <=
+		(sig_259 and psc_loop_reg_3(0)) or
+		(sig_258 and sig_297(3)) or
+		(sig_271 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_96' model 'mux'
+	mux_96 <=
+		(repeat(8, sig_259) and cp_din(55 downto 48)) or
+		(repeat(8, sig_267) and augh_main_i(7 downto 0));
+
+	-- Behaviour of component 'mux_97' model 'mux'
+	mux_97 <=
+		(sig_259 and psc_loop_reg_3(0)) or
+		(sig_247 and augh_main_i(3)) or
+		(sig_245 and sig_298(3));
+
+	-- Behaviour of component 'mux_98' model 'mux'
+	mux_98 <=
+		(sig_257 and and_116) or
+		(sig_246 and sig_313) or
+		(sig_244 and sig_307) or
+		(sig_266 and and_201);
+
+	-- Behaviour of component 'mux_99' model 'mux'
+	mux_99 <=
+		(sig_259 and psc_loop_reg_3(0)) or
+		(sig_258 and sig_297(3)) or
+		(sig_271 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_100' model 'mux'
+	mux_100 <=
+		(repeat(8, sig_259) and cp_din(63 downto 56)) or
+		(repeat(8, sig_267) and augh_main_i(7 downto 0));
+
+	-- Behaviour of component 'mux_101' model 'mux'
+	mux_101 <=
+		(sig_259 and psc_loop_reg_3(0)) or
+		(sig_247 and augh_main_i(3)) or
+		(sig_245 and sig_298(3));
+
+	-- Behaviour of component 'mux_102' model 'mux'
+	mux_102 <=
+		(sig_257 and and_116) or
+		(sig_246 and sig_223) or
+		(sig_244 and sig_306) or
+		(sig_266 and and_203);
+
+	-- Behaviour of component 'mux_103' model 'mux'
+	mux_103 <=
+		(sig_259 and psc_loop_reg_3(0)) or
+		(sig_258 and sig_297(3)) or
+		(sig_271 and augh_main_i(3));
+
+	-- Behaviour of component 'mux_106' model 'mux'
+	mux_106 <=
+		(sig_239 and sig_301) or
+		(sig_238 and sig_316);
+
+	-- Behaviour of component 'mux_108' model 'mux'
+	mux_108 <=
+		(sig_241 and sig_302);
+
+	-- Behaviour of component 'mux_109' model 'mux'
+	mux_109 <=
+		(repeat(64, sig_263) and (sig_330 & sig_329 & sig_328 & sig_327 & sig_326 & sig_325 & sig_324 & sig_323)) or
+		(repeat(64, sig_259) and (sig_338 & sig_337 & sig_336 & sig_335 & sig_334 & sig_333 & sig_332 & sig_331)) or
+		(repeat(64, sig_251) and (psc_stuff_reg_11 & cp_id_reg_4));
+
+	-- Behaviour of component 'mux_110' model 'mux'
+	mux_110 <=
+		(sig_265 and '1') or
+		(sig_263 and sig_305) or
+		(sig_259 and sig_317) or
+		(sig_251 and sig_280);
+
+	-- Behaviour of component 'and_116' model 'and'
+	and_116 <=
+		cp_en and
+		cp_rest;
+
+	-- Behaviour of component 'not_122' model 'not'
+	not_122 <= not (
+		cp_en
+	);
+
+	-- Behaviour of component 'or_143' model 'or'
+	or_143 <=
+		and_144 or
+		and_155 or
+		and_157 or
+		and_159 or
+		and_147 or
+		and_149 or
+		and_151 or
+		and_153;
+
+	-- Behaviour of component 'and_147' model 'and'
+	and_147 <=
+		sig_332 and
+		repeat(8, sig_233);
+
+	-- Behaviour of component 'and_149' model 'and'
+	and_149 <=
+		sig_333 and
+		repeat(8, sig_232);
+
+	-- Behaviour of component 'and_151' model 'and'
+	and_151 <=
+		sig_334 and
+		repeat(8, sig_231);
+
+	-- Behaviour of component 'and_153' model 'and'
+	and_153 <=
+		sig_335 and
+		repeat(8, sig_230);
+
+	-- Behaviour of component 'and_155' model 'and'
+	and_155 <=
+		sig_336 and
+		repeat(8, sig_229);
+
+	-- Behaviour of component 'and_157' model 'and'
+	and_157 <=
+		sig_337 and
+		repeat(8, sig_228);
+
+	-- Behaviour of component 'and_159' model 'and'
+	and_159 <=
+		sig_338 and
+		repeat(8, sig_227);
+
+	-- Behaviour of component 'or_161' model 'or'
+	or_161 <=
+		and_162 or
+		and_167 or
+		and_168 or
+		and_169 or
+		and_163 or
+		and_164 or
+		and_165 or
+		and_166;
+
+	-- Behaviour of component 'and_162' model 'and'
+	and_162 <=
+		sig_323 and
+		repeat(8, sig_296);
+
+	-- Behaviour of component 'or_172' model 'or'
+	or_172 <=
+		and_173 or
+		and_182 or
+		and_184 or
+		and_186 or
+		and_175 or
+		and_177 or
+		and_179 or
+		and_181;
+
+	-- Behaviour of component 'and_173' model 'and'
+	and_173 <=
+		sig_331 and
+		repeat(8, sig_294);
+
+	-- Behaviour of component 'and_175' model 'and'
+	and_175 <=
+		sig_332 and
+		repeat(8, sig_293);
+
+	-- Behaviour of component 'and_177' model 'and'
+	and_177 <=
+		sig_333 and
+		repeat(8, sig_292);
+
+	-- Behaviour of component 'and_179' model 'and'
+	and_179 <=
+		sig_334 and
+		repeat(8, sig_291);
+
+	-- Behaviour of component 'and_181' model 'and'
+	and_181 <=
+		sig_335 and
+		repeat(8, sig_314);
+
+	-- Behaviour of component 'and_190' model 'and'
+	and_190 <=
+		not_122 and
+		sig_287;
+
+	-- Behaviour of component 'and_197' model 'and'
+	and_197 <=
+		not_122 and
+		sig_286;
+
+	-- Behaviour of component 'and_199' model 'and'
+	and_199 <=
+		not_122 and
+		sig_285;
+
+	-- Behaviour of component 'and_201' model 'and'
+	and_201 <=
+		not_122 and
+		sig_284;
+
+	-- Behaviour of component 'and_203' model 'and'
+	and_203 <=
+		not_122 and
+		sig_283;
+
+	-- Behaviour of component 'or_205' model 'or'
+	or_205 <=
+		and_206 or
+		and_211 or
+		and_212 or
+		and_213 or
+		and_207 or
+		and_208 or
+		and_209 or
+		and_210;
+
+	-- Behaviour of component 'and_206' model 'and'
+	and_206 <=
+		sig_323 and
+		repeat(8, sig_287);
+
+	-- Behaviour of component 'and_207' model 'and'
+	and_207 <=
+		sig_324 and
+		repeat(8, sig_319);
+
+	-- Behaviour of component 'and_208' model 'and'
+	and_208 <=
+		sig_325 and
+		repeat(8, sig_318);
+
+	-- Behaviour of component 'and_209' model 'and'
+	and_209 <=
+		sig_326 and
+		repeat(8, sig_225);
+
+	-- Behaviour of component 'and_210' model 'and'
+	and_210 <=
+		sig_327 and
+		repeat(8, sig_286);
+
+	-- Behaviour of component 'and_211' model 'and'
+	and_211 <=
+		sig_328 and
+		repeat(8, sig_285);
+
+	-- Behaviour of component 'and_212' model 'and'
+	and_212 <=
+		sig_329 and
+		repeat(8, sig_284);
+
+	-- Behaviour of component 'and_213' model 'and'
+	and_213 <=
+		sig_330 and
+		repeat(8, sig_283);
+
+	-- Behaviour of component 'and_144' model 'and'
+	and_144 <=
+		sig_331 and
+		repeat(8, sig_296);
+
+	-- Behaviour of all components of model 'reg'
+	-- Registers with clock = sig_clock and reset = sig_reset active '1'
+	process(sig_clock, sig_reset)
+	begin
+		if sig_reset = '1' then
+			psc_stuff_reg_11 <= "0000000000000000000000000000000000000000000000000000000000000";
+		else
+			if rising_edge(sig_clock) then
+				if mux_20 = '1' then
+					psc_stuff_reg_11 <= augh_main_i & augh_main_result(31 downto 3);
+				end if;
+			end if;
+		end if;
+	end process;
+	-- Registers with clock = sig_clock and no reset
+	process(sig_clock)
+	begin
+		if rising_edge(sig_clock) then
+			if mux_27 = '1' then
+				cp_id_reg_stable_5 <= mux_26;
+			end if;
+			if mux_29 = '1' then
+				cp_id_reg_4 <= mux_28;
+			end if;
+			if mux_31 = '1' then
+				psc_loop_reg_3 <= mux_30;
+			end if;
+			if mux_65 = '1' then
+				augh_main_i <= mux_64;
+			end if;
+			if mux_67 = '1' then
+				augh_main_result <= mux_66;
+			end if;
+			if mux_69 = '1' then
+				augh_main_std_addition <= mux_68;
+			end if;
+			if mux_71 = '1' then
+				augh_main_max_iter <= mux_70;
+			end if;
+		end if;
+	end process;
+
+	-- Remaining signal assignments
+	-- Those who are not assigned by component instantiation
+
+	sig_clock <= clock;
+	sig_reset <= reset;
+	sig_start <= start;
+	test_cp_4_6 <= mux_25;
+	test_cp_3_7 <= mux_24;
+	test_cp_0_8 <= mux_23;
+	test_cp_1_9 <= mux_22;
+	memextrct_loop_sig_13 <= sig_303;
+	memextrct_loop_sig_14 <= sig_303;
+	sig_339 <= repeat(24, or_172(7)) & or_172;
+	sig_340 <= or_161(7) & or_161;
+	sig_341 <= or_143(7) & or_143;
+	sig_342 <= repeat(23, sig_295(8)) & sig_295;
+
+	-- Remaining top-level ports assignments
+	-- Those who are not assigned by component instantiation
+
+	stdin_rdy <= mux_106;
+	stdout_data <= augh_main_result;
+	stdout_rdy <= mux_108;
+	cp_dout <= mux_109;
+	cp_ok <= mux_110;
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/v_split0.vhd b/testsuite/gna/issue50/vector.d/v_split0.vhd
new file mode 100644
index 000000000..e95973e01
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/v_split0.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity v_split0 is
+	port (
+		clk : in  std_logic;
+		ra0_data : out std_logic_vector(7 downto 0);
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic;
+		wa0_en : in  std_logic;
+		ra0_addr : in  std_logic
+	);
+end v_split0;
+architecture augh of v_split0 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (others => (others => '0'));
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/v_split1.vhd b/testsuite/gna/issue50/vector.d/v_split1.vhd
new file mode 100644
index 000000000..537758796
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/v_split1.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity v_split1 is
+	port (
+		clk : in  std_logic;
+		ra0_data : out std_logic_vector(7 downto 0);
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic;
+		wa0_en : in  std_logic;
+		ra0_addr : in  std_logic
+	);
+end v_split1;
+architecture augh of v_split1 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (others => (others => '0'));
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/v_split2.vhd b/testsuite/gna/issue50/vector.d/v_split2.vhd
new file mode 100644
index 000000000..3ec8ce48c
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/v_split2.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity v_split2 is
+	port (
+		clk : in  std_logic;
+		ra0_data : out std_logic_vector(7 downto 0);
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic;
+		wa0_en : in  std_logic;
+		ra0_addr : in  std_logic
+	);
+end v_split2;
+architecture augh of v_split2 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (others => (others => '0'));
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/v_split3.vhd b/testsuite/gna/issue50/vector.d/v_split3.vhd
new file mode 100644
index 000000000..a2a569c3b
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/v_split3.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity v_split3 is
+	port (
+		clk : in  std_logic;
+		ra0_data : out std_logic_vector(7 downto 0);
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic;
+		wa0_en : in  std_logic;
+		ra0_addr : in  std_logic
+	);
+end v_split3;
+architecture augh of v_split3 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (others => (others => '0'));
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/v_split4.vhd b/testsuite/gna/issue50/vector.d/v_split4.vhd
new file mode 100644
index 000000000..f48a53a47
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/v_split4.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity v_split4 is
+	port (
+		clk : in  std_logic;
+		ra0_data : out std_logic_vector(7 downto 0);
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic;
+		wa0_en : in  std_logic;
+		ra0_addr : in  std_logic
+	);
+end v_split4;
+architecture augh of v_split4 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (others => (others => '0'));
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/v_split5.vhd b/testsuite/gna/issue50/vector.d/v_split5.vhd
new file mode 100644
index 000000000..ea9acd5a5
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/v_split5.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity v_split5 is
+	port (
+		clk : in  std_logic;
+		ra0_data : out std_logic_vector(7 downto 0);
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic;
+		wa0_en : in  std_logic;
+		ra0_addr : in  std_logic
+	);
+end v_split5;
+architecture augh of v_split5 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (others => (others => '0'));
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/v_split6.vhd b/testsuite/gna/issue50/vector.d/v_split6.vhd
new file mode 100644
index 000000000..98e87b9cc
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/v_split6.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity v_split6 is
+	port (
+		clk : in  std_logic;
+		ra0_data : out std_logic_vector(7 downto 0);
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic;
+		wa0_en : in  std_logic;
+		ra0_addr : in  std_logic
+	);
+end v_split6;
+architecture augh of v_split6 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (others => (others => '0'));
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/v_split7.vhd b/testsuite/gna/issue50/vector.d/v_split7.vhd
new file mode 100644
index 000000000..ff89b3c21
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/v_split7.vhd
@@ -0,0 +1,65 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity v_split7 is
+	port (
+		clk : in  std_logic;
+		ra0_data : out std_logic_vector(7 downto 0);
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic;
+		wa0_en : in  std_logic;
+		ra0_addr : in  std_logic
+	);
+end v_split7;
+architecture augh of v_split7 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (others => (others => '0'));
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/w_split0.vhd b/testsuite/gna/issue50/vector.d/w_split0.vhd
new file mode 100644
index 000000000..0fcb022f3
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/w_split0.vhd
@@ -0,0 +1,67 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity w_split0 is
+	port (
+		clk : in  std_logic;
+		ra0_data : out std_logic_vector(7 downto 0);
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic;
+		wa0_en : in  std_logic;
+		ra0_addr : in  std_logic
+	);
+end w_split0;
+architecture augh of w_split0 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (
+		"00000111", "00000111"
+	);
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/w_split1.vhd b/testsuite/gna/issue50/vector.d/w_split1.vhd
new file mode 100644
index 000000000..aa72b9f55
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/w_split1.vhd
@@ -0,0 +1,67 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity w_split1 is
+	port (
+		clk : in  std_logic;
+		ra0_data : out std_logic_vector(7 downto 0);
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic;
+		wa0_en : in  std_logic;
+		ra0_addr : in  std_logic
+	);
+end w_split1;
+architecture augh of w_split1 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (
+		"00000111", "00000111"
+	);
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/w_split2.vhd b/testsuite/gna/issue50/vector.d/w_split2.vhd
new file mode 100644
index 000000000..b23549ac2
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/w_split2.vhd
@@ -0,0 +1,67 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity w_split2 is
+	port (
+		clk : in  std_logic;
+		ra0_data : out std_logic_vector(7 downto 0);
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic;
+		wa0_en : in  std_logic;
+		ra0_addr : in  std_logic
+	);
+end w_split2;
+architecture augh of w_split2 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (
+		"00000111", "00000111"
+	);
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/w_split3.vhd b/testsuite/gna/issue50/vector.d/w_split3.vhd
new file mode 100644
index 000000000..446b4ee14
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/w_split3.vhd
@@ -0,0 +1,67 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity w_split3 is
+	port (
+		clk : in  std_logic;
+		ra0_data : out std_logic_vector(7 downto 0);
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic;
+		wa0_en : in  std_logic;
+		ra0_addr : in  std_logic
+	);
+end w_split3;
+architecture augh of w_split3 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (
+		"00000111", "00000000"
+	);
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/w_split4.vhd b/testsuite/gna/issue50/vector.d/w_split4.vhd
new file mode 100644
index 000000000..0be33beb5
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/w_split4.vhd
@@ -0,0 +1,67 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity w_split4 is
+	port (
+		clk : in  std_logic;
+		ra0_data : out std_logic_vector(7 downto 0);
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic;
+		wa0_en : in  std_logic;
+		ra0_addr : in  std_logic
+	);
+end w_split4;
+architecture augh of w_split4 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (
+		"00000111", "00000111"
+	);
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/w_split5.vhd b/testsuite/gna/issue50/vector.d/w_split5.vhd
new file mode 100644
index 000000000..dd447b296
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/w_split5.vhd
@@ -0,0 +1,67 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity w_split5 is
+	port (
+		clk : in  std_logic;
+		ra0_data : out std_logic_vector(7 downto 0);
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic;
+		wa0_en : in  std_logic;
+		ra0_addr : in  std_logic
+	);
+end w_split5;
+architecture augh of w_split5 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (
+		"00000111", "00000111"
+	);
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/w_split6.vhd b/testsuite/gna/issue50/vector.d/w_split6.vhd
new file mode 100644
index 000000000..e00068742
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/w_split6.vhd
@@ -0,0 +1,67 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity w_split6 is
+	port (
+		clk : in  std_logic;
+		ra0_data : out std_logic_vector(7 downto 0);
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic;
+		wa0_en : in  std_logic;
+		ra0_addr : in  std_logic
+	);
+end w_split6;
+architecture augh of w_split6 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (
+		"00000111", "00000111"
+	);
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;
diff --git a/testsuite/gna/issue50/vector.d/w_split7.vhd b/testsuite/gna/issue50/vector.d/w_split7.vhd
new file mode 100644
index 000000000..046b02597
--- /dev/null
+++ b/testsuite/gna/issue50/vector.d/w_split7.vhd
@@ -0,0 +1,67 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity w_split7 is
+	port (
+		clk : in  std_logic;
+		ra0_data : out std_logic_vector(7 downto 0);
+		wa0_data : in  std_logic_vector(7 downto 0);
+		wa0_addr : in  std_logic;
+		wa0_en : in  std_logic;
+		ra0_addr : in  std_logic
+	);
+end w_split7;
+architecture augh of w_split7 is
+
+	-- Embedded RAM
+
+	type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
+	signal ram : ram_type := (
+		"00000111", "00000111"
+	);
+
+
+	-- Little utility functions to make VHDL syntactically correct
+	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
+	--   This happens when accessing arrays with <= 2 cells, for example.
+
+	function to_integer(B: std_logic) return integer is
+		variable V: std_logic_vector(0 to 0);
+	begin
+		V(0) := B;
+		return to_integer(unsigned(V));
+	end;
+
+	function to_integer(V: std_logic_vector) return integer is
+	begin
+		return to_integer(unsigned(V));
+	end;
+
+begin
+
+	-- Sequential process
+	-- It handles the Writes
+
+	process (clk)
+	begin
+		if rising_edge(clk) then
+
+			-- Write to the RAM
+			-- Note: there should be only one port.
+
+			if wa0_en = '1' then
+				ram( to_integer(wa0_addr) ) <= wa0_data;
+			end if;
+
+		end if;
+	end process;
+
+	-- The Read side (the outputs)
+
+	ra0_data <= ram( to_integer(ra0_addr) );
+
+end architecture;