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Diffstat (limited to 'testsuite/synth/issue1596/ent.vhdl')
-rw-r--r-- | testsuite/synth/issue1596/ent.vhdl | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/testsuite/synth/issue1596/ent.vhdl b/testsuite/synth/issue1596/ent.vhdl new file mode 100644 index 000000000..ff86d620b --- /dev/null +++ b/testsuite/synth/issue1596/ent.vhdl @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; + +-- Instatiated component --- +entity v is + -- input is unconstrained + port (input : in std_logic_vector); +end; + +architecture RTL of v is + constant bits : positive := 4; + signal i : std_logic_vector(bits - 1 downto 0); +begin + i <= input; +end; |