diff options
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/synth/issue1596/ent.vhdl | 15 | ||||
-rw-r--r-- | testsuite/synth/issue1596/ent_bug.vhdl | 11 | ||||
-rw-r--r-- | testsuite/synth/issue1596/ent_working.vhdl | 12 | ||||
-rwxr-xr-x | testsuite/synth/issue1596/testsuite.sh | 8 |
4 files changed, 46 insertions, 0 deletions
diff --git a/testsuite/synth/issue1596/ent.vhdl b/testsuite/synth/issue1596/ent.vhdl new file mode 100644 index 000000000..ff86d620b --- /dev/null +++ b/testsuite/synth/issue1596/ent.vhdl @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; + +-- Instatiated component --- +entity v is + -- input is unconstrained + port (input : in std_logic_vector); +end; + +architecture RTL of v is + constant bits : positive := 4; + signal i : std_logic_vector(bits - 1 downto 0); +begin + i <= input; +end; diff --git a/testsuite/synth/issue1596/ent_bug.vhdl b/testsuite/synth/issue1596/ent_bug.vhdl new file mode 100644 index 000000000..3002995cf --- /dev/null +++ b/testsuite/synth/issue1596/ent_bug.vhdl @@ -0,0 +1,11 @@ +library ieee; +use ieee.std_logic_1164.all; +use work.v; + +-- TOP BUG --- +entity ent_bug is end; +architecture RTL of ent_bug is +begin + inst_v : entity v + port map (input => "0000"); +end; diff --git a/testsuite/synth/issue1596/ent_working.vhdl b/testsuite/synth/issue1596/ent_working.vhdl new file mode 100644 index 000000000..d311b7d76 --- /dev/null +++ b/testsuite/synth/issue1596/ent_working.vhdl @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; +use work.v; + +-- TOP WORKING --- +entity ent_working is end; +architecture RTL of ent_working is + signal a : std_logic_vector(3 downto 0) := "0101"; +begin + inst_v : entity v + port map (input => a); +end; diff --git a/testsuite/synth/issue1596/testsuite.sh b/testsuite/synth/issue1596/testsuite.sh new file mode 100755 index 000000000..f9c9fdd54 --- /dev/null +++ b/testsuite/synth/issue1596/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +synth ent.vhdl ent_working.vhdl -e > syn_working.vhdl +synth ent.vhdl ent_bug.vhdl -e > syn_bug.vhdl + +echo "Test successful" |