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python
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libghdl
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thin
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vhdl
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nodes.py
Commit message (
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Author
Age
Files
Lines
*
synth: handle more operations from synsopsys packages.
Tristan Gingold
2020-03-14
1
-77
/
+79
*
vhdl: recognize more std_logic_arith operations.
Tristan Gingold
2020-03-13
1
-0
/
+32
*
vhdl-ieee-std_logic_arith: recognize more conversions.
Tristan Gingold
2020-03-11
1
-0
/
+4
*
vhdl: recognize mod/rem operators.
Tristan Gingold
2020-03-10
1
-162
/
+174
*
synthesis: add option --vendor-library= for synthesis.
Tristan Gingold
2020-03-10
1
-0
/
+4
*
vhdl: recognize conversion functions from std_logic_1164
Tristan Gingold
2020-02-18
1
-216
/
+222
*
synth: handle some rotation and shifts. Fix #1077
Tristan Gingold
2020-01-30
1
-205
/
+209
*
synth: handle matching comparisons. Fix #1109
Tristan Gingold
2020-01-24
1
-90
/
+126
*
synth: add id_abs gate. For #1101
Tristan Gingold
2020-01-20
1
-71
/
+72
*
synth: handle more signed operations. For #1101
Tristan Gingold
2020-01-19
1
-140
/
+144
*
vhdl: recognize predefined shift operators for ieee.numeric_std. For #1077
Tristan Gingold
2020-01-11
1
-77
/
+85
*
synth: handle ieee.math_real.round Fix #1075
Tristan Gingold
2020-01-10
1
-50
/
+51
*
ams-vhdl: add support for 'delayed for quantity.
Tristan Gingold
2019-12-31
1
-25
/
+28
*
ams-vhdl: handle zoh, ltf and ztf attributes.
Tristan Gingold
2019-12-31
1
-28
/
+45
*
ams-vhdl: add simultaneous null statement.
Tristan Gingold
2019-12-30
1
-86
/
+90
*
ams-vhdl: add frequency function, minor fixes.
Tristan Gingold
2019-12-30
1
-180
/
+181
*
ams-vhdl: check nature for record natures and terminals.
Tristan Gingold
2019-12-30
1
-29
/
+39
*
vhdl: improve support of AMS-vhdl (array and record natures, source quantities)
Tristan Gingold
2019-12-28
1
-454
/
+625
*
vhdl: add Has_Delay_Machanism for optional 'inertial' printing.
Tristan Gingold
2019-12-26
1
-0
/
+4
*
vhdl: recognize ieee.std_logic_1164.is_x.
Tristan Gingold
2019-12-24
1
-159
/
+161
*
vhdl: recognize sin and cos from math_real.
Tristan Gingold
2019-11-26
1
-47
/
+49
*
synth: preliminary work to support intrinsic procedures.
Tristan Gingold
2019-11-14
1
-172
/
+175
*
vhdl: recognize rising_edge/falling_edge.
Tristan Gingold
2019-11-06
1
-155
/
+157
*
vhdl: recognize std_logic_unsigned.conv_integer.
Tristan Gingold
2019-10-13
1
-18
/
+19
*
vhdl: recognize conv_integer functions from std_logic_arith.
Tristan Gingold
2019-10-11
1
-0
/
+4
*
vhdl: recognize std_logic_signed package (from synopsys).
Tristan Gingold
2019-10-11
1
-4
/
+14
*
vhdl: recognize minus from std_logic_unsigned
Tristan Gingold
2019-10-11
1
-22
/
+27
*
vhdl: recognize conv_unsigned from ieee.std_logic_arith.
Tristan Gingold
2019-10-10
1
-0
/
+4
*
synth: handle package bodies.
Tristan Gingold
2019-10-07
1
-131
/
+132
*
vhdl: recognize div operators.
Tristan Gingold
2019-09-30
1
-90
/
+96
*
vhdl: recognize rotate functions.
Tristan Gingold
2019-09-22
1
-46
/
+50
*
vhdl: add exit/next flags.
Tristan Gingold
2019-09-18
1
-0
/
+12
*
vhdl: recognize numeric_std shift_left.
Tristan Gingold
2019-09-11
1
-46
/
+50
*
vhdl: recognize numeric_std mul.
Tristan Gingold
2019-09-07
1
-82
/
+88
*
vhdl: renames Conditional_Expression to Conditional_Expression_Chain.
Tristan Gingold
2019-09-02
1
-2
/
+2
*
vhdl synth: recognize more operators (add uns log).
Tristan Gingold
2019-09-02
1
-91
/
+95
*
vhdl: recognize ieee.numeric_std std_match.
Tristan Gingold
2019-08-30
1
-25
/
+30
*
vhdl: recognize 1164 condition operator, handle in synth.
Tristan Gingold
2019-08-30
1
-99
/
+102
*
synth: handle verification units.
Tristan Gingold
2019-08-20
1
-0
/
+4
*
vhdl: parse verification unit (WIP).
Tristan Gingold
2019-08-17
1
-242
/
+243
*
vhdl: declare verification units (WIP).
Tristan Gingold
2019-08-16
1
-207
/
+226
*
vhdl: recognize PSL units reserved words.
Tristan Gingold
2019-08-16
1
-27
/
+41
*
vhdl: remove unused Get/Set_Choice_Order.
Tristan Gingold
2019-08-09
1
-4
/
+0
*
Add support for PSL assumptions, used in formal verification (#880)
Pepijn de Vos
2019-08-07
1
-87
/
+93
*
python: regenerate files.
Tristan Gingold
2019-07-26
1
-66
/
+76
*
Fix a merge collision.
Tristan Gingold
2019-07-08
1
-154
/
+84
*
vhdl: rename Cover_Statement to Cover_Directive.
Tristan Gingold
2019-07-04
1
-3
/
+3
*
vhdl: parse and analyze restrict directive.
Tristan Gingold
2019-07-04
1
-1
/
+74
*
vhdl: add anonymous_signal_declaration.
Tristan Gingold
2019-07-03
1
-167
/
+222
*
Rework libghdl build/install procedure (#840)
1138-4EB
2019-06-17
1
-0
/
+2374