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path: root/python/libghdl/thin/vhdl/nodes.py
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* synth: handle more operations from synsopsys packages.Tristan Gingold2020-03-141-77/+79
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* vhdl: recognize more std_logic_arith operations.Tristan Gingold2020-03-131-0/+32
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* vhdl-ieee-std_logic_arith: recognize more conversions.Tristan Gingold2020-03-111-0/+4
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* vhdl: recognize mod/rem operators.Tristan Gingold2020-03-101-162/+174
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* synthesis: add option --vendor-library= for synthesis.Tristan Gingold2020-03-101-0/+4
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* vhdl: recognize conversion functions from std_logic_1164Tristan Gingold2020-02-181-216/+222
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* synth: handle some rotation and shifts. Fix #1077Tristan Gingold2020-01-301-205/+209
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* synth: handle matching comparisons. Fix #1109Tristan Gingold2020-01-241-90/+126
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* synth: add id_abs gate. For #1101Tristan Gingold2020-01-201-71/+72
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* synth: handle more signed operations. For #1101Tristan Gingold2020-01-191-140/+144
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* vhdl: recognize predefined shift operators for ieee.numeric_std. For #1077Tristan Gingold2020-01-111-77/+85
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* synth: handle ieee.math_real.round Fix #1075Tristan Gingold2020-01-101-50/+51
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* ams-vhdl: add support for 'delayed for quantity.Tristan Gingold2019-12-311-25/+28
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* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-28/+45
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* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-86/+90
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* ams-vhdl: add frequency function, minor fixes.Tristan Gingold2019-12-301-180/+181
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* ams-vhdl: check nature for record natures and terminals.Tristan Gingold2019-12-301-29/+39
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* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-454/+625
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* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-261-0/+4
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* vhdl: recognize ieee.std_logic_1164.is_x.Tristan Gingold2019-12-241-159/+161
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* vhdl: recognize sin and cos from math_real.Tristan Gingold2019-11-261-47/+49
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* synth: preliminary work to support intrinsic procedures.Tristan Gingold2019-11-141-172/+175
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* vhdl: recognize rising_edge/falling_edge.Tristan Gingold2019-11-061-155/+157
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* vhdl: recognize std_logic_unsigned.conv_integer.Tristan Gingold2019-10-131-18/+19
| | | | Handle more operators in synth.
* vhdl: recognize conv_integer functions from std_logic_arith.Tristan Gingold2019-10-111-0/+4
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* vhdl: recognize std_logic_signed package (from synopsys).Tristan Gingold2019-10-111-4/+14
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* vhdl: recognize minus from std_logic_unsignedTristan Gingold2019-10-111-22/+27
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* vhdl: recognize conv_unsigned from ieee.std_logic_arith.Tristan Gingold2019-10-101-0/+4
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* synth: handle package bodies.Tristan Gingold2019-10-071-131/+132
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* vhdl: recognize div operators.Tristan Gingold2019-09-301-90/+96
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* vhdl: recognize rotate functions.Tristan Gingold2019-09-221-46/+50
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* vhdl: add exit/next flags.Tristan Gingold2019-09-181-0/+12
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* vhdl: recognize numeric_std shift_left.Tristan Gingold2019-09-111-46/+50
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* vhdl: recognize numeric_std mul.Tristan Gingold2019-09-071-82/+88
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* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-2/+2
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* vhdl synth: recognize more operators (add uns log).Tristan Gingold2019-09-021-91/+95
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* vhdl: recognize ieee.numeric_std std_match.Tristan Gingold2019-08-301-25/+30
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* vhdl: recognize 1164 condition operator, handle in synth.Tristan Gingold2019-08-301-99/+102
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* synth: handle verification units.Tristan Gingold2019-08-201-0/+4
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* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-171-242/+243
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* vhdl: declare verification units (WIP).Tristan Gingold2019-08-161-207/+226
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* vhdl: recognize PSL units reserved words.Tristan Gingold2019-08-161-27/+41
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* vhdl: remove unused Get/Set_Choice_Order.Tristan Gingold2019-08-091-4/+0
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* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-071-87/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
* python: regenerate files.Tristan Gingold2019-07-261-66/+76
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* Fix a merge collision.Tristan Gingold2019-07-081-154/+84
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* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-3/+3
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* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-041-1/+74
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* vhdl: add anonymous_signal_declaration.Tristan Gingold2019-07-031-167/+222
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* Rework libghdl build/install procedure (#840)1138-4EB2019-06-171-0/+2374
* feat(libghdl): add libghdl_pkg.py, add option to generate libghdl-py.tgz with dist/travis/build.sh * libghdl*.so is now part of GHDL * move python sources to python/libghdl and python/pnodes * rename src/vhdl/python to src/vhdl/libghdl * add generation of tarball for libghdl-py to the makefile * deprecate --enable-python and --disable-python * add configuration option --disable-libghdl * feat(python/libghdl): add support for LIBGHDL_PREFIX (#844) * fix(travis): disable libghdl on mac * feat(python/libghdl): add support for GHDL_BIN_PATH and VUNIT_GHDL_PATH
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