| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | netlists-disp_vhdl: adjust output for #2140 | Tristan Gingold | 2022-07-27 | 1 | -2/+8 |
| * | netlist-disp_vhdl: add a separator between instances and signals. | Tristan Gingold | 2022-07-26 | 1 | -1/+1 |
| * | synth: Display dlatch | Tristan Gingold | 2022-07-14 | 1 | -1/+4 |
| * | synth memories: also accept constant signal as memory initial value | Tristan Gingold | 2021-11-28 | 1 | -3/+8 |
| * | synth: put direction into port desc | Tristan Gingold | 2021-11-17 | 1 | -9/+5 |
| * | synth: use a global table for instances attributes | Tristan Gingold | 2021-11-17 | 1 | -48/+38 |
| * | synth: renaming to instance_attributes. | Tristan Gingold | 2021-11-17 | 1 | -5/+6 |
| * | synth: reuse signal name while creating memories. Fix #1838 | Tristan Gingold | 2021-08-25 | 1 | -5/+5 |
| * | netlists-disp_vhdl: do not display edge net when not needed. Fix #1703 | Tristan Gingold | 2021-03-29 | 1 | -6/+48 |
| * | synth: expand ports for record. Fix #1675 | Tristan Gingold | 2021-03-27 | 1 | -5/+3 |
| * | netlists-dump: also dump attributes | Tristan Gingold | 2021-03-17 | 1 | -64/+1 |
| * | update license headers | umarcor | 2021-02-05 | 1 | -5/+3 |
| * | synth: add option to treat asserts as assumes and vice-versa | tmeissner | 2021-01-02 | 1 | -1/+2 |
| * | netlists-disp_vhdl: handle null vectors for reducation operators. | Tristan Gingold | 2020-09-28 | 1 | -3/+12 |
| * | synth: disp_vhdl: const_x may not have a location. | Tristan Gingold | 2020-07-21 | 1 | -0/+1 |
| * | netlists-disp_vhdl: display inout ports as inout. | Tristan Gingold | 2020-07-02 | 1 | -2/+8 |
| * | netlists: handle UL32 in memory initial value. | Tristan Gingold | 2020-05-29 | 1 | -1/+11 |
| * | synth: handle reduction operators. Fix #1342 | Tristan Gingold | 2020-05-27 | 1 | -0/+16 |
| * | netlists: disp attributes in vhdl output (as comments). For #1318 | Tristan Gingold | 2020-05-23 | 1 | -20/+95 |
| * | netlists-memories: set location on utrunc. Fix #1332 | Tristan Gingold | 2020-05-21 | 1 | -10/+11 |
| * | netlists-disp_vhdl: fix id_sextend for 1 bit. | Tristan Gingold | 2020-05-21 | 1 | -1/+1 |
| * | synth: handle inout ports with default values. For #1312 | Tristan Gingold | 2020-05-16 | 1 | -1/+2 |
| * | netlists-builders: add Build_Pmux. | Tristan Gingold | 2020-05-09 | 1 | -0/+29 |
| * | synth: add Id_Enable gate (for sequential assertions). | Tristan Gingold | 2020-05-06 | 1 | -0/+2 |
| * | synth: preliminary support of sequential assertions. For #1273 | Tristan Gingold | 2020-05-04 | 1 | -1/+1 |
| * | netlists: ignore missing location on more const. | Tristan Gingold | 2020-04-27 | 1 | -7/+10 |
| * | netlists-disp_vhdl: check presence location on significant instances. | Tristan Gingold | 2020-04-26 | 1 | -0/+15 |
| * | netlists: add resolver gate. | Tristan Gingold | 2020-04-22 | 1 | -0/+5 |
| * | synth: add tri gate. | Tristan Gingold | 2020-04-22 | 1 | -0/+4 |
| * | synth: improve handling of nested memories. Fix #1250 | Tristan Gingold | 2020-04-20 | 1 | -1/+5 |
| * | synth: rework edge handling to properly support falling edge. Fix #1227 | Tristan Gingold | 2020-04-15 | 1 | -20/+53 |
| * | netlists-disp_vhdl: factorize code, improve handling of 'Z'. | Tristan Gingold | 2020-04-06 | 1 | -16/+8 |
| * | netlists-disp_vhdl: display generics. | Tristan Gingold | 2020-03-31 | 1 | -0/+25 |
| * | synth: preliminary work to export module parameters. | Tristan Gingold | 2020-03-31 | 1 | -12/+41 |
| * | netlists-disp_vhdl: fix typos. | Tristan Gingold | 2020-03-31 | 1 | -2/+2 |
| * | synth: improve output of memory initial value. | Tristan Gingold | 2020-03-29 | 1 | -4/+36 |
| * | synth: add id_inout gate to handle inout behaviour. Fir #1166 | Tristan Gingold | 2020-03-23 | 1 | -0/+13 |
| * | synth-disp_vhdl: do not wrap inout ports. For #1166 | Tristan Gingold | 2020-03-22 | 1 | -0/+2 |
| * | netlists: add id_nop gate. | Tristan Gingold | 2020-03-22 | 1 | -0/+2 |
| * | synth: handle numeric_std minimum/maximum. Fix #1168 | Tristan Gingold | 2020-03-21 | 1 | -0/+12 |
| * | synth: handle div/rem/mod operations. Fix #1157 | Tristan Gingold | 2020-03-13 | 1 | -0/+3 |
| * | netlists: handle more case of 0 sized nets. | Tristan Gingold | 2020-03-13 | 1 | -1/+0 |
| * | netlists-expands: fix dyn_insert_en (en was missing). Fix #1155 | Tristan Gingold | 2020-03-07 | 1 | -0/+2 |
| * | netlists-disp_vhdl: handle xnor. Fix #1153 | Tristan Gingold | 2020-03-07 | 1 | -0/+2 |
| * | netlists: rework memories to fix port orders, add a loop. | Tristan Gingold | 2020-02-23 | 1 | -7/+10 |
| * | synth: handle component with ports in different order. | Tristan Gingold | 2020-02-13 | 1 | -18/+12 |
| * | synth: handle null vector for vec-vec concat. Fix #1133 | Tristan Gingold | 2020-02-11 | 1 | -1/+3 |
| * | netlists-disp_vhdl: handle 1-bit const_x. For #1107 | Tristan Gingold | 2020-02-05 | 1 | -3/+9 |
| * | netlists-disp_vhdl: minor rework. | Tristan Gingold | 2020-01-26 | 1 | -2/+2 |
| * | synth: improve support of 0-width nets and gates. Fix #1113 | Tristan Gingold | 2020-01-25 | 1 | -14/+22 |
