aboutsummaryrefslogtreecommitdiffstats
path: root/src/synth/netlists-gates.ads
Commit message (Expand)AuthorAgeFilesLines
* netlists: rename id_memidx1 to id_memidxTristan Gingold2019-10-031-1/+1
* synth: replace memidx2 by addidx; handle some 2d arrays.Tristan Gingold2019-10-031-2/+2
* synth: simplify dyn_insert.Tristan Gingold2019-10-021-1/+1
* synth: simplify id_dyn_extract.Tristan Gingold2019-10-021-1/+1
* synth: introduce memidx1Tristan Gingold2019-10-021-1/+1
* netlists: add memidx1 and memidx2 gates.Tristan Gingold2019-10-021-4/+10
* netlists-disp_vhdl: handle Const_Log, add comments, fix assertion.Tristan Gingold2019-10-021-0/+3
* synth: add support for integer rem.Tristan Gingold2019-10-011-1/+2
* synth: improve support of * and /. Fix #953Tristan Gingold2019-09-301-2/+4
* synth: add support for mod operator.Tristan Gingold2019-09-281-20/+22
* synth: handle rotate.Tristan Gingold2019-09-221-26/+34
* synth: use constant for constant values.Tristan Gingold2019-09-211-0/+2
* synth: Add support for PSL cover directive (#930)T. Meissner2019-09-191-0/+1
* synth-inference: detect false loop.Tristan Gingold2019-09-171-0/+2
* synth: minor refactoring about const gates.Tristan Gingold2019-09-151-0/+9
* synth: handle unsigned shift left.Tristan Gingold2019-09-111-53/+57
* synth: add const_x gate.Tristan Gingold2019-09-111-0/+1
* synth: add const_sb32, add smul/umul.Tristan Gingold2019-09-071-2/+4
* synth: remove insert gate.Tristan Gingold2019-08-311-7/+0
* synth: remove unused const gates.Tristan Gingold2019-08-301-7/+2
* synth: add support for memories.Tristan Gingold2019-07-291-1/+5
* synth: add concatn gateTristan Gingold2019-07-191-0/+3
* synth: add const_z gate.Tristan Gingold2019-07-191-0/+2
* synth: add Id_Port gate to improve display.Tristan Gingold2019-07-101-23/+24
* netlists: add reduce_or/reduce_and gates.Tristan Gingold2019-07-041-0/+2
* netlists: add assume gate.Tristan Gingold2019-07-041-0/+1
* synth: handle concurrent assertions.Tristan Gingold2019-07-021-0/+3
* synth: add dyn_insert module.Tristan Gingold2019-07-011-4/+10
* synth: add ule, fix gate number.Tristan Gingold2019-06-301-29/+29
* synth: disp_vhdl: handle mux2Tristan Gingold2019-06-281-0/+4
* synth: add get_input_net helper.Tristan Gingold2019-06-281-1/+7
* synth: add syn_extract for dynamic slices.Tristan Gingold2019-06-281-1/+2
* synth: add insert gate.Tristan Gingold2019-06-241-0/+10
* synth: use only one edge gate, make it fully abstract. Handle falling_edge.Tristan Gingold2019-05-221-5/+4
* synth: add comments.Tristan Gingold2019-04-161-3/+13
* Add netlist generation infrastructure.Tristan Gingold2017-01-311-0/+114
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 02:22:34 +0000