| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | synth: add support for record types. | Tristan Gingold | 2019-08-29 | 1 | -62/+132 |
| * | synth: support sequential conditional signal assignment. | Tristan Gingold | 2019-08-27 | 1 | -0/+2 |
| * | synth: rework partial assignments | Tristan Gingold | 2019-08-27 | 1 | -24/+24 |
| * | synth: set name to assert/assume gates. | Tristan Gingold | 2019-08-20 | 1 | -4/+15 |
| * | vhdl: handle assume in verification units. | Tristan Gingold | 2019-08-20 | 1 | -0/+2 |
| * | synth: set location on assume/assert gates. | Tristan Gingold | 2019-08-20 | 1 | -4/+13 |
| * | synth: handle verification units. | Tristan Gingold | 2019-08-20 | 1 | -2/+19 |
| * | synth: fix handling of assume/assert. | Tristan Gingold | 2019-08-14 | 1 | -6/+65 |
| * | synth: also extract edge in PSL expressions. | Tristan Gingold | 2019-08-13 | 1 | -4/+20 |
| * | synth: extract edge for PSL clocks. | Tristan Gingold | 2019-08-13 | 1 | -27/+34 |
| * | Support for PSL assert and assume in synthesis (#892) | Pepijn de Vos | 2019-08-13 | 1 | -4/+53 |
| * | synth: fix crash when assignment target is an aggregate. | Tristan Gingold | 2019-08-08 | 1 | -5/+7 |
| * | synth: handle subtype conversions. | Tristan Gingold | 2019-08-05 | 1 | -24/+45 |
| * | synth: preliminary support of integer literals. | Tristan Gingold | 2019-08-02 | 1 | -6/+2 |
| * | synth: rework indexed names. | Tristan Gingold | 2019-07-30 | 1 | -34/+36 |
| * | synth: add support for memories. | Tristan Gingold | 2019-07-29 | 1 | -3/+5 |
| * | synth: remove extract_bound (trivial). | Tristan Gingold | 2019-07-28 | 1 | -1/+1 |
| * | synth: preliminary support of dynamic indexing. | Tristan Gingold | 2019-07-28 | 1 | -41/+34 |
| * | synth: preliminary support of integer subtypes. | Tristan Gingold | 2019-07-26 | 1 | -1/+3 |
| * | synth: array inequality, integer in choices. | Tristan Gingold | 2019-07-25 | 1 | -0/+4 |
| * | synth: save and display locations for instances. | Tristan Gingold | 2019-07-25 | 1 | -1/+4 |
| * | synth: fix bad ordering in case statement. | Tristan Gingold | 2019-07-24 | 1 | -2/+3 |
| * | synth: fix slice/indexed assignment that partially override previous assign. | Tristan Gingold | 2019-07-23 | 1 | -5/+8 |
| * | synth: rework names. | Tristan Gingold | 2019-07-22 | 1 | -1/+6 |
| * | synth: add support for concurrent selected signal assignment. | Tristan Gingold | 2019-07-20 | 1 | -2/+138 |
| * | synth: initial support for for-generate statement. | Tristan Gingold | 2019-07-20 | 1 | -29/+84 |
| * | synth: finalize concurrent assignments (WIP). | Tristan Gingold | 2019-07-19 | 1 | -4/+12 |
| * | synth: make more types private. | Tristan Gingold | 2019-07-17 | 1 | -1/+1 |
| * | synth: make type Wire_Id_Record private. | Tristan Gingold | 2019-07-17 | 1 | -4/+4 |
| * | synth: renaming of Assign to Seq_Assign. | Tristan Gingold | 2019-07-17 | 1 | -5/+5 |
| * | synth: handle instantiation within generate statement. | Tristan Gingold | 2019-07-15 | 1 | -0/+2 |
| * | synth: handle choices by range in aggregates. | Tristan Gingold | 2019-07-15 | 1 | -7/+11 |
| * | synth: use correct instance to synth default expressions of assocs. | Tristan Gingold | 2019-07-15 | 1 | -10/+13 |
| * | synth: save and restore instance_pool for processes. | Tristan Gingold | 2019-07-15 | 1 | -2/+4 |
| * | synth: handle black boxes. | Tristan Gingold | 2019-07-13 | 1 | -1/+13 |
| * | synth: handle instantiation (WIP) | Tristan Gingold | 2019-07-10 | 1 | -7/+6 |
| * | synth: handle simple user function calls. | Tristan Gingold | 2019-07-06 | 1 | -3/+21 |
| * | synth: use future states for PSL restrict directive. | Tristan Gingold | 2019-07-04 | 1 | -5/+8 |
| * | synth: handle PSL restrict directive (WIP). | Tristan Gingold | 2019-07-04 | 1 | -0/+109 |
| * | vhdl: parse and analyze restrict directive. | Tristan Gingold | 2019-07-04 | 1 | -0/+2 |
| * | synth: handle vhdl2008 std_logic_1164, handle anonymous_signal. | Tristan Gingold | 2019-07-04 | 1 | -1/+2 |
| * | synth: handle concurrent assertions. | Tristan Gingold | 2019-07-02 | 1 | -0/+18 |
| * | synth: destroy iterator after for-loop. | Tristan Gingold | 2019-07-01 | 1 | -2/+10 |
| * | synth: add dyn_insert module. | Tristan Gingold | 2019-07-01 | 1 | -8/+12 |
| * | synth: handle for-loop statements. | Tristan Gingold | 2019-07-01 | 1 | -0/+38 |
| * | synth: handle various enum ranges for case stmts. | Tristan Gingold | 2019-06-30 | 1 | -4/+24 |
| * | synth: handle 2 states fsms. | Tristan Gingold | 2019-06-30 | 1 | -1/+5 |
| * | synth: handle process statement. | Tristan Gingold | 2019-06-30 | 1 | -6/+43 |
| * | vhdl: move annotations from simul to vhdl. | Tristan Gingold | 2019-06-29 | 1 | -1/+1 |
| * | synth: add syn_extract for dynamic slices. | Tristan Gingold | 2019-06-28 | 1 | -3/+9 |
