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vhdl
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simulate
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Author
Age
Files
Lines
*
Fix indentation and English mistakes.
Tristan Gingold
2016-07-05
1
-3
/
+3
*
simulate/execution: uses grt.strings
Tristan Gingold
2016-06-28
1
-5
/
+6
*
simulation: remove unused kind_range.
Tristan Gingold
2016-03-29
2
-9
/
+1
*
simulation: reuse Mode_Signal_Type from grt.types.
Tristan Gingold
2016-03-10
5
-72
/
+76
*
elaboration: use std_time to represent time in signal table.
Tristan Gingold
2016-03-10
3
-9
/
+9
*
simulation: add block id.
Tristan Gingold
2016-03-10
3
-1
/
+13
*
simul debugger: display packages and configuration.
Tristan Gingold
2016-03-10
1
-2
/
+12
*
Refactoring in simulate in order to link with ortho.
Tristan Gingold
2016-02-20
12
-1213
/
+1206
*
simul debugger: add info instances
Tristan Gingold
2016-02-17
2
-3
/
+46
*
simul: fix local protected object, boolean for-generate loop
Tristan Gingold
2016-02-14
3
-38
/
+51
*
simul debugger: handle more concurrent statements.
Tristan Gingold
2016-02-14
1
-0
/
+50
*
simul: more fixes for std_ulogic.
Tristan Gingold
2016-02-14
2
-17
/
+21
*
psl: cover directive works on a sequence, not on a property.
Tristan Gingold
2016-02-14
2
-2
/
+48
*
simul: preliminary work to support PSL.
Tristan Gingold
2016-02-14
7
-105
/
+323
*
simul: return the exit status set by std.env
Tristan Gingold
2016-02-14
1
-2
/
+4
*
simul: check for no unconstrained port/generic of top-level entity.
Tristan Gingold
2016-02-14
2
-1
/
+30
*
simul: make delayed signal elaborated.
Tristan Gingold
2016-02-10
1
-0
/
+1
*
simul: add support of e8.
Tristan Gingold
2016-02-10
9
-170
/
+205
*
simul: handle generic override.
Tristan Gingold
2016-02-10
1
-0
/
+99
*
simul: handle slice in individual association for subprograms.
Tristan Gingold
2016-02-10
1
-0
/
+11
*
simul: fix type conversion to unconstrained array.
Tristan Gingold
2016-02-10
1
-14
/
+35
*
simul: fix corner cases for image.
Tristan Gingold
2016-02-10
1
-100
/
+131
*
simul: fix issue14.
Tristan Gingold
2016-02-10
1
-10
/
+21
*
simul: fix elaboration check for implicit signals.
Tristan Gingold
2016-02-10
1
-0
/
+1
*
simul: fix individual association for array.
Tristan Gingold
2016-02-09
1
-3
/
+4
*
simul: avoid stupid crashes in debugger.
Tristan Gingold
2016-02-09
1
-2
/
+10
*
simul: handle vhdl 2008.
Tristan Gingold
2016-02-06
9
-119
/
+252
*
simul: support of package instantiation.
Tristan Gingold
2016-02-06
4
-11
/
+85
*
simul: preliminary work for environments.
Tristan Gingold
2016-01-27
6
-80
/
+57
*
simul: use Tables instead of GNAT.Table
Tristan Gingold
2016-01-27
5
-36
/
+24
*
simul: handle declarations in configuration.
Tristan Gingold
2016-01-27
3
-59
/
+68
*
simul: fix attribute specification, noop type conversion, indiv sig assoc.
Tristan Gingold
2016-01-26
5
-11
/
+37
*
simul: handle default assignment to unconstrained ports.
Tristan Gingold
2016-01-24
3
-109
/
+63
*
simul: fix various issues.
Tristan Gingold
2016-01-24
8
-254
/
+351
*
simulate: fix handling of deferred constants.
Tristan Gingold
2016-01-19
4
-19
/
+30
*
cleanup in errorout.
Tristan Gingold
2015-12-21
2
-1
/
+11
*
Adjust simulation after sigptr changes.
Tristan Gingold
2015-12-19
4
-49
/
+78
*
ghdl_simul debugger: handle break on operator, handle end of file.
Tristan Gingold
2015-12-03
2
-6
/
+31
*
ghdl_simul debugger: add nstmt and fstmt.
Tristan Gingold
2015-12-03
1
-8
/
+78
*
ghdl_simul debugger: add auto-repeat.
Tristan Gingold
2015-11-30
1
-3
/
+21
*
ghdl_simul debugger: handle function call, consider entity declarations.
Tristan Gingold
2015-11-30
1
-7
/
+21
*
Fix ghdl_simul build.
Tristan Gingold
2015-11-30
3
-29
/
+13
*
Fix simulate backend.
Tristan Gingold
2015-06-02
4
-24
/
+42
*
simulation: use invalid_instance_slot instead of 0.
Tristan Gingold
2015-01-24
2
-4
/
+4
*
Simulation: renaming.
Tristan Gingold
2015-01-23
6
-133
/
+118
*
simulation: rework scope_level.
Tristan Gingold
2015-01-23
6
-123
/
+157
*
Style fixes.
Tristan Gingold
2015-01-18
1
-1
/
+2
*
simulation: adjust for vhdl08 configurations.
Tristan Gingold
2015-01-18
1
-39
/
+38
*
execution: fix v87 concat with element.
Tristan Gingold
2015-01-18
1
-20
/
+24
*
simulation: handle v87 concatenation.
Tristan Gingold
2015-01-17
1
-41
/
+74
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