iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	vhdl-sem_decls: add comment.	Tristan Gingold	2019-10-21	1	-0/+3
*	vhdl-parse: parse declarations in vunit.	Tristan Gingold	2019-10-21	1	-327/+352
*	vhdl: handle labels in verification units.	Tristan Gingold	2019-10-21	1	-8/+62
*	psl: add active state.	Tristan Gingold	2019-10-21	1	-0/+7
*	vhdl-prints: handle restrict in vunit.	Tristan Gingold	2019-10-21	1	-0/+2
*	vhdl: try to convert identifier to token only for identifiers	Tristan Gingold	2019-10-20	1	-1/+3
*	vhdl-prints: add parenthesis around boolean and/or.	Tristan Gingold	2019-10-18	1	-0/+4
*	vhdl: check cover/restrict is followed by a sequence.	Tristan Gingold	2019-10-16	4	-11/+65
*	vhdl: Add the implicit [*] at start of PSL cover sequence.	Tristan Gingold	2019-10-15	1	-0/+7
*	vhdl: handle cover and restrict within vunit.	Tristan Gingold	2019-10-15	4	-1/+15
*	vhdl-evaluation: handle bit condition operator. Fix #977	Tristan Gingold	2019-10-13	1	-0/+3
*	vhdl-annotations: handle list of record elements declaration.	Tristan Gingold	2019-10-13	1	-2/+4
*	vhdl: recognize std_logic_unsigned.conv_integer.	Tristan Gingold	2019-10-13	2	-0/+7
*	vhdl: recognize conv_integer functions from std_logic_arith.	Tristan Gingold	2019-10-11	2	-18/+30
*	vhdl: recognize std_logic_signed package (from synopsys).	Tristan Gingold	2019-10-11	4	-14/+64
*	vhdl: recognize minus from std_logic_unsigned	Tristan Gingold	2019-10-11	2	-0/+15
*	vhdl: do not try to recognize mentor version of std_logic_arith.	Tristan Gingold	2019-10-10	1	-0/+7
*	vhdl: recognize conv_unsigned from ieee.std_logic_arith.	Tristan Gingold	2019-10-10	4	-1/+201
*	synth: handle package bodies.	Tristan Gingold	2019-10-07	1	-0/+1
*	vhdl: recognize to_bitvector.	Tristan Gingold	2019-10-07	2	-81/+74
*	synth: add support for concurrent procedure calls. Fix #969	Tristan Gingold	2019-10-07	1	-1/+2
*	Rework errors handling, to have a more generic framework.	Tristan Gingold	2019-10-06	2	-4/+61
*	synth: improve support of arrays or arrays. Fix #955	Tristan Gingold	2019-10-01	1	-13/+8
*	vhdl: recognize div operators.	Tristan Gingold	2019-09-30	2	-0/+27
*	vhdl-std_package: reduce cascaded error messages.	Tristan Gingold	2019-09-30	1	-0/+1
*	vhdl: recognize rotate functions.	Tristan Gingold	2019-09-22	2	-0/+17
*	synth: handle record subtypes.	Tristan Gingold	2019-09-19	1	-5/+8
*	vhdl: add exit/next flags.	Tristan Gingold	2019-09-18	5	-63/+173
*	vhdl-nodes: add a comment.	Tristan Gingold	2019-09-12	1	-1/+1
*	vhdl-ieee-numeric: recognize shift_right.	Tristan Gingold	2019-09-11	1	-17/+31
*	vhdl: recognize numeric_std shift_left.	Tristan Gingold	2019-09-11	2	-0/+24
*	vhdl: recognize numeric_std mul.	Tristan Gingold	2019-09-07	2	-0/+27
*	vhdl: fix unused warning on protected variable.	Tristan Gingold	2019-09-06	1	-0/+1
*	vhdl: handle P32 in connect_scalar. Fix #918	Tristan Gingold	2019-09-05	1	-1/+2
*	vhdl: do not crash on attribute with a type conversion prefix.	Tristan Gingold	2019-09-04	1	-2/+3
*	vhdl: renames Conditional_Expression to Conditional_Expression_Chain.	Tristan Gingold	2019-09-02	8	-37/+40
*	vhdl synth: recognize more operators (add uns log).	Tristan Gingold	2019-09-02	2	-2/+6
*	vhdl-annotations: ignore conditional variable assignment.	Tristan Gingold	2019-08-30	1	-1/+2
*	vhdl-annotate: handle shared anonymous subtype in interfaces.	Tristan Gingold	2019-08-30	1	-1/+4
*	vhdl: recognize ieee.numeric_std std_match.	Tristan Gingold	2019-08-30	2	-0/+39
*	vhdl: recognize 1164 condition operator, handle in synth.	Tristan Gingold	2019-08-30	2	-5/+17
*	synth: add support for record types.	Tristan Gingold	2019-08-29	1	-0/+4
*	synth: support sequential conditional signal assignment.	Tristan Gingold	2019-08-27	1	-0/+1
*	ignore restrict in simulation (#897)	Pepijn de Vos	2019-08-20	2	-18/+17
*	initial support for reduce and/or (#900)	Pepijn de Vos	2019-08-20	2	-5/+22
*	vhdl psl: fully scan PSL keywords in scanner.	Tristan Gingold	2019-08-20	6	-66/+141
*	vhdl-prints: handle architecture in verification unit hierarchical name.	Tristan Gingold	2019-08-20	1	-0/+7
*	vhdl: handle architecture in verification unit hierarchical name.	Tristan Gingold	2019-08-20	3	-13/+53
*	vhdl-prints: handle verification units.	Tristan Gingold	2019-08-20	1	-318/+354
*	vhdl: handle assume in verification units.	Tristan Gingold	2019-08-20	4	-1/+9