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* synth: handle concurrent assertions.Tristan Gingold2019-07-027-1/+50
* synth-expr: remove useless code.Tristan Gingold2019-07-021-5/+1
* synth-decls: handle initial value for variables andTristan Gingold2019-07-021-5/+4
* netlists-disp_vhdl: handle xor.Tristan Gingold2019-07-021-0/+2
* synth: fix Idff; fix 'edge and enable'.Tristan Gingold2019-07-022-9/+6
* libghdlsynth: do not depend on ghdlsimul.Tristan Gingold2019-07-021-3/+10
* ghdlsynth_gates.h: rebuild.Tristan Gingold2019-07-021-29/+33
* ghdllocal: fix a typo in an error message.Tristan Gingold2019-07-021-1/+1
* vhdl: adjust python pathes in Makefile.Tristan Gingold2019-07-021-9/+11
* synth: destroy iterator after for-loop.Tristan Gingold2019-07-016-10/+54
* synth: improve handling of dynamic slices, add aTristan Gingold2019-07-011-3/+30
* netlists-disp_vhdl: handle dyn_insert, fix mul.Tristan Gingold2019-07-011-20/+36
* synth: add dyn_insert module.Tristan Gingold2019-07-017-28/+130
* netlists-dump: write const in hexa.Tristan Gingold2019-07-011-7/+9
* netlists-disp_vhdl: handle numbers in disp_template.Tristan Gingold2019-07-011-14/+22
* netlists: fix pasto in builders.Tristan Gingold2019-07-011-1/+1
* synth: add types_utils package.Tristan Gingold2019-07-013-3/+31
* ghdlsynth: add option to select the output format.Tristan Gingold2019-07-011-6/+16
* ghdldrv: add comments, analyze files for --synth/-eTristan Gingold2019-07-013-1/+7
* vhdl: improve error message.Tristan Gingold2019-07-011-2/+1
* synth: handle for-loop statements.Tristan Gingold2019-07-012-1/+40
* netlists disp_vhdl: rewrite uextend.Tristan Gingold2019-07-011-5/+7
* synth: handle more concat.Tristan Gingold2019-06-301-0/+19
* ghdlsimul: fix warning.Tristan Gingold2019-06-301-1/+1
* synth: add ule, fix gate number.Tristan Gingold2019-06-303-30/+41
* synth: handle more comparisons.Tristan Gingold2019-06-301-11/+29
* vhdl: recognize more predefined std_logic_unsigned functions.Tristan Gingold2019-06-302-0/+24
* synth: handle various enum ranges for case stmts.Tristan Gingold2019-06-301-4/+24
* synth: handle 2 states fsms.Tristan Gingold2019-06-301-1/+5
* netlists: add a comment.Tristan Gingold2019-06-301-0/+11
* synth: handle process statement.Tristan Gingold2019-06-301-6/+43
* synth: handle std_logic_unsigned."+"Tristan Gingold2019-06-303-1/+17
* synth: handle "=" from std_logic_unsigned.Tristan Gingold2019-06-291-1/+2
* vhdl: recognize std_logic_unsignedTristan Gingold2019-06-294-1/+155
* ghdlcomp: fix warnings.Tristan Gingold2019-06-291-4/+1
* ghdl_jit: almost add ghdlsynthTristan Gingold2019-06-293-0/+2
* vhdl: move annotations from simul to vhdl.Tristan Gingold2019-06-2916-23/+23
* ghdldrv: refactoring - share more code, isolate ghdlsynth from ghdlsimul.Tristan Gingold2019-06-296-123/+111
* synth: disp_vhdl: merge literals.Tristan Gingold2019-06-284-88/+154
* synth: Move get_input_net to netlists.utils.Tristan Gingold2019-06-286-8/+9
* synth: fix disp_vhdl. Can now be analyzed.Tristan Gingold2019-06-281-68/+159
* synth: handle some functions from math_real.Tristan Gingold2019-06-281-1/+43
* vhdl: recognize some functions of math_real.Tristan Gingold2019-06-285-3/+91
* std_names: add names for math_real.Tristan Gingold2019-06-282-1/+7
* synth: disp_vhdl: handle mux2Tristan Gingold2019-06-282-3/+32
* synth: add get_input_net helper.Tristan Gingold2019-06-287-19/+32
* synth: disp_vhdl: add disp_template.Tristan Gingold2019-06-281-23/+46
* synth: improve disp_vhdl.Tristan Gingold2019-06-281-80/+232
* synth: add syn_extract for dynamic slices.Tristan Gingold2019-06-286-63/+273
* synth: handle slice assignment.Tristan Gingold2019-06-255-31/+71