ecp5: Working on bitstream gen

Signed-off-by: David Shah <davey1576@gmail.com>

4 files changed, 478 insertions, 1 deletions

diff --git a/ecp5/synth/.gitignore b/ecp5/synth/.gitignore
index 23844244..5b3bf578 100644
--- a/ecp5/synth/.gitignore
+++ b/ecp5/synth/.gitignore
@@ -1,2 +1 @@
-*.config
 *.bit
diff --git a/ecp5/synth/ulx3s.v b/ecp5/synth/ulx3s.v
new file mode 100644
index 00000000..7f0786f5
--- /dev/null
+++ b/ecp5/synth/ulx3s.v
@@ -0,0 +1,16 @@
+module top(input a_pin, output led_pin, output gpio0_pin);
+
+	wire a;
+	wire led;
+    wire gpio0;
+	(* BEL="X90/Y65/PIOB" *) (* IO_TYPE="LVCMOS33" *)
+	TRELLIS_IO #(.DIR("INPUT")) a_buf (.B(a_pin), .O(a));
+	(* BEL="X0/Y23/PIOC" *) (* IO_TYPE="LVCMOS33" *)
+	TRELLIS_IO #(.DIR("OUTPUT")) led_buf (.B(led_pin), .I(led), .T(t));
+	(* BEL="X0/Y62/PIOD" *) (* IO_TYPE="LVCMOS33" *)
+	TRELLIS_IO #(.DIR("OUTPUT")) gpio0_buf (.B(gpio0_pin), .I(gpio0), .T(t));
+    assign led = !a;
+    wire t;
+    TRELLIS_SLICE #(.MODE("LOGIC"), .LUT0_INITVAL(16'h0000)) gnd (.F0(t));
+    TRELLIS_SLICE #(.MODE("LOGIC"), .LUT0_INITVAL(16'hFFFF)) vcc (.F0(gpio0));
+endmodule
diff --git a/ecp5/synth/ulx3s.ys b/ecp5/synth/ulx3s.ys
new file mode 100644
index 00000000..d741c985
--- /dev/null
+++ b/ecp5/synth/ulx3s.ys
@@ -0,0 +1,9 @@
+read_verilog ulx3s.v
+read_verilog -lib cells.v
+synth -top top
+abc -lut 4
+techmap -map simple_map.v
+splitnets
+opt_clean
+stat
+write_json ulx3s.json
diff --git a/ecp5/synth/ulx3s_empty.config b/ecp5/synth/ulx3s_empty.config
new file mode 100644
index 00000000..8b641943
--- /dev/null
+++ b/ecp5/synth/ulx3s_empty.config
@@ -0,0 +1,453 @@
+.device LFE5U-45F
+
+.comment Lattice Semiconductor Corporation Bitstream
+.comment Version:         Diamond (64-bit) 3.10.0.111.2
+.comment Bitstream Status: Final Version 10.25
+.comment Design name: wire_impl1.ncd
+.comment Architecture: sa5p00
+.comment Part: LFE5U-45F-6CABGA381
+.comment Date: Sun Jul  8 15:46:42 2018
+.comment Rows: 9470
+.comment Cols: 846
+.comment Bits: 8011620
+.comment Readback:     Off
+.comment Security:     Off
+.comment Bitstream CRC: 0x66BA
+
+.tile CIB_R10C3:PVT_COUNT2
+unknown: F2B0
+unknown: F3B0
+unknown: F5B0
+unknown: F11B0
+unknown: F13B0
+
+.tile CIB_R5C1:CIB_PLL1
+enum: CIB.JA3MUX 0
+enum: CIB.JB3MUX 0
+
+
+.tile CIB_R5C89:CIB_PLL1
+enum: CIB.JA3MUX 0
+enum: CIB.JB3MUX 0
+
+
+.tile CIB_R70C3:CIB_PLL3
+enum: CIB.JA3MUX 0
+enum: CIB.JB3MUX 0
+
+
+.tile CIB_R70C42:VCIB_DCU0
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C43:VCIB_DCUA
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C44:VCIB_DCUB
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C45:VCIB_DCUC
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C46:VCIB_DCUD
+enum: CIB.JA1MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C47:VCIB_DCUF
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C48:VCIB_DCU3
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C49:VCIB_DCU2
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C50:VCIB_DCUG
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C51:VCIB_DCUH
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C52:VCIB_DCUI
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C53:VCIB_DCU1
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+
+
+.tile CIB_R70C69:VCIB_DCU0
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C6:CIB_EFB0
+enum: CIB.JB3MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C70:VCIB_DCUA
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C71:VCIB_DCUB
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C72:VCIB_DCUC
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C73:VCIB_DCUD
+enum: CIB.JA1MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C74:VCIB_DCUF
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C75:VCIB_DCU3
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C76:VCIB_DCU2
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C77:VCIB_DCUG
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C78:VCIB_DCUH
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C79:VCIB_DCUI
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C7:CIB_EFB1
+enum: CIB.JA3MUX 0
+enum: CIB.JA4MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA6MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB4MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB6MUX 0
+enum: CIB.JC3MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC5MUX 0
+enum: CIB.JD3MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD5MUX 0
+
+
+.tile CIB_R70C80:VCIB_DCU1
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+
+
+.tile CIB_R70C87:CIB_PLL3
+enum: CIB.JA3MUX 0
+enum: CIB.JB3MUX 0
+
+
+.tile MIB_R10C40:CMUX_UL_0
+arc: G_DCS0CLK0 G_VPFN0000
+
+
+.tile MIB_R10C41:CMUX_UR_0
+arc: G_DCS0CLK1 G_VPFN0000
+
+
+.tile MIB_R58C40:CMUX_LL_0
+arc: G_DCS1CLK0 G_VPFN0000
+
+
+.tile MIB_R58C41:CMUX_LR_0
+arc: G_DCS1CLK1 G_VPFN0000
+
+
+.tile MIB_R71C4:EFB0_PICB0
+unknown: F54B1
+unknown: F56B1
+unknown: F82B1
+unknown: F94B1
+
+.tile MIB_R71C3:BANKREF8
+unknown: F18B0
+