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authorgatecat <gatecat@ds0.me>2021-04-30 13:29:21 +0100
committerGitHub <noreply@github.com>2021-04-30 13:29:21 +0100
commit0461cc8c3ac93bc525d35a15528c4711f244b9c6 (patch)
tree240de8f8603237a782a34df3a18915c495a394b3 /fpga_interchange/arch.cc
parentd718ccaa78763300146f0b8e5f2339b7fba97542 (diff)
parent5225550b5b83db2685f6c3ad3ce73e1eaadea891 (diff)
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Merge pull request #690 from YosysHQ/gatecat/interchange-wire-types
interchange: Add wire types
Diffstat (limited to 'fpga_interchange/arch.cc')
-rw-r--r--fpga_interchange/arch.cc19
1 files changed, 18 insertions, 1 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 441c2e1f..c49a172b 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -461,7 +461,24 @@ WireId Arch::getWireByName(IdStringList name) const
return ret;
}
-IdString Arch::getWireType(WireId wire) const { return id(""); }
+IdString Arch::getWireType(WireId wire) const
+{
+ int tile = wire.tile, index = wire.index;
+ if (tile == -1) {
+ // Nodal wire
+ const TileWireRefPOD &wr = chip_info->nodes[wire.index].tile_wires[0];
+ tile = wr.tile;
+ index = wr.index;
+ }
+ auto &w2t = chip_info->tiles[tile].tile_wire_to_type;
+ if (index >= w2t.ssize())
+ return IdString();
+ int wire_type = w2t[index];
+ if (wire_type == -1)
+ return IdString();
+ return IdString(chip_info->wire_types[wire_type].name);
+}
+
std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) const { return {}; }
// -----------------------------------------------------------------------