diff options
| author | gatecat <gatecat@ds0.me> | 2021-02-19 08:41:58 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-19 08:41:58 +0000 |
| commit | 5dcb59b13decab276ac736b0b06b4ccebcf83f62 (patch) | |
| tree | 67017806da1d36a6ec13fc538390b875b30309ab /fpga_interchange/examples/lut/lut.v | |
| parent | b4a97efe4da95084ba5585c48d20681f68742fd4 (diff) | |
| parent | c21e23b3eb6fee48c2b2da384b2dd0cd2d4ad91f (diff) | |
| download | nextpnr-5dcb59b13decab276ac736b0b06b4ccebcf83f62.tar.gz nextpnr-5dcb59b13decab276ac736b0b06b4ccebcf83f62.tar.bz2 nextpnr-5dcb59b13decab276ac736b0b06b4ccebcf83f62.zip | |
Merge pull request #576 from litghost/add_cell_bel_pin_mapping
Complete FPGA interchange Arch to the point where it can route a wire
Diffstat (limited to 'fpga_interchange/examples/lut/lut.v')
| -rw-r--r-- | fpga_interchange/examples/lut/lut.v | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/fpga_interchange/examples/lut/lut.v b/fpga_interchange/examples/lut/lut.v new file mode 100644 index 00000000..ca18e665 --- /dev/null +++ b/fpga_interchange/examples/lut/lut.v @@ -0,0 +1,5 @@ +module top(input i0, input i1, output o); + +assign o = i0 | i1; + +endmodule |