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| author | gatecat <gatecat@ds0.me> | 2021-02-19 08:41:58 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-19 08:41:58 +0000 |
| commit | 5dcb59b13decab276ac736b0b06b4ccebcf83f62 (patch) | |
| tree | 67017806da1d36a6ec13fc538390b875b30309ab /fpga_interchange/examples/lut/run.tcl | |
| parent | b4a97efe4da95084ba5585c48d20681f68742fd4 (diff) | |
| parent | c21e23b3eb6fee48c2b2da384b2dd0cd2d4ad91f (diff) | |
| download | nextpnr-5dcb59b13decab276ac736b0b06b4ccebcf83f62.tar.gz nextpnr-5dcb59b13decab276ac736b0b06b4ccebcf83f62.tar.bz2 nextpnr-5dcb59b13decab276ac736b0b06b4ccebcf83f62.zip | |
Merge pull request #576 from litghost/add_cell_bel_pin_mapping
Complete FPGA interchange Arch to the point where it can route a wire
Diffstat (limited to 'fpga_interchange/examples/lut/run.tcl')
| -rw-r--r-- | fpga_interchange/examples/lut/run.tcl | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/fpga_interchange/examples/lut/run.tcl b/fpga_interchange/examples/lut/run.tcl new file mode 100644 index 00000000..1edd8bb7 --- /dev/null +++ b/fpga_interchange/examples/lut/run.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog lut.v + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json build/lut.json |