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authorAlessandro Comodi <acomodi@antmicro.com>2021-03-23 20:35:53 +0100
committerAlessandro Comodi <acomodi@antmicro.com>2021-03-23 21:05:58 +0100
commit15e945aa1c83d5408f93e6375b38ec81deb4f874 (patch)
treeb4d4801916cb71352284657c0183d3685c4bb7e2 /fpga_interchange/examples/tests/wire/basys3.xdc
parent2956a0ca03d3e7e4573ed3f44de6fec23d33018e (diff)
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interchange: added boards and group testing across multiple boards
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Diffstat (limited to 'fpga_interchange/examples/tests/wire/basys3.xdc')
-rw-r--r--fpga_interchange/examples/tests/wire/basys3.xdc5
1 files changed, 5 insertions, 0 deletions
diff --git a/fpga_interchange/examples/tests/wire/basys3.xdc b/fpga_interchange/examples/tests/wire/basys3.xdc
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@@ -0,0 +1,5 @@
+set_property PACKAGE_PIN V17 [get_ports i]
+set_property PACKAGE_PIN U16 [get_ports o]
+
+set_property IOSTANDARD LVCMOS33 [get_ports i]
+set_property IOSTANDARD LVCMOS33 [get_ports o]