interchange: added boards and group testing across multiple boards

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

6 files changed, 8 insertions, 45 deletions

diff --git a/fpga_interchange/examples/tests/wire/CMakeLists.txt b/fpga_interchange/examples/tests/wire/CMakeLists.txt
index c7199475..7b6567ae 100644
--- a/fpga_interchange/examples/tests/wire/CMakeLists.txt
+++ b/fpga_interchange/examples/tests/wire/CMakeLists.txt
@@ -1,49 +1,7 @@
-add_interchange_test(
-    name wire_basys3
+add_interchange_group_test(
+    name wire
     family ${family}
-    device xc7a35t
-    package cpg236
+    board_list basys3 arty35t zybo arty100t nexys_video
     tcl run.tcl
-    xdc wire_basys3.xdc
-    sources wire.v
-)
-
-add_interchange_test(
-    name wire_arty_35t
-    family ${family}
-    device xc7a35t
-    package csg324
-    tcl run.tcl
-    xdc wire_arty.xdc
-    sources wire.v
-)
-
-add_interchange_test(
-    name wire_arty_100t
-    family ${family}
-    device xc7a100t
-    package csg324
-    tcl run.tcl
-    xdc wire_arty.xdc
-    sources wire.v
-)
-
-add_interchange_test(
-    name wire_nexys_video
-    family ${family}
-    device xc7a200t
-    package sbg484
-    tcl run.tcl
-    xdc wire_nexys_video.xdc
-    sources wire.v
-)
-
-add_interchange_test(
-    name wire_zybo
-    family ${family}
-    device xc7z010
-    package clg400
-    tcl run.tcl
-    xdc wire_zybo.xdc
     sources wire.v
 )
diff --git a/fpga_interchange/examples/tests/wire/wire_arty.xdc b/fpga_interchange/examples/tests/wire/arty100t.xdc
index 54c661c9..54c661c9 100644
--- a/fpga_interchange/examples/tests/wire/wire_arty.xdc
+++ b/fpga_interchange/examples/tests/wire/arty100t.xdc
diff --git a/fpga_interchange/examples/tests/wire/arty35t.xdc b/fpga_interchange/examples/tests/wire/arty35t.xdc
new file mode 100644
index 00000000..54c661c9
--- /dev/null
+++ b/fpga_interchange/examples/tests/wire/arty35t.xdc
@@ -0,0 +1,5 @@
+set_property PACKAGE_PIN A8 [get_ports i]
+set_property PACKAGE_PIN H5 [get_ports o]
+
+set_property IOSTANDARD LVCMOS33 [get_ports i]
+set_property IOSTANDARD LVCMOS33 [get_ports o]
diff --git a/fpga_interchange/examples/tests/wire/wire_basys3.xdc b/fpga_interchange/examples/tests/wire/basys3.xdc
index 317d5acc..317d5acc 100644
--- a/fpga_interchange/examples/tests/wire/wire_basys3.xdc
+++ b/fpga_interchange/examples/tests/wire/basys3.xdc
diff --git a/fpga_interchange/examples/tests/wire/wire_nexys_video.xdc b/fpga_interchange/examples/tests/wire/nexys_video.xdc
index 326f77cb..326f77cb 100644
--- a/fpga_interchange/examples/tests/wire/wire_nexys_video.xdc
+++ b/fpga_interchange/examples/tests/wire/nexys_video.xdc
diff --git a/fpga_interchange/examples/tests/wire/wire_zybo.xdc b/fpga_interchange/examples/tests/wire/zybo.xdc
index 072c19d2..072c19d2 100644
--- a/fpga_interchange/examples/tests/wire/wire_zybo.xdc
+++ b/fpga_interchange/examples/tests/wire/zybo.xdc