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authorDavid Shah <dave@ds0.me>2019-04-01 20:16:29 +0100
committerDavid Shah <dave@ds0.me>2019-04-02 15:30:01 +0100
commit32327b761ab8b8c438bd91d6c32f061ffaed3454 (patch)
tree22d0674b10e29634cf072058ae0bafcd3e2d9149 /generic/examples
parent6a383cd4c57db1f8bab6416daffdb24c0eb093c6 (diff)
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generic: Simple working example
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'generic/examples')
-rw-r--r--generic/examples/.gitignore1
-rw-r--r--generic/examples/README.md11
-rw-r--r--generic/examples/blinky.v9
-rw-r--r--generic/examples/report.py13
-rwxr-xr-xgeneric/examples/simple.sh4
-rw-r--r--generic/examples/simple.v15
6 files changed, 38 insertions, 15 deletions
diff --git a/generic/examples/.gitignore b/generic/examples/.gitignore
new file mode 100644
index 00000000..83d79a7d
--- /dev/null
+++ b/generic/examples/.gitignore
@@ -0,0 +1 @@
+blinky.txt
diff --git a/generic/examples/README.md b/generic/examples/README.md
new file mode 100644
index 00000000..5eb0ea72
--- /dev/null
+++ b/generic/examples/README.md
@@ -0,0 +1,11 @@
+# Generic Architecture Example
+
+This contains a simple, artificial, example of the nextpnr generic API.
+
+ - simple.py procedurally generates a simple FPGA architecture with IO at the edges,
+ logic slices in all other tiles, and interconnect only between adjacent tiles
+
+ - report.py stores design information after place-and-route to blinky.txt in place
+ of real bitstream generation
+
+ - Run blinky.sh to build an example design on the FPGA above \ No newline at end of file
diff --git a/generic/examples/blinky.v b/generic/examples/blinky.v
new file mode 100644
index 00000000..b7cb1b86
--- /dev/null
+++ b/generic/examples/blinky.v
@@ -0,0 +1,9 @@
+module top(input clk, output reg [7:0] leds);
+
+reg [25:0] ctr;
+always @(posedge clk)
+ ctr <= ctr + 1'b1;
+
+assign leds = ctr[25:18];
+
+endmodule \ No newline at end of file
diff --git a/generic/examples/report.py b/generic/examples/report.py
new file mode 100644
index 00000000..c43367fa
--- /dev/null
+++ b/generic/examples/report.py
@@ -0,0 +1,13 @@
+with open("blinky.txt", "w") as f:
+ for nname, net in ctx.nets:
+ print("# Net %s" % nname, file=f)
+ # FIXME: Pip ordering
+ for wire, pip in net.wires:
+ if pip.pip != "":
+ print("%s" % pip.pip, file=f)
+ print("", file=f)
+ for cname, cell in ctx.cells:
+ print("# Cell %s at %s" % (cname, cell.bel), file=f)
+ for param, val in cell.params:
+ print("%s.%s %s" % (cell.bel, param, val), file=f)
+ print("", file=f) \ No newline at end of file
diff --git a/generic/examples/simple.sh b/generic/examples/simple.sh
new file mode 100755
index 00000000..ed800639
--- /dev/null
+++ b/generic/examples/simple.sh
@@ -0,0 +1,4 @@
+#!/usr/bin/bash
+set -ex
+yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v
+../../nextpnr-generic --pre-pack simple.py --json blinky.json --post-route report.py \ No newline at end of file
diff --git a/generic/examples/simple.v b/generic/examples/simple.v
deleted file mode 100644
index 6d337101..00000000
--- a/generic/examples/simple.v
+++ /dev/null
@@ -1,15 +0,0 @@
-(* blackbox *)
-module SLICE_LUT4(
- input I0, I1, I2, I3,
- input CLK,
- output Q
-);
-parameter INIT = 16'h0000;
-parameter FF_USED = 1'b0;
-endmodule
-
-module top(input a, output q);
-
-SLICE_LUT4 sl_i(.I0(a), .Q(q));
-
-endmodule \ No newline at end of file