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* generic: Use arch_pybindings_sharedgatecat2022-07-042-105/+18
* Merge pull request #1000 from YosysHQ/gatecat/fix-empty-portsmyrtle2022-06-261-9/+9
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| * ice40: Fix accidental creation of empty portsgatecat2022-06-251-9/+9
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* Merge pull request #997 from Chandler-Kluser/mastermyrtle2022-06-231-1/+2
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| * Update README.mdChandler Klüser2022-06-221-1/+2
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* Disable broken and failing interchange CIgatecat2022-06-211-0/+0
* clangformatgatecat2022-06-121-1/+1
* ecp5: Bind write_bitstream to Pythongatecat2022-06-091-0/+3
* Merge pull request #996 from yrabbit/snmyrtle2022-06-091-7/+11
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| * gowin: Use local aliasesYRabbit2022-06-091-7/+11
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* Merge pull request #993 from yrabbit/lw-wip-1myrtle2022-06-075-8/+299
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| * gowin: Add support for long wiresYRabbit2022-05-275-8/+299
* | Merge pull request #992 from antmicro/mdudek/nexus_write_dccmyrtle2022-05-271-3/+2
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| * | Change write_dcc to work with tilegroups from prjoxideMaciej Dudek2022-05-271-3/+2
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* | Merge pull request #990 from YosysHQ/gatecat/fix-988myrtle2022-05-221-5/+0
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| * | Don't assert on mixed domain paths in reportgatecat2022-05-221-5/+0
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* | Merge pull request #989 from YosysHQ/lofty/cmake-bumpmyrtle2022-05-211-1/+1
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| * Bump minimum CMake to 3.13Lofty2022-05-211-1/+1
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* Merge pull request #985 from antmicro/interchange-lut-constantsmyrtle2022-05-135-58/+180
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| * Added fallback to VCC as the preferred constant if the architecture does not ...Maciej Kurc2022-05-123-6/+20
| * Added tying unused LUT pins to preferred constant instead of VccMaciej Kurc2022-05-111-2/+8
| * Generalized representation of unused LUT pins connectionsMaciej Kurc2022-05-115-58/+160
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* Merge pull request #984 from yrabbit/assertmyrtle2022-05-101-1/+1
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| * common: Correct a minor typo in the messageYRabbit2022-05-101-1/+1
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* Merge pull request #982 from YosysHQ/gatecat/ice40-gb-constr-fixmyrtle2022-05-081-7/+24
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| * ice40: Fix propagation of constraints through SB_GBgatecat2022-05-081-7/+24
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* Merge pull request #981 from yrabbit/lw-cst-0gatecat2022-05-031-7/+27
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| * gowin: Add initial syntax support for long wiresYRabbit2022-05-021-7/+27
* | generic: Add some extra helpers for viaduct uarchesgatecat2022-05-024-4/+52
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* generic: Add missing uarch guardgatecat2022-04-271-1/+2
* ecp5: Tweak delay predictiongatecat2022-04-201-1/+1
* Merge pull request #977 from YosysHQ/gatecat/prefine-tileswapgatecat2022-04-192-1/+100
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| * prefine: Do full-tile swaps, toogatecat2022-04-192-1/+100
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* Merge pull request #976 from YosysHQ/gatecat/dp-reworkgatecat2022-04-175-545/+730
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| * Move general parallel detail place code out of parallel_refinegatecat2022-04-175-545/+730
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* Merge pull request #975 from YosysHQ/gatecat/ice40-carry-i3-fixgatecat2022-04-121-34/+45
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| * ice40: Avoid chain finder from mixing up chains by only allowing I3 chaining ...gatecat2022-04-111-34/+45
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* Merge pull request #974 from YosysHQ/gatecat/ci-restructuregatecat2022-04-0816-125/+301
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| * ci: Restructure and move entirely to GH actions from Cirrusgatecat2022-04-0816-125/+301
* | Merge pull request #973 from YosysHQ/gatecat/folder-tidygatecat2022-04-0875-3/+6
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| * Split up common into kernel,place,routegatecat2022-04-0875-3/+6
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* Merge pull request #972 from YosysHQ/gatecat/ecp5-split-slice-v2gatecat2022-04-0713-1349/+1137
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| * ecp5: Split the SLICE bel into separate LUT/FF/RAMW belsgatecat2022-04-0713-1349/+1137
* | Merge pull request #971 from modwizcode/fix-tbb-macosgatecat2022-04-061-1/+1
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| * cmake: properly include TBB libraries.Irides2022-04-051-1/+1
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* generic: Allow bel pins without wiresgatecat2022-04-041-3/+6
* Merge pull request #970 from yrabbit/nr9-wipgatecat2022-04-034-2/+40
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| * gowin: handle the GW1N-9 feature.YRabbit2022-04-034-2/+40
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* clangformatgatecat2022-03-313-12/+12
* Merge pull request #969 from YosysHQ/gatecat/ice40-wirename-fixgatecat2022-03-311-1/+1
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