| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge pull request #713 from YosysHQ/gatecat/version-bump | gatecat | 2021-05-27 | 2 | -1/+1 |
| |\ | | | | | interchange: Bump versions | ||||
| | * | interchange: Bump versions | gatecat | 2021-05-27 | 2 | -1/+1 |
| |/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Merge pull request #686 from YosysHQ/gatecat/interchange-macro | gatecat | 2021-05-21 | 14 | -4/+414 |
| |\ | | | | | interchange: Add macro expansion | ||||
| | * | interchange: Bump versions | gatecat | 2021-05-21 | 2 | -1/+1 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | interchange: Add macro parameter mapping | gatecat | 2021-05-21 | 2 | -3/+53 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | interchange: Don't error out on missing cell ports | gatecat | 2021-05-21 | 2 | -2/+3 |
| | | | | | | | | | | | | | | | This is required for LUTRAM support, as the upper address bits of RAMD64E etc are missing for shallower primitives. Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | interchange: Add LUTRAM test | gatecat | 2021-05-21 | 6 | -0/+169 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | interchange: Preliminary implementation of macro expansion | gatecat | 2021-05-21 | 3 | -0/+116 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | interchange: Add macro param map rules to chipdb | gatecat | 2021-05-21 | 1 | -0/+24 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | interchange: Add macro data to chipdb | gatecat | 2021-05-21 | 1 | -1/+51 |
| |/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Merge pull request #712 from YosysHQ/gatecat/rr-heatmap | gatecat | 2021-05-21 | 6 | -3/+64 |
| |\ | | | | | router2: Add heatmap by routing resource type | ||||
| | * | router2: Add heatmap by routing resource type | gatecat | 2021-05-20 | 6 | -3/+64 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | Merge pull request #711 from acomodi/interchange-site-to-pseudo-pips | gatecat | 2021-05-20 | 3 | -4/+29 |
| |\ \ | |/ |/| | interchange: phys: add site instance idstr for pseudo tile PIPs | ||||
| | * | gh-actions: interchange: use commit sha as cache key | Alessandro Comodi | 2021-05-20 | 1 | -4/+10 |
| | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| | * | bump interchange schema | Alessandro Comodi | 2021-05-20 | 1 | -0/+0 |
| | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| | * | interchange: phys: add site instance idstr for pseudo tile PIPs | Alessandro Comodi | 2021-05-19 | 1 | -0/+19 |
| |/ | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | Run clangformat | gatecat | 2021-05-16 | 3 | -6/+8 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Merge pull request #708 from Ravenslofty/mistral-getchipname | gatecat | 2021-05-15 | 1 | -1/+1 |
| |\ | | | | | mistral: add getChipName | ||||
| | * | mistral: add getChipName | Lofty | 2021-05-15 | 1 | -1/+1 |
| |/ | | | | Signed-off-by: Lofty <dan.ravensloft@gmail.com> | ||||
| * | Merge pull request #707 from gatecat/cyclonev | gatecat | 2021-05-15 | 31 | -9/+4222 |
| |\ | | | | | mistral: Initial Cyclone V support | ||||
| | * | Update README | gatecat | 2021-05-15 | 1 | -0/+1 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Add MISTRAL_CLKBUF cell type | gatecat | 2021-05-15 | 5 | -1/+15 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | ci: Use GH only for Mistral and fpga-interchange | gatecat | 2021-05-15 | 3 | -2/+58 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Tidying up | gatecat | 2021-05-15 | 12 | -12/+13 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Make router2 the default | gatecat | 2021-05-15 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | router2: Hacky workaround for slow Cyclone V convergence | gatecat | 2021-05-15 | 1 | -3/+3 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Speed up bel binding and checking | gatecat | 2021-05-15 | 1 | -4/+18 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Workaround for weird SCLR issue | gatecat | 2021-05-15 | 1 | -0/+7 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Fix ENA and ACLR bitstream generation | gatecat | 2021-05-15 | 4 | -4/+11 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Disable global buffers that are currently broken | gatecat | 2021-05-15 | 1 | -0/+2 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | router2: Reduce verbosity when debugging | gatecat | 2021-05-15 | 1 | -0/+2 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Compensate for EF_SEL mirroring in validity check | gatecat | 2021-05-15 | 1 | -2/+2 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Fix EF_SEL and BTO_DIS | gatecat | 2021-05-15 | 2 | -4/+5 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: PKREG bits appear to be mirrored within a half? | gatecat | 2021-05-15 | 1 | -2/+3 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Debugging flipflops | gatecat | 2021-05-15 | 1 | -3/+4 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Trim SDATA if SLOAD is low | gatecat | 2021-05-15 | 1 | -0/+9 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: FF&CLKBUF fixes, part 1 | gatecat | 2021-05-15 | 2 | -1/+10 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: First pass at FF and CLKBUF bitgen | gatecat | 2021-05-15 | 2 | -18/+115 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Account for TD input count limit | gatecat | 2021-05-15 | 4 | -9/+128 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | msitral: Fix pip iterator Python bindings | gatecat | 2021-05-15 | 1 | -2/+2 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Implement PIP locations, too | gatecat | 2021-05-15 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Implement bounding boxes for router2 | gatecat | 2021-05-15 | 2 | -1/+15 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Debugging carry chain issues | gatecat | 2021-05-15 | 2 | -13/+34 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Adding FF control set reservation | gatecat | 2021-05-15 | 3 | -58/+148 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Carry fixes | gatecat | 2021-05-15 | 2 | -3/+16 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Carry debugging | gatecat | 2021-05-15 | 3 | -41/+11 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Write arith mode to bitstream (not yet functional) | gatecat | 2021-05-15 | 2 | -2/+18 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: First pass at carry packing | gatecat | 2021-05-15 | 4 | -8/+82 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: FF validity checking fixes | gatecat | 2021-05-15 | 1 | -7/+13 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | mistral: Fix constant trimming | gatecat | 2021-05-15 | 2 | -1/+2 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
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index : iCE40/nextpnr | |
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