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path: root/ecp5/arch.h
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* Merge remote-tracking branch 'origin/master' into mmicko/ecp5_guiMiodrag Milanovic2019-12-281-1/+7
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| * ecp5: Fix 25k DDRDLLA bitstream genDavid Shah2019-11-291-1/+1
| * ecp5: Add an error for out-of-sync constids and bbaDavid Shah2019-10-261-0/+1
| * ecp5: Fix routing to shared DSP control inputsDavid Shah2019-10-251-0/+5
* | set wire active flagMiodrag Milanovic2019-10-201-0/+2
* | Start adding visible wiresMiodrag Milanovic2019-10-201-5/+2
* | Added type to wireMiodrag Milanovic2019-10-201-1/+8
* | Draw swbox, smaller slices, proper ioMiodrag Milanovic2019-10-201-7/+7
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* ecp5: Add full part name to bitstream headerDavid Shah2019-08-271-0/+1
* ecp5: Add GSR/SGSR supportDavid Shah2019-08-271-0/+4
* ecp5: Delay tweaking for lower speed gradesDavid Shah2019-06-211-1/+1
* Add --placer option and refactor placer selectionDavid Shah2019-03-241-0/+3
* clangformatDavid Shah2019-03-221-12/+15
* ecp5: Speedup cell delay lookupsDavid Shah2019-03-221-0/+23
* ecp5: Increase ripup penaltyDavid Shah2019-02-251-1/+1
* ecp5: Add criticality-based LUT permutationDavid Shah2019-02-251-0/+2
* ecp5: Delay tuningDavid Shah2019-02-251-1/+1
* ecp5: Router performance improvementsDavid Shah2019-02-251-1/+1
* ecp5: Helper functions for DQS and ECLKDavid Shah2019-02-241-0/+4
* ecp5: Add DQS groupings to databaseDavid Shah2019-02-241-1/+1
* Load chipdb from filesystem as optionMiodrag Milanovic2019-02-091-1/+1
* ecp5: Adding DTR, OSCG, CLKDIVF, USRMCLK, JTAGGDavid Shah2019-02-081-0/+11
* ecp5: clangformat timing changesDavid Shah2018-11-161-4/+6
* ecp5: Fix db import, improve timing data debuggingDavid Shah2018-11-161-0/+1
* ecp5: Consider fanout when calculating pip delaysDavid Shah2018-11-161-2/+12
* ecp5: Use new timing dataDavid Shah2018-11-161-15/+17
* ecp5: Adding real timing data to databaseDavid Shah2018-11-161-5/+56
* Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-131-0/+4
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| * clangformatClifford Wolf2018-11-111-8/+2
| * Add getConflictingWireWire() arch API, streamline getConflictingXY semanticClifford Wolf2018-11-111-5/+10
| * Add getConflictingPipWire() arch API, router1 improvementsClifford Wolf2018-11-111-0/+5
* | ecp5: Update arch to new timing APIDavid Shah2018-11-121-2/+10
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* ecp5: Separate global promotion and routingDavid Shah2018-10-311-1/+1
* ecp5: Adding LPF parserDavid Shah2018-10-311-0/+3
* ecp5: Add support for correct tile naming in all variantsDavid Shah2018-10-161-0/+6
* clangformatDavid Shah2018-09-291-1/+0
* ecp5: Import SPINE data to databaseDavid Shah2018-09-291-0/+2
* ecp5: Helper function and arch tweaks for global routerDavid Shah2018-09-291-0/+23
* ecp5: Add crude approximation of Pip delaysDavid Shah2018-08-191-1/+1
* Merge pull request #54 from daveshah1/ecp5_speedupDavid Shah2018-08-191-16/+20
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| * ecp5: Flatten bel_to_cell for performanceDavid Shah2018-08-181-22/+18
| * ecp5: Speed up Bel availability/binding checksDavid Shah2018-08-181-5/+11
| * ecp5: Speedup placement using ArchCellInfoDavid Shah2018-08-181-0/+2
* | Add Arch attrs APIClifford Wolf2018-08-141-0/+18
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* ecp5: Implement getPipLocation and related APIDavid Shah2018-08-091-1/+11
* Merge branch 'master' of github.com:YosysHQ/nextpnr into constidsClifford Wolf2018-08-081-4/+3
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| * Merge pull request #44 from YosysHQ/improve_timing_specDavid Shah2018-08-081-4/+2
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| | * Arch API: Removing Arch::isIOCellDavid Shah2018-08-081-2/+0
| | * Arch API: New specification for timing port classesDavid Shah2018-08-081-4/+2
| | * Add Arch::isIOCell() to ecp5 and genericEddie Hung2018-08-061-0/+2
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