Commit message (Collapse) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | ecp5: Fix derivation of OSCG timing constraint | David Shah | 2020-06-29 | 1 | -1/+5 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Disconnect dedicated DCU inputs if connected to constants | David Shah | 2020-05-14 | 1 | -0/+12 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Further condense | Ross Schlaikjer | 2020-04-29 | 1 | -11/+10 |
| | |||||
* | Dedupe clock error check | Ross Schlaikjer | 2020-04-29 | 1 | -12/+13 |
| | |||||
* | Issue warning for mixed-mode inputs | Ross Schlaikjer | 2020-04-29 | 1 | -13/+34 |
| | |||||
* | Alter MULT18X18D timing db based on register config | Ross Schlaikjer | 2020-04-28 | 1 | -0/+35 |
| | | | | | | | | | | | | | | | If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should use the faster setup/hold timings for the 18x8 multiplier. Similarly, check the value of REG_OUTPUT_CLK for whether or not to use faster timings for the output. This is based on how I currently understand the registers to work - if anyone knows the actual rules for when each timing applies please do chime in to correct this implementation if necessary. Along the same lines, this PR does not address the case when the pipeline registers are enabled, since it is not clear to me how exactly that affects the timing. | ||||
* | Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-database | David Shah | 2020-04-07 | 1 | -0/+23 |
|\ | | | | | Add support for REGMODE to DP16KD | ||||
| * | No need to fetch context | Ross Schlaikjer | 2020-04-07 | 1 | -3/+2 |
| | | |||||
| * | Change assert to error | Ross Schlaikjer | 2020-04-07 | 1 | -2/+5 |
| | | |||||
| * | Rearrange bool algebra | Ross Schlaikjer | 2020-04-07 | 1 | -2/+2 |
| | | |||||
| * | Actually just move all the logic to ArchInfo | Ross Schlaikjer | 2020-04-07 | 1 | -2/+13 |
| | | |||||
| * | Extract regmode configuration to ArchInfo | Ross Schlaikjer | 2020-04-07 | 1 | -0/+10 |
| | | |||||
* | | ecp5: Allow use of IDDRXN and ODDRXN type primitives on the same pin | David Shah | 2020-04-03 | 1 | -0/+10 |
|/ | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Fix tieoff of unused DELAY signals | David Shah | 2020-01-21 | 1 | -3/+3 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add support for flipflops with preload | David Shah | 2019-12-07 | 1 | -2/+6 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Fix placement of DDRDLLA | David Shah | 2019-11-29 | 1 | -0/+26 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Improve flipflop packing density | David Shah | 2019-11-20 | 1 | -0/+153 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Fix handling of custom DEL_VALUE | David Shah | 2019-11-18 | 1 | -1/+2 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add logic utilisation before packing statistics | David Shah | 2019-11-18 | 1 | -0/+45 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge pull request #345 from YosysHQ/dave/sdf | David Shah | 2019-11-18 | 1 | -11/+3 |
|\ | | | | | Improve handling of top level IO and add SDF support | ||||
| * | ecp5: Preserve top level IO properly | David Shah | 2019-10-18 | 1 | -11/+3 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ecp5: Copy timing constraints across ECLKBRIDGECS | David Shah | 2019-11-01 | 1 | -1/+4 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ecp5: Fix placement of ECLKBRIDGECS | David Shah | 2019-11-01 | 1 | -11/+41 |
|/ | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add support for ECLKBRIDGECS | David Shah | 2019-10-11 | 1 | -1/+52 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Fix tristate IO registers | David Shah | 2019-10-09 | 1 | -3/+9 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add support for IO registers | David Shah | 2019-10-09 | 1 | -0/+97 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add IDDR71B support | David Shah | 2019-10-09 | 1 | -3/+15 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add ODDR71B support | David Shah | 2019-10-09 | 1 | -3/+14 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Fix parameters | David Shah | 2019-10-04 | 1 | -0/+4 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Adding support for 36-bit wide PDP RAMs | David Shah | 2019-10-01 | 1 | -0/+53 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Move clock constraints across IO and DCCA | David Shah | 2019-09-13 | 1 | -0/+9 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add GSR/SGSR support | David Shah | 2019-08-27 | 1 | -0/+11 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add --out-of-context for building hard macros | David Shah | 2019-08-07 | 1 | -1/+7 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add a check for legacy parameter values | David Shah | 2019-08-06 | 1 | -0/+12 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: New Property interface | David Shah | 2019-08-05 | 1 | -62/+66 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Fix missing LUT inputs, fixes #301 | David Shah | 2019-07-10 | 1 | -0/+4 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Use flags for each step | Miodrag Milanovic | 2019-06-14 | 1 | -1/+1 |
| | |||||
* | Save top level attrs and store current step | Miodrag Milanovic | 2019-06-07 | 1 | -0/+1 |
| | |||||
* | ecp5: Use an attribute to store is_global | David Shah | 2019-06-07 | 1 | -2/+6 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | WIP saving/loading attributes | Miodrag Milanovic | 2019-06-07 | 1 | -0/+1 |
| | |||||
* | Added support for attributes/properties types | Miodrag Milanovic | 2019-06-01 | 1 | -1/+1 |
| | |||||
* | ecp5: Fix USRMCLK primitive | David Shah | 2019-05-10 | 1 | -0/+14 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: DELAY fixes | David Shah | 2019-02-25 | 1 | -11/+10 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Improve packing density | David Shah | 2019-02-25 | 1 | -0/+58 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add criticality-based LUT permutation | David Shah | 2019-02-25 | 1 | -0/+1 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Speed up timing analysis | David Shah | 2019-02-25 | 1 | -0/+3 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: DELAYF/G fixes | David Shah | 2019-02-24 | 1 | -2/+2 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Connect unused DQSBUF inputs to GND | David Shah | 2019-02-24 | 1 | -14/+30 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | ecp5: Compute derived constraints iteratively | David Shah | 2019-02-24 | 1 | -52/+79 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | ecp5: Derived constraint support for PLLs, clock dividers and oscillators | David Shah | 2019-02-24 | 1 | -0/+115 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> |