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* ecp5: Fix invalid accesses during certain IO packing casesgatecat2023-04-121-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2023-03-161-66/+42
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1090 from rowanG077/ecp5-propagate-dcsc-clk-ctmyrtle2023-02-131-12/+156
|\ | | | | ecp5: Propagate clock constraints through DCSC
| * streamline constant_net detectionrowanG0772023-02-061-2/+4
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| * ecp5: DSCS clock propagation if modesel is 0 constantrowanG0772023-02-061-52/+99
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| * ecp5: Propagate clock constraints through DSCSrowanG0772023-02-011-12/+107
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* | ecp5: Handle the case where both CE are the same constantgatecat2023-02-091-2/+8
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Improve IOFF CE handling robustnessgatecat2023-01-251-8/+24
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Remove deprecated functionsMiodrag Milanovic2022-12-221-3/+3
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* refactor: Use IdString::in instead of || chainsgatecat2022-08-101-23/+18
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-101-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Split the SLICE bel into separate LUT/FF/RAMW belsgatecat2022-04-071-874/+527
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* ecp5: Fix double-counting of FFs in reportgatecat2022-03-161-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #925 from YosysHQ/gatecat/netlist-ivgatecat2022-03-011-31/+25
|\ | | | | Switch to potentially-sparse net users array
| * Switch to potentially-sparse net users arraygatecat2022-02-271-31/+25
| | | | | | | | | | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me>
* | ecp5: Fix PDPW16K clock param renaminggatecat2022-02-281-1/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New member functions to replace design_utilsgatecat2022-02-181-150/+149
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use constids instead of id("..")gatecat2022-02-161-452/+431
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New NetInfo and CellInfo constructorsgatecat2022-02-161-39/+19
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* ecp5: LUT permutation supportgatecat2021-12-131-1/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Fix packing of IOFF with IODELAYsgatecat2021-11-051-1/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fix mistype.YRabbit2021-09-291-1/+1
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* clangformatgatecat2021-08-241-5/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Make EXTREFB handling more robustAidan Klein2021-08-181-6/+44
| | | | | Avoids a segfault if an EXTREFB does not connect directly to its associated DCUA. Also adds location constraints specifically for EXTREFB.
* ecp5: Copy REGMODE in PDP mode to both A and B portsgatecat2021-08-021-1/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fixing old emails and names in copyrightsgatecat2021-06-121-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Using hashlib in archesgatecat2021-06-021-15/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib for core netlist structuresgatecat2021-06-021-61/+61
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Use new cluster APIgatecat2021-05-061-18/+24
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2021-04-301-40/+30
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add check_alu to Ecp5PackerAdam Greig2021-04-291-15/+123
| | | | | | | | | | | Checks that every ALU54B is correctly connected to two MULT18X18Ds: * SIGNEDIA and SIGNEDIB connected to SIGNEDP * MA and MB connected to P * A and B connected to {ROA, ROB} Diamond enforces these requirements; the connections are fixed in any event so no other connection is possible.
* Add relative constraints to position MULT18X18D near connected ALU54B.Adam Greig2021-04-291-0/+24
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* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-17/+17
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Use snake case for arch-specific functionsD. Shah2021-02-031-6/+7
| | | | | | | This makes the difference clearer between the general arch API that everyone must implement; and helper functions specific to one arch. Signed-off-by: D. Shah <dave@ds0.me>
* refactor: Replace getXName().c_str(ctx) with ctx->nameOfXD. Shah2021-02-021-1/+1
| | | | | | This makes the ongoing migration to IdStringList easier. Signed-off-by: D. Shah <dave@ds0.me>
* ecp5: Proof-of-concept using IdStringList for bel namesD. Shah2021-02-021-25/+21
| | | | | | | | | | | This uses the new IdStringList API to store bel names for the ECP5. Note that other arches and the GUI do not yet build with this proof-of-concept patch. getBelByName still uses the old implementation and could be more efficiently implemented with further development. Signed-off-by: D. Shah <dave@ds0.me>
* cleanup: Spelling fixesD. Shah2021-01-281-1/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* ecp5: Fix some tricky ECLKSYNCB/CLKDIVF packing casesDavid Shah2020-10-091-0/+64
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #489 from YosysHQ/dave/ecp5-fix-ioddrx2David Shah2020-08-131-8/+8
|\ | | | | ecp5: Fix how ODDRX2 SCLK/RST are set
| * ecp5: Fix how ODDRX2 SCLK/RST are setDavid Shah2020-08-131-8/+8
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Run fixupHierarchy after packingDavid Shah2020-08-121-0/+1
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix derivation of OSCG timing constraintDavid Shah2020-06-291-1/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Disconnect dedicated DCU inputs if connected to constantsDavid Shah2020-05-141-0/+12
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Further condenseRoss Schlaikjer2020-04-291-11/+10
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* Dedupe clock error checkRoss Schlaikjer2020-04-291-12/+13
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* Issue warning for mixed-mode inputsRoss Schlaikjer2020-04-291-13/+34
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* Alter MULT18X18D timing db based on register configRoss Schlaikjer2020-04-281-0/+35
| | | | | | | | | | | | | | | If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should use the faster setup/hold timings for the 18x8 multiplier. Similarly, check the value of REG_OUTPUT_CLK for whether or not to use faster timings for the output. This is based on how I currently understand the registers to work - if anyone knows the actual rules for when each timing applies please do chime in to correct this implementation if necessary. Along the same lines, this PR does not address the case when the pipeline registers are enabled, since it is not clear to me how exactly that affects the timing.
* Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-databaseDavid Shah2020-04-071-0/+23
|\ | | | | Add support for REGMODE to DP16KD
| * No need to fetch contextRoss Schlaikjer2020-04-071-3/+2
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| * Change assert to errorRoss Schlaikjer2020-04-071-2/+5
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