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ecp5
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Author
Age
Files
Lines
*
Fix MESSAGE indicating where externally-built .bbas live.
William D. Jones
2020-08-22
1
-1
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+1
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Merge pull request #489 from YosysHQ/dave/ecp5-fix-ioddrx2
David Shah
2020-08-13
1
-8
/
+8
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ecp5: Fix how ODDRX2 SCLK/RST are set
David Shah
2020-08-13
1
-8
/
+8
*
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ecp5: Run fixupHierarchy after packing
David Shah
2020-08-12
1
-0
/
+1
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Initial conversion to pybind11
Miodrag Milanovic
2020-07-23
1
-18
/
+16
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ecp5: Add a warning for unknown LPF IOBUF attrs
David Shah
2020-07-13
1
-0
/
+8
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ecp5: Add SYSCONFIG settings to bitstream
David Shah
2020-07-12
4
-3
/
+38
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ecp5: Add parsing of SYSCONFIG line in LPF
David Shah
2020-07-12
1
-1
/
+20
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Merge pull request #463 from YosysHQ/fix-archcheck
David Shah
2020-07-02
1
-2
/
+3
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ecp5: Fix getTileBelDimZ
David Shah
2020-06-29
1
-2
/
+3
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CMake: improve logic for discovering Trellis.
whitequark
2020-07-01
1
-1
/
+25
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CMake: fix path checks in chipdb build scripts.
whitequark
2020-07-01
1
-2
/
+2
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ecp5: Fix derivation of OSCG timing constraint
David Shah
2020-06-29
1
-1
/
+5
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Fix clangformat and execute it
Miodrag Milanovic
2020-06-27
1
-12
/
+8
*
Update git ignore locations
Miodrag Milanovic
2020-06-27
1
-1
/
+1
*
Merge pull request #460 from whitequark/better-embed
David Shah
2020-06-26
8
-109
/
+66
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Simplify and improve chipdb embedding/loading.
whitequark
2020-06-26
8
-109
/
+66
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Fix typo
whitequark
2020-06-25
1
-1
/
+1
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/
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CMake: require at least version 3.5 (Ubuntu 16.04).
whitequark
2020-06-25
1
-1
/
+1
*
CMake: rewrite chipdb handling from ground up.
whitequark
2020-06-25
6
-119
/
+151
*
ecp5: Fix placement of DCCs to guarantee routeability
David Shah
2020-06-10
1
-2
/
+44
*
Merge pull request #447 from whitequark/wasi
David Shah
2020-05-24
2
-8
/
+18
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Port nextpnr-{ice40,ecp5} to WASI.
whitequark
2020-05-23
2
-8
/
+18
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Merge pull request #440 from YosysHQ/lattice-fixes
David Shah
2020-05-18
3
-0
/
+28
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ecp5: Disconnect dedicated DCU inputs if connected to constants
David Shah
2020-05-14
1
-0
/
+12
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ecp5: Improve global routing robustness
David Shah
2020-05-14
1
-0
/
+11
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*
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ecp5: Don't promote VCC/GND to globals even if connected to clock port
David Shah
2020-05-14
1
-0
/
+2
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*
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lpf: Support // comments
David Shah
2020-05-14
1
-0
/
+3
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*
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clangformat
David Shah
2020-05-16
1
-1
/
+2
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Merge pull request #442 from nategraff-sifive/fix-unsupported-spelling
David Shah
2020-05-14
1
-5
/
+5
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Fix spelling of 'unsupported'
Nathaniel Graff
2020-05-13
1
-5
/
+5
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ecp5: Allow setting drive strength for LVCMOS33D IOs
Mike Walters
2020-05-12
1
-0
/
+19
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ecp5: MULT18X18D timing fixes
David Shah
2020-05-01
1
-10
/
+26
*
No cell delay for clocked MULT18X18D
Ross Schlaikjer
2020-04-30
1
-0
/
+2
*
Further condense
Ross Schlaikjer
2020-04-29
1
-11
/
+10
*
Dedupe clock error check
Ross Schlaikjer
2020-04-29
1
-12
/
+13
*
Issue warning for mixed-mode inputs
Ross Schlaikjer
2020-04-29
3
-40
/
+46
*
Handle register timing case
Ross Schlaikjer
2020-04-29
1
-6
/
+58
*
Use registered port class on mult18x18
Ross Schlaikjer
2020-04-29
1
-3
/
+5
*
Alter MULT18X18D timing db based on register config
Ross Schlaikjer
2020-04-28
3
-2
/
+43
*
ecp5: Fix CSDECODE bitgen
David Shah
2020-04-15
1
-0
/
+3
*
ecp5: Use dedicated routing for ECLKs where possible
David Shah
2020-04-14
1
-1
/
+80
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Add TRELLIS_PROGRAM_PREFIX
Miodrag Milanovic
2020-04-11
1
-4
/
+6
*
ecp5: Fix routing bitgen for non-SERDES 'VCIB' tiles
David Shah
2020-04-10
1
-3
/
+12
*
ecp5: Make hysteresis default-on for LVCMOS33 bidir as well as input
David Shah
2020-04-09
1
-9
/
+7
*
Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-database
David Shah
2020-04-07
3
-4
/
+33
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No need to fetch context
Ross Schlaikjer
2020-04-07
1
-3
/
+2
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Change assert to error
Ross Schlaikjer
2020-04-07
1
-2
/
+5
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Rearrange bool algebra
Ross Schlaikjer
2020-04-07
1
-2
/
+2
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Actually just move all the logic to ArchInfo
Ross Schlaikjer
2020-04-07
3
-19
/
+23
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